Sharp MZ-3500 User Manual

MZ-3500

SERVICE MANUAL

CODE; OOZMZ 3500SM/E

PERSONAL COMPUTER

MODEL MZ-3500

CONTENTS

1. Specifications........................................................................................................................................................................... 1

2. Software (Memory) Configuration ........................................................................................................................................... 7

3. CPU and memory .................................................................................................................................................................. 12

4. CRT display............................................................................................................................................................................ 25

5. MFD interface ........................................................................................................................................................................ 52

6. R232C interface....................................................................................................................................................................... 72

7. Printer interface ....................................................................................................................................................................... 78

8. Other interface....................................................................................................................................................................... 81

9. Power circuit discription......................................................................................................................................................... 87

10. Keyboard controller circuit discription.................................................................................................................................... 9q

11. Self check functions.................................................................................................................................................................. 94

12. IPL flow chart .........................................................................................................................................................................IO3

13. Circuit diagram & P.W.B Parts list & Guide

SHARP CORPORATION

1-1. Specification of the main unit (Model 35XX)

1) High speed processing using multi-CPU

2) Built in mini floppy disk

Outline

( )

3) Built in printer interface and RS232C serial interface

4) Connection of up to two video displa\ »nits ^separate graphic display or overlaid display possible on two individual color monitor units)

5) Permits the use of standard CP/M

Model 3530 incluse a single double-side, double density mini floppy disk and 64 KB RAM. Model MZ3540 has two double-side, density mini floppy disks and 64 KB RAM.

CPU

MEMORY

LSI

I/O FDC

DISPLAY

MZ353X

MZ354X

Light pen

Other l/F

Other

functions

Software

Accessories

Keyboard Dedicated keyboard Printer RS232C

Speaker (500mW) Battery backup clock

FDOS

CP/M

Intstruction Manual master floppy disk povver cord

1. SPECIFICATIONS

Model 3531 includes a single double side, double density mini floppy disk and 128 KB Model 3541 has two double side, double density mini floppy disks, and 128 K6

Multi-CPU processing Z80A microprocessor x 2

ROM

RAM

Custom LSI

GDC

PIO SIO TIMER CLOCK Screen structure Elements 8 X 16,8x8 Attribute Colors 8 colors on each character and background color l/F One double-side,

double density floppy disk

Two double-side, double density floppy disks

Centronics interface

No protocol, asynchronus mode. 110 to 9600 bps, half-duplex

BASIC

Utilities

Basic CP/M Expanded CP/M

IPL C, G 8K Byte ROM For main CPU 64K Bit ORAM X 16 chips or 8 chips For subCPU Shared RAM VIDEO

RAM Memory mapper

Screen controller CRT controller

Floppy disk controller Parallel I/O port

Serial I/O port 8251 Counter Clock 80 characters x 25 lines, 80 x 20, 40 x 25, or 40 x 20

Reverse, blink, line (horizontal, vertical)

2 channels (applicable CRT 640 x 400, 640 x 200, B/W or color)

256 bytes/sector, 16 sectors/track, 80 tracks/disk

Built-in interface for optional MFD

High class compatible with PC3200 BASIC, supplemented and graphic control commands

Expanded RS232C, GPIB, and GPIO BACKUP, INIT, COPY, DEBUG, KILLALL

8K Byte ROM

16K Bit SRAM X 4 chips 16K Bit SRAM X 1 chip 16KB'tSRAMx 1 chip

4K Bit SRAM X 2 chips

TH SP6102R001

SP6102C002

CSP-1 CSP 2

SP6102C003 *iPD7220 pPD765 8255

8253 pPD1990AC

HALT SW Speaker volume control

M 7 3500

I -

MZ3500

1-2. MZ-1K01 (Keyboard) specification

Outline

Specification

Keyboard layout

Ш P In

MZ1K02 U.S. keyboard (ASCII) MZ1K04 German keyboard

LSI, 1C

Keys (98)

Interfacing cables

Other

Cabinet

Keyboard controller CMOSIC Sculpture key

Alphanumeric keys

Mode switch For data transfer with the CPU (serial) and power supply (transmission under 15,000 baud) Use of coiled cable with 8-pin DIN plug

Repeat function

Indicators (4 LED's) Molded Color Office gray

Size (W X H X L)

MZ1K03: U.K. keyboard (ISO). MZ1K05: French keyboard

80C49 or 8749 4049 X 2,4514 Mechanical contact key, with life of 10,000,(Ю0 operations.

61 Ten key 15

Automatic repeat occurs 0.64 seconds after continuous depression of the same key.

POWER, Alphanumeric keys

467 X 35 X 190

Function keys

Weight About 1.5kg (3.3 lb)

6 Definable keys 10

2 Two-key rollover

II in

1-3. MZ-1U02

Outline

Specifications

Refer to the page TIN "CIRCUIT DIAGRAM”

Expansion unit for the MZ-3500 series CPU, which can be attached to the rear side of the main unit. Optional boards are plugged in to the expansion box. The expansion box will accomodate up to four option boards.

Number of slots: 4 slots Slot connector. 60-pin edge connector x 4 Area of the slot inserting option board: 140.5 x 140 Slot for option and slot number

Slot 4

MZ-1R06

(expansion RAM)

SFD l/F

Expansion RS232C

GPIO о GPIB

(IEEE l/F)

Slotl

О о

Slot 2

Slots

о о

о о о

о о

о о о о

- 2-

MZ3500

1-4. MZ-IR03

Outline

Specifications

Optional board used graphic display functions with the Model-3500 series CPU. It includes 32K6 of RAM. It is inserted through the slot on the front panel of the PU. The MZ-1U02 expansion box Is not required.

GDC Graphic controller MPD7220

LSI

' ——____VIDEO^^

Graphic functions (Color must be specified for each dot, when the color video unit is in use)

Software

BASIC graphic control statements

VIDEO RAM

Basic (buit-in) Expansion

(optional)

640 X 200

green monitor

640 X 200

color monitor

640 X 400

green monitor

640 X 400

color monitor

16KDRAM X 16 (32KB) 16KORAM X 32 (64KB)

32KB

(basic)

640 X 200 dots

Two screens

-------

640 X 400 dots

One screen

--------------------SDISP

ODISP CHANGE DISP Mode designation GCOLOR CLS PSET Dot set PRESET Dot reset LINE GTABLE CIRCLE Circle creation PAINT GINPUT Input of graphic pattern GDISP GPRINT Output of graphic pattern on printer GREAD GENTER Input of pattern within the specified area GCURSOR GSCROL SYMBOL Graphic symbol displaying SCALE Scren scle-down designation

Screen designation for two video units. Designation of output screen.

Graphic pattern designation Cleared by the color specified.

Line creation

Table creation

Paint over

Display of graphic pattern

Read of coordinates

Graphic cursor position designation

Graphic screen scrolling

(maximum expansion)

96KB

640 X 200 dots

Six screens

640 X 200 dots

Two screens

640 X 400 dots Three screens

640 X 400 dots

One screen

3 -

MZ3500

1-6. MZ-1R06

Outline

Specifications

Optional board for memory expantion of the MZ-3500 sries CPU. with this option the main memory (RAM) can be expanded up to a maximum of 256 KB. This option plug into the expantion box in slot 1 or 3.

LSI

Memory and user area

Basic Expansion

Totai capacity of

the main CPU RAM

64KDRAM X 8 (64KBI 64KDRAM X 8 (128KB)

SYSTEM

BASIC

(RAM

BASE)

AREA

USER

AREA

Main CPU only

128 KB 192 KB

• 57 KB

80 KB

Use of MZ-1R06

128 KB

Using eight 64K RAM's

on the MZ-1R06

256 KB

208 KB

- 4 -

1-7. MZ-1D07

MZ3500

Outline

Specifications

High resolution MZ 3500 senes 12 green monitor

Video tube

Display capacity

Display size

Input signals

Power supply

Cabinet

Adjusting knobs

Accessories

Type Fluorescent color P39 (green, long PERSISTANCE) Total number of

display characters 220X145 Method

Horizontal 20 86kHz 29W power consumption Molded

Size (W X H X L)

CPU connection cable and power cord and Tilt stand

Non glare green

2,000 characters

(80 characters x 25 lines)

Separate input, TTL level

Color

Vertical synchronization, contrast, brightness

Office gray

324x310x356

Size

Display capacity

Vertical

Weight

12”, 90 deflection

640 horizontal dots, 400 vertical lines

47 8 Hz

7.2 kg

(

- 5 -

MZ3500

1-8. System configuration of Model 3500

6 -

2. SOFTWARE (MEMORY) CONFIGURATION

MZ3500

Memory will be operated under four states of SDO ~ SD3, depending on the hardware and software configurations. In the paragraphs to follow, description will be made for

those four states.

MAIN CPU

2-1. SDO (INITIALIZE STATE)

SDO can only exist immediately after power on, and the

system executes IPL under this condition and that the system thus loaded will automatically assign memory area for SDÌ, SD2. and SD3.

SUB CPU

MSI = 0 (L) MSO = 0 (L)

2000

OFFF

0000

ROM

1 PL

ROM

(SPARE)

RAM

5F^FF

5800

57PF 5000

4FFF

4 000

0000

MZ 3500

Operational description

(1) Upon reset after power on, the main CPU loads the

contents of the initial program loader (IPL) into RAM starting at address 4000H, during which time reset is applied to the sub-CPU.

TIMING OF RESET SIGNAL

The main CPU then terminates resetting the sub CPU

(2)

and starts the sub-CPU. At the same time, the ROM

IPL is assigned to the sub-CPU.

The main CPU then send the memory allocation (state)

(3)

to SDÌ, and starts to load DOS from the system floppy disk.

Signal generated from the CR network and power supply

Output signal from the mam CPU port

MAIN CPU

START

Memory Map Data:

1. ROM-B is tested to determine if ROM's are present.

2. The ROM-IPL functions under control of the main CPU at first, but later it functions under the sub-CPU after

the IPL program has been loaded in RAM.

3. RAM-COM is shared by both the main CPU and the subCPU.

INITIALIZE FLOW „„t

a. Main CPU reset time

b. Main CPU IPL load time

4. Memories other than described above cannot be accessed under the SDO state.

5. Bank select, MA0~MA3, is used within the address range of COOOH-FFFFH.

''M* )S V 1 M/}

MZS.'tOO

ROM-IPL

1. An 8KB ROM (2764 or mask ROM equivalent) is used for the ROM-IPL.

2. When the system reset signal turns from low to high state after power on, the main CPU starts to operate At this stage, the ROM-IPL is addressed.

3. The CPU starts from address OOOOIROM address 10000)

4. The main CPU sets the sub-CPU reset signal from low to high state as it goes out of its initial state via the memory mapper and the sub-CPU starts to operate. At this point, the ROM-IPL is addressed by the sub-CPU.

5. Address 0000 of the sub-CPU is ROM address (0000) The memory area above ROM address (1000) cannot be used by the sub-CPU because the mam CPU initial program has been loaded there.

2-2. SDÌ (SYSTEM LOADING & CP/M)

SDÌ determines which operating system is in use. The system is loaded in the CP/M (Control Program for Micro processors) mode.

Mam CPU logical address (during IPL operation)

Logical address of the sub-CPU

ROM physical address

МЫ = 0( L) WS0=l(Hj

FFFF

P800 F7FF

i. Л 0 n

-----

' \

\ \

V \

\ \

RAM RAM RAM

\ \

RAM

\ \

5FFF

5800

57FF

5000

4FFF

4800

47FF

MZ3500

Operational description

(1 ) As soon as the sub-CPU is started, it initializes the I/O

port and waits for program transfer (IOCS) from the main CPU. This IOCS (Input Output Control System) is the program resident at address 4000H-5FFFH.

(2) As the main CPU loads the information from sector

Communication between Main and SUB CPU

"1" of track "0" of the floppy disk, it loads the IOCS

and bootstrap routine to the sub-CPU. (3) The bootstrap program is loaded next. (4) The bootstrap program determines memory allocation.

BUSRQ H OUTPUT

(ISOLATION OF COM RAM)

2.3. SD2 (ROM based BASIC)

SD2 is active when "SHARP BASIC" is executed via ROM.

RAM

BANK

SELECT

MA3 0 0 MA2 0 0 MAI 0 0 MAO 0 1

FFFF

KAMA

cooo

BFFF

4000

Ifff

2000

I FFF

4 1

KOMB

—I—1—1—

KAMb

1, 2 1 3|

0000

M02 0 MO] 0 MOO 0

MAIN CPU

---------1--------1--------\--------

ROM 2 ROMS

К AM L

1 1 2, 3, 4

--------

______

1--------1

KAM I*

i| г, 3| 4

MSI = u H ) Mso = 0 L;

--------1-------

SUB CPU

RAM SD

RAM

RAM(aX) ROM

J PL

1. Bank select. MA0~MA3, is effective for memory area COOOH-FFFFH.

2. Bank select. MOO—MA2, is effective for memory area 2000H-3FFFH

10 -

2-4. SD3 (RAM based BASIC)

SD3 is active when "SHARP BASIC" is ececuted via RAM. "SHARP BASIC" is loaded in RAM from the floppy disk.

MZ3500

MAIN CPU

МЛЗ 0

RAM

\ МЛ2 0

BANK

SELECT

I MAI 0 I MAO 0

I I г

RAM в

RAMA

lU 4L. 4U

2 I 3,

ROM!

cooo

BFFF

IFFF

0000

ROM («02 0 0 0 0 1

BANK (mo) 0 0 1 ' 1 0

SELECT /moo 0 10 I 0

1. Bank select, MA0-MA3, is effective for memory area COOOH-FFFFH.

2. Bank select, MO0-MO2, is effective for memory area 2000H-3FFFH.

0 0

1 1

0 0

0 i

----

RAMC

2j- -

1—

----1-----

KAMI)

MSI = 1 (H )

MSO = 1 ( H)

ЕЩх

SUB CPU

' \

RAM

_SA

ROMS

ROM BASE OF THE

SUB CPU

RAM EAM

\ ЦМ(СШ)

ROM I PI

Operational description The state of the system is determined by the bootstrap

program before the load of the system program.

3-1. Block diagram

1) Relation between MMR (Main Memory Mapper) and

main memory.

3. CPU AND MEMORY

3-2. Main CPU and I/O port

M A 1

C P

A5 A6 A7

A2 AS

lORQ

¥T

MZ3500

This paragraph discusses main CPU I/O

Connector port select and addressing.

I FC2 The address output from the main CPU

I is decoded in the 74LSI38 to create the I select signal.

I Table below describes address map and [ signal functions.

G2A

SKDC

O lOSF

L© 'MTR !

G2B

MFUC

ijD lOMF^

I I

74 LS138

lOABCMEMORY MAPPER)

- IT -

MZ3500

3-3. Sub CPU and I/O port

AS6

ASS

SUB

CPU

AS7

3—

¥T

___

AS4 1

“c

Shown at the left is the circuit used by

74LSI38

G2A

G2B

S07

S06

10 SOS

.11 S04

■ 12 S03

.15 S02

14 SOI

15 SOO

-►gdc-i

Graphic option

-►cSP-1 .CSP-2

-> Input port select (LS244)

-►8255-‘cT

-►8253-CS

-►8251-CS

MAINCPU-INT

the CPU to select the I/O ports The out put address from the sub CPU is decoded by the 74LS138to create the select signal.

Shown

below Is the address map and

select signals.

- 18 -

3-4. Memory mapper (MMR) SP6102R-001

1) Block diagram

MZ3500

19 -

MZ3500

2) Memory mapper (MMR) SP6102R-001 signal description

Pin No.

Polarity

Signal Name

A15

A13

A1 IN

SRES

SRQ

AR13

AR15

IN/OUT

OUT

Function

Main CPU DRAM output buffer (LS244) switching strap.

Bidirectional main CPU data bus.

(Data bus 0 7)

Main CPU address bus. Used in the memory mapping logic of the MMR for address output for the DRAM, ROM, and shared RAM. (Address bus 13 ~ 15)

Main CPU address bus. Used in the I/O port select logic of the MMR to assign device number

Sub-CPU bus request signal.

• After power on: Halts the sub-CPU.

• After write command (LDA-80H: OUT#FD) by the main CPU- Starts the sub-CPU. This signal is issued after transfer of the main CPU program contained m the ROM-IPL.

(Sub CPU Reset)

Sub-CPU bus request signal.

• After power on: Resets bus request to sub-CPU.

• After write command (LDA-02H: OUT#FC) by the main CPU: Place bus request to the sub-CPU This signal is issued to bus of the sub-CPU, after the main CPU writes to the shared RAM a command parameter to the sub-CPU or reads the message status from the sub-CPU.

(Sob CPU Request)

Address signal to the main CPU dynamic RAM. The main CPU addresssignals.A13-A 15, merged in the memory mapping logic circuit to produce AR13-AR15. This is means by which the 4 basic and CP/M memory maps are made, along with MSI and MSO.

19 R32 OUT

22 ROPB

lOAB

SRDY

ROAB

RODB

RSAB

RSDB

SACK

OUT

•R32B (alternate choice with the 32KB mask ROM chip select signal).

OUT

BASIC interpreter 32KB mask ROM chip select signal.

Valid when SD2 is active (Sharp ROM based BASIC). Command ILDA 02H OUT 3F D)

(ROM 32K select)

Internal MMR I/O port select logic signal.

Goes low by the command IN/OUT #FC-#FF.

(Input/Output Address)

Input of ready signal from the sub-CPU.

(Sub CPU Ready)

Chip select signal issued from the main CPU to the 8KB mask ROM. Valid with SDO active (initialize state).

(ROM ipl)

Chip select signal for four chip BASIC interpreter 8KB EPROM (A. B, C, D). Valid with SD2 active (Sharp ROM based BASIC).

(ROM A~D Buffer)

Row address select signal for the main CPU dynamic RAM (block A-block D). RAS (ROW ADDRESS SELECT; LINE ADDRESS SELECT) SIGNAL

(Row address Select)

Input of bus acknowledge signal from the sub-CPU. When the mam CPU must write a command in the shared RAM a bus request is issued first, then the command is written in the shared RAM after acknowledgement from the sub-CPU

I At the end of the command cycle bus request is released and the sub CPU executes the command

20-

M7-3S00

Polarity

Pin No.

Signai Name

35 RCMB

40 MRQB IN

RF1B

RF2B

WATB

ITFB IN

ITOB

IT1B

ÏT2B

IN/OUT Function

OUT

Mam CPU 128KB dynamic RAM output buffer (LS244) output enable signal.

(RAM buffer 1)

Signal identical to R F1 B For option RAM

(RAM buffer 2)

Wait signal to the mam CPU (One wait cycle is applied during the memory fetch cycle of the main CPU. It consists of one dock

period) (WAIT)

Chip select signat issued from the main CPU to select the RAM shared by the main CPU and the sub-CPU

(RAM Common)

Interrupt input from the UPD765 FDC (Floppy Disk Controller). |

(Interrupt from Floppy)

Interrupt input from the sub-CPU.

(Interrupt from No. 0)

Interrupt input from slot 1 or 2.

(Interrupt from No. 1, 2)

Memory request signal from the main CPU.

(Memory Request)

45 GND

46 Vcc

IT3B

ÏT«

SEC IN

SW1

SW2

RFSH

SW3

SW4

GND IN

Write signal from the mam CPU.

(Write)

Interrupt input from slot 3 or 4.

(Interrupt from No. 3, 4)

Input from the FDD (Floppy Disk Drive) assignment dip switch (A), No. 1. *See the dip switch description, provided separately.

(Section)

Ground

5V supply

Input from the svstem assignment dip switch. *See The dip swtch description, provided separately.

Mam CPU address bus Used in the I/O port select logic in the MMR to designate device number.

Refresh signal from the main CPU,

(Refresh)

Input from the system assignment dip switch. 'See the dip switch description, provided separately.

Ground

FD1

Vcc

FD2

IN 5V supply.

Input from the system assignment dip switch.

'See the dip switch description, provided separately.

Input from the FDD assignment dip switch (A), No. 2. 'See the dip swi*ch description, provided separately.

- 21 -

M/.3500

Pm No

Polarity

Signal Name

57 SYSR IN

FD3

COAB IN

60 R01B

63 64

GND IN

Vcc IN

R02B

R03B

RDB

CLK

IN/OUT

OUT

Function

System reset signal. Used to reset I/O port in the MMR.

(System Reset)

Input from the sytem assignment dip switch.

•$ee the dip switch description, provided separately.

Shared RAM select signal. Address of the shared RAM is i?F800-#FFFF for the main CPU

(Common RAM Address)

Select signal for 8KB area allocated to slot 1.

Valid when SD2 is active (ROM based BASIC) and SD3 (RAM based BASIC)

(ROM 1)

Ground

5V supply

Select signal for 8KB area allocated to slot 2 or 3. Valid when SD2 is active (ROM based BASIC) and SD3 (RAM based BASIC).

(ROM2, 3)

Read signal from the main CPU.

(Read)

EAIT signal generation clocit.

(Clock)

67 R04B OUT

MPX

GND IN

OUT

70 CASB OUT

71 GND

INTB

IN Ground

OUT

Select signal for 8KB area allocated to slot 4. Valid when SD2 or SD3 (RAM based BASIC) are active.

(ROM 4)

RAS/CAS address switching signal for the main CPU DRAM. High: Row address Low: Column address

(Multiplex)

Ground

CAS (Column Address) signal for the main CPU 64K DRAM.

•Refresh for the RAM only.

(Column Address Select Buffer)

Interrupt signal to the main CPU.

(Interrupt)

Not used

MAIN CPU

I/O PORT IN MEMORY MAPPER

ADDKKSS

-\7 A6 A5 A4 A3 A2 Al AO

111110 0

1111110 1

11111110

11111111

HEX

El)

DHUS

DO D7

1)7

D5 D4 D2 D1 DO D4 D3 D2 D1 DO D7 D6 D5

1)4 D3 D2

DO D7

1 ()

OUT

SKUH

I I

SKI s

MSI MSO

MA2 MAI MAO M02 MOl MOO

S\\4

S\)3

S'\2

Stt 1

SEC FD3 FD2 EDI

SKDY

SACK

1 NP2

INPl

1 NPO

MF2

ME 1

SRQ Bus request from the main CPU to the sub-CPU

Sub-CPU reset signal

Memory system define

Bank select signal to memory area of COOO-FFFF.

Bank select signal to memory area of 2000-3FFF.

System assign switch

FD assign

t. ^------------------------------------------

TÌ1 Sub-CPU READY signal

V Sub-CPU acknowledge signal

Interrupt status

M/3S00

(SW8)

1. All output signals are reset to low level upon power on, ' except for SRBQ that goes high.

2. Noted with a star mark "A" are input/output signals, and

rest of others are processed in the LSI.

#1 I/O port output of MEI and ME2 uses the memory at the addresses.

( ME2-^8000~ BFFF

1 MEI ^4000 ~7FFF When MEI and ME2 are in high state, RSAB (RASA) is inhibited during memory addresses in RAM-A that correspond to overlayed addresses for ME! and ME2 This is not true during SDÌ mode.

_____

- 23 -

‘ VK IN MEMCKT MM I Mf

, X 1

1 " i "

Wait timing generator WAIT IS issued once per main CPU fetch cycle. Its outui IS tri state

MFH noh

1 TsTTiT

1 H

f " ÌLtT“

M I TO ENCODMf

IMP 112h

IMI

IN=Tt INF?

1 M 1 X H

” -J

, " 1 '

II H

X X

X X X X

H M H H

FkoM SI Ml

I h <• 11

ii3h 1T4H JNT3

X X

<*nriT M(t»M FNCODFK

IM 2

INT4 Tvf

1 1 L

X X

X X L H L

1 1

L H

X X tl

H L H H

■ ^ ■

—

IMH

IM «

L 1

TO MAIN Cl I

MZ3500

3-5. Memory (ROMIPL, RAMCOM, S RAM) select circuit

1) ROM-IPL select by the main CPU As ROM IPL turns to low level after power on address bus buffers {LS244, LS367) and data bus buffer (LS245) are enabled. S of the data selector 1C (LS157) is set to a low level to enable input 1A-4A. The 3Y and 2Y outputs of the LSI 57 then go low so that CE and OE of the ROM-IPL are from main CPU. The contents of the IPL-ROM are then read by the main CPU. Because the input pin (ff16) of the address buffer (LS367) is

connected to Vcc, IPL for the main CPU will be at

address 1000 of the IPL-ROM. Switch SW2BA is the operation test dip switch which should be ON at all times.

2) RAM-COM select by the main CPU

When RAM COM is low, SRES high, and SACK low, the

select input S of the selector 1C (LSI 57) is in low state so that input 1A-4A becomes effective. That is, the out put 4Y is low and either 1Y (WE) or 2Y (OE) becomes low level, so as to enable to read or write RAM-COM.

3) ROM-IPL select by sub-CPU Normally, the select signal S of the selector is pulled up to Vcc level that inputs 1B-4B are enabled by sub CPU.

If A13 thru A15 were to be at low level, the output YO of the LSI39 becomes low level so that the output 3Y of the LS147 or CE of the ROM-IPL should be at low level. Should SRD, SMRO be at low lebel as well, the output 2Y of the LSI57 or OE of the ROM-IPL turnde to low lebel to read the ROM-IPL. Though the sub-CPU can access an address range of 0000 to 1FFF theoretical ly, it would be from 0000 to OFFF, actually.

4) RAM-COM select by sub-CPU Y1 of the LS139 changes to low level when AS13 is high

and AS14 and AS15 are low. In other words, the input 4B of the LSI 57 is at low level which brings the output

Y4 to low level, so that CS of the RAM-COM chip select

signal should become effective.

If SMRO, SRD or SMRO, SWR is in low level at this point, it enables read (OE) or write (WE). Address range, however, is 2000 to 3FFF

5) RAM (SA, SB, SC, SD) select by sub-CPU

SMRO, S^ (OE) or SMRO, SWR (WE) is at low level

to select the sub-CPU dedicated RAM, SA-SD. Tne

following chip select signal, then becomes valid under these conditions:

RAMSA .. AS11, AS12, AS13, AS14, AS15

(address 4000-47FF)

RAMSB .. AS11, AST2, ASi^, AS14, AS15

(address 4800-fFFF)

RAMSC .. AS11, AS12, AS13, AS14, AS15

(address 5000-57FF)

RAMSD .. ASH, AS12, AST3, ASK, AS15

(address 5800-5FFF)

- 24 -

4-1. Specification

y-/ rr-,^

4. CRT DISPLAY

Display memory

Character display

Graphic display (option)

Ust of fiigh resduiion CRT

3KB (characu>-$l 96KB, max (graphtc i

Screen structure

Programmable

Character structure

Attributes

Colors 8 colors, programmable for each character

80 chrs X 25 lines, 80 chrs x 20 lines 40 chrs X 25 lines, 40 chrs x 20 lines

8x16 dots

With lower case descenders

255 characters Alphanumerics and 69 symbols 26 small characters 97 graphic patterns

Revers, vertical line, bhnk, horizontal line Programmable for each character

Option

32KB type 640 X 400 dots, B/W (one frame)

Color designation for each character

96KB type

640 X 400 dots. B/W (three frames)

Color designation possible for each character Color (one f rante)

Use of medium resolution i,RT

8x8 dots

Blink, revers

Programmable for each character.

640 X 200 dots, B/W (Two frames) Color designation possible for each character

640 X 200 dots, B/W (six frames) Color designation possible for each character

Color (Two frame)

Screen merge

Merge of chracters and graphics

Merge any graphic screen (1 to 3 frames)

Merge a character screen with a graphic screen

Background color Choice of 8 colors

Control of two independent screens Possible to d bpiav on separate two screens origma' graphic scieen and character screen

Separate graphic screens can be merged into one Possible to affix attributes (CRT2 only) Selection of character/non-character screen display

Control channel number

Light pen input (option)

Incorporation of two independent video outut channels

Scans coordinates and character code

23 •

Summary of video display specification

Table 1

High resolution CRT (640 x 400 dots mode)

Type of monitor

Characters

Function

Elements

Character structure 5x14 5x14

Screen structure

(Characters x lines)

Basic

Color designation

Small letter descenders 0

Line creation

Display memory

Frames

overlay

Option 1 (48KB) Option II (96KB)

Basic Option 1 (48KB1 Option II (96KB) Basic

Option 1 (48KB)

Option II (96 K B}

ASCd

8 X 20

80 X 25 mode 80 X 25 80 X 20 mode 40 X 25 mode

40 X 20 mode

One character screen against

one gra'C'hic screen

One character screen Tgambi three graphic screens

Green monitor

Graphics (option) Characters Graphics (option) Characters

8x16

640 X 400 dot

3KB

1 frame

t 1 frame

Not possible

B/W

32KB 3KB 32KB (1), 96KB(ll)

No frame

3 frames

ASCII

8 X 16 8 X 20

80 X 20 40 X 25

40 X 20 40 X 20 40 X 20

By character By character

1 By character

O X

1 frame

f 1 frame t 1 frame

One character screen against one graphic screen

One B/W character screen agamst three graphic screens One color character screen against one graphic screen

Color monitor

Color

640 X 400

By dot

No frame

Medium resolution CRT (640 x 200 dots mode)

Green monitor

Graphics (option) Characters

ASCII

8x8 8x10

5x7 5x7

80 X 25 80 X 25 80 X 20 40 X 25

X X X X

3KB 16KB 3KB

1 frame (1 page)

*- -

One character screen against three graphic screens

’

B/W

640 X 200

No frame 1 frame (1 page) No frame 3 frames 6 frames

Color monitor

Graphics (option)

ASCII

8x8 8x10

80 X 20 40 X 25

t t

One 8/W character screen agamst three graphic screens One color character screen agamst one graphic screen

640 X 200

1 frame

2 frames

Color

By dot

48KB

NOTE Graphics opi'on

1) Character display

1.1. Screen structure

M7 3500

CRT used , (640 x 400 dot)

, High resolution CRT

Character |! INewlfV = 47 3Hz

80 X 25 lines

ASCIL

80 X 25 lines 40 X 25 lines 40 X 20 lines

|| fH = 20 9KHz

Medium resolution CRT

(640 X 200 dot)

fH = 15 7KHz

fV = 60Hz

Dip switch in the main unit is used to select assignment of high resolution/medium resolution CRT. Display mode must be chosen by programming.

1-2. Character structure and picture elements

640 X 200

Structure

8x8

8x10

Small tetter descenders and line creating functions are not available.

5x7

8x8

ASCII

Graphic symbol

640 X 400

Elements

8x16 8 X 20

Small letter descenders

and line creating

functions are available.

Structure Elements

5x14

8x16

NOTE: In the case of 8 x 8 and 8x16 picture elements,

vertically adjoining graphic symbols will joint together in the 25-line mode. As for character structure of 6 x 14, 7 x 14, 6x7, or 7 X 7, decision must be given on an actual dot pattern.

2) Graphic display (option)

(High resolution CRT) (Medium resolution CRT)

640 dot 640 dot

200 dot

Dot pitch

Horizontal vertical

1 1

400 dot

Dot pitch Horizontal vertical = 1 ; 2

W While

4) Attribute

B/W

ATI Vertical line

Horizontal line

AT2

AT3 AT4

Reverse

Blink

Color

Blink

Designated for each chaia-

cter.

Line and character r, .uV

exist in the same element

(Line may also be dis

played on the 80 charac ters X 25 lines screen.)

5) Screen overlay It will be possible to have an overlaid screen that consists

of one character (screen and a maximum of three graphic screens. (For detail of overlay screen, refer to Table 1.)

In the color mode, if there are two colors in the same

screen and other designated for a dot on the graphic screen element — the one designated for a character on the character — both colors will be merged altogether to produce image.

(Red)

@ Dot color designated by

character attribute

(Blue)

O Dot color designated by

graphic dot.

(Violet)

^ Dot composed of more than

two color lD .i-jmtior.:.

3) Color designation Eight colors are usable (white, yellow, cyan, green, violet, red, blue, black) Color designation

640 X 400 dot

ASCII By character

Graphics

48K byte By character By dot 96 K by te

By dot By dot

Background color 8 colors for designation

640 X 200 dot

By character

•¿1 -

MZ 3500

6) Screen overlay and displaying on two independent CRT’s

As there are two video output channels it will be pos sible to display two independent screens on separate video display unit Overlay is possible on either of

screens (See preceding item 5) ) The following bit selection is needed for screen overlay

CSP 1

Address Data

Hex

50 0

51 0 0

55 0

(5D)

AS AS DS DS PS S gnal name

2 1

0 0

0 1

0 2 0 0

0 1

1 1

0 1 COLOR Color mode

1 ECHI

1 BGC R 1 Choice of background color display

Internal

of CSP

Choice of outputting the character screen on CRT1 0 No 1 Yes ECH2 EAT2

SRI Displays on CRTI the blue elements contained m the VRAM SR2 SR3 SR4

SR5 SR6 Displays on CRT2 the green elements contained in the VRAM

BGC B

BGC G

BODER Border color mode in effect

08/16 Defines the data size for the graphic RAM (0 8 bits, 1 16 bits) 40/80 Defines display digits for the character screen

Cho ce of outputting the character screen on CRT2 0 No 1 Yes

Choice of whether attribute or cursor be put on the frame that displayed

on CRT2 (0 No 1 Yes)

Displays on CRTI the red elements contained in the VRAM

Displays on CRTI the green elements contained in the VRAM

Displays on CRT2 the blue elements contained in the VRAM

Displays on CRT2 the red elements contained in the VRAM

<0 40 digits 1 80 digits)

Function

56 0

57 0

5D 1 1 0 1

CSP 2

NOTE Both CRT1 and CRT2 must be high resolution CRT's (640 x 400) or medium resolution CRT’s fC40 y 'tftt))

Output to each CRT may be possible in the following

CRT I CH ( AT ) GF( AT) CH AI )+(> ! ^ AT )

1 1

0 1

1 V RAM1

RA-400 V RAM2

25/20

1 08/16

40/80

Connection of a 400 raster CRT

Connection of the 96K bytes VRAM Connection of graphio GDC 25 lines/20 lines switching (0 25 lines, 1 20 lines)

Defines data size for the graphic RAM (0 8 bits 1 16 bits)

Defines display digits for the character screen

(0 40 digits, 1 80 digits)

Output to each CRT may be possible in the following combination .

CRT 2 CH(AT) (.F AT) CH(Arj+C.i Al

CH ASCII GF Graphic screen, including overlay of two graphics

(AT) Attached with attribute

CH (.F CH+(,I

screens

7) ASCII CG

Uses an 8KB MROM contains two patterns' 640 X 400 dots (8x16 dots) and 640 x 200 dots (8x8 dots)

#0FFF

8x8 dot pattern

(2K bvte)

8x8 dot pattern

#0 000

(2K byte)

#1FFF

For Model 3200 senes

Without lower-case, letter descenders

MZ3500

With 8x8 dot format two kinds of patterns coexist

Refer to ROM address and data

code on separate information

8x16 dot pattern

(4K byte)

With lower-case,

letter (h i j) descenders

#1000

* Address and pattern in picture element

(Example of 5 x 12 dots pattern for 1 x 16 elements)

8) Element structure, character structure, and line

Element structure, character structure, and line

640 X 200 dot

1) 25 line display mode

Model 3500

(Address) (Data)

#1000

#00

#1001 10 #1002 10

#1003 28 #1004 #1005

#1006 #1007

44 44

7C #1008 7C #1009

44 #100A 44 #1006

44 #100C 44

#100D

#100E

.#100F

/ — Character pattern area \— Line area X— Area where pattern and line are overload

640 X 400 dot

Pattern

1 5 2

ASCD/JIS

Graphic symbol^

Without line

ASCQ/J IS

[Graphic symbol]

29 -

’ With line

HL On 16th line VL Line oi the right of

element

In the case of graphic

symbol display

* Both HL and VL are

overlaid to the pattern

MZ3500

9) Cursor Sharp of the cursor: Same as seen in Model 3200

Reverse and blink)

10) Light pen input incorporates the light pen input connector and its inter

face. The light p>en, however, is an option. Accuracy: By each character

Function: Coordinates/character code

11) Difference in specification with that of Model 3200 (1) There are two modes for the Model 3200; normal

mode (6x9 elements) and graphic mode (6x8 ele ments). In the normal mode of 25-line displaying of the PC-3200, vertically adjacent graphic symbols do not joint. But, they will joint with the Model 3500.

Model-3200 Model 3500

(2) No line will be displayed for the medium resolution

CRT (640x200 dot). It is possible to display line on the high resolution CRT, compatible to line the utilizing program of the Model 3200

4-2. Video RAM

1) Structure of VRAM

GDCl (for character)

GDC2 (for graphic)

#BFFF

16Kbit

(G)

17FFF

Attribute

#07FF

2Kbit > 8

2Kbit

( S-RA.M )

(ASCI L

(. s-

R.AM)

#0000

DO-

VRAM capacity Graphic option 1: 48KB Basic 3KB (including altibutes) Graphic option 2 96KB

Bit structure of VRAM

Character VRAM |

Graphic

V RAM

-D7 1)8—011

___CRT

48 KB 1 16 bit / word

96 KB 1 16 bit / word

#3FFF

#0000

Solid line 48KB option Broken line. To be added to comprise

640 X 400 dot

8 bit / word 8 bit / word

(D-RAM)

16Kb, t

( B)

------

D7 D8-

the 96KB option.

640 X 200 dcn

8 bit / word

16 bit / wo'd

-----------

________

I6Kbit

(R)

-D15

- 30 -

2) Read/write from Z 80 to VRAM

(1) Timing period for display and V-RAM Read/write.

M7 3500

^>-'7 Range wh°ra RDC can draw.

Fly back perfod

H • SYNC-

J~L

BLNK-

(2) Timing that the Z-80 can read/write VRAM

The Z-80 can read/write VRAM when GDC FIFO buffer is either empty or Full, and can be accessed by

3) Structure of character VRAM

(1) When read/write from GDC

#07FF

2KX8

ASC 1 I

#0000

8bi t

(A)

-D7 D8

2KX4

Attribute

4 b I t

----------

(B)

► Dll

refreshing during the display period. Number of characters that can be read/write within one raster in any mode.

(A)

-----------------------------------------------1--1

--------

----

----------------

ASC I K8bit) (

( I2bil ) )

no D1 D2 D3 D4 D5 D6 D7|d0

(B)

DI D2

- —

■ Blink

Reverse (G)

. Vertical line IR) . Horizontal line (B)

(2) During display

#07FF

#0000

2KX8

12bi t

(A)

(B)

2KX4

MZ3500

4) Graphic VRAM memory (MZIR03)

• Block Diagram

1. read/wnte Mode The select signal RASA, RASB and RASC are generate from

R AS, A14 and A15 which is signal of GDC-2.

The address »5 allocated to each area selected by above signal.

Read/write by Z-80 via the GDC

(1) 640 X 200 dots display mode

Low High

byte byte

Option I #BFFF

(48K byte)

8bit structure

+ 8000

I I

I t

#4000

I I

16K

#0000

8b it 8bit

Option II # BFFF

(96K byte) 16bit structure

together. By the DBiN signal from GDC-2, 08/16 signal is gener ated by CSP-2. The signal of 08/16 select, after P-5 conversion for RAMA, RAMB output signal then output to VB by serial signal, or sprit the signal to VB and VR. (08/16 select: 08 for 200 rasters, 16 for 400 rasters}

During displaying

B/W: 3 frames Color: 1 frame

#3FFF

16K

#0000

8bit

8bu

B/W: 6 frames Color: 2 frames

# 8000

# 4 0 0 0

+ 00 00

I6bit

I6K

16K

- 32 ■

MZ3500

(2) 640 X 400 dots display mode

Option i

{48K byte)

Option 11

(96K byte) 16 bits structure

#8000

#4 000

#0000

16bit

A #3FFF

16K

V #0000

16K

#3FFF

#0000

16bi t

B/W: 1 frame

Color: 1 frame

Video 1

_____

16bit

B/W: 3 frames

Color: 1 frame

K G

I6bit

1 tr

Color can be designated for each character

J6K

16bit

16K

5) Synchronize signal timing

(1) For 640 X 200 dots display mode

fH = 15.87kHz fV = 60 Hz

Dot clock (00)

2XCCLK

Horizontal display time

HFP

HBP

Vertical display time

VFP

VBP

Total rasters: 261 rasters Display raster: 200 rasters

GDC-1 (80 digits)

Character display (40 digits)

(16MHz)

( 8MHz)

(4MHz)

<2MHz>

40ms

7ms

6/JS

10ms (20 Chr.)

12,6ms

1.2ms

1 ms

1.8ms

—1

8 bits

16MHz

4MHz

^ (14 Chr.)

(1? Chr )

(tREF-0.8ms)

GDC-2

X : Y - 1 : 2

graphic)

16 bits

16MHz

2MHz

10ms

5jus

(tREF-1.6ms)

8iis

33 ■

_TL

2rn- h

+ 86 hidden pages

Sharp MZ-3500 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

CODE; OOZMZ 3500SM/E

SHARP CORPORATION

1-1. Specification of the main unit (Model 35XX)

1. SPECIFICATIONS

Keyboard layout

1-3. MZ-1U02

1-4. MZ-IR03

1-6. MZ-1R06

1-7. MZ-1D07

2. SOFTWARE (MEMORY) CONFIGURATION

MAIN CPU

2-1. SDO (INITIALIZE STATE)

2-2. SDÌ (SYSTEM LOADING & CP/M)

2.3. SD2 (ROM based BASIC)

2-4. SD3 (RAM based BASIC)

3-1. Block diagram

3-2. Main CPU and I/O port

3-3. Sub CPU and I/O port

3-5. Memory (ROMIPL, RAMCOM, S RAM) select circuit

4-1. Specification

4. CRT DISPLAY

4-2. Video RAM