Sharp LH540202U-50, LH540202D-25, LH540202D-15, LH540202U-25, LH540202U-20 Datasheet

LH540202

CMOS 1024 × 9 Asynchron ous FIFO

FEATURES

•• Fast Acces s Times : 15/20/ 25/ 35/50 ns

•• Fast- Fall-Through Time Ar chitect ure Based on

CMOS Dual-Port SRAM Tec hnology

•• Input Port and Output Port Have Entirely
Indepen dent Timing

•• Expandable in Width and Depth

•• Full, Half-Full, and Empty Status Flags

•• Data Retransmission Capability

•• TTL-Compa tible I/O

•• Pin and Functionally Comp atible with Sharp LH5497

and with Am/IDT/ MS7202

•• Indust rial Tempera tur e Gra de Option Curr ent ly
Available With Sharp LH5497H only
(Contact a Sharp Re presentative fo r Mo re Informatio n)

•• Control Signals Ass ertive- LO W for Noise Immunit y

•• Packages:

28-Pin, 300-mil PDIP
28-Pin, 300-mil SOJ *
32-Pin PLCC

PIN CONNECTIONS

FUNCTIONAL DESCRIP TIO N

The LH540202 is a FIFO (First-In, First-Out) memory
device, based on fully-static CMOS dual-port SRAM tech­nology, capable of storing up to 1024 nine-bit words. It
foll ows the industry-standard architecture and package
pinouts for nine-bit asynchronous FIFOs. Each nine-bit
LH540202 wor d m ay consist of a st andard eight -b it by te ,
toget her with a parity bit or a block-marking/ fram ing bit.

The input and output ports operate entirely inde­pendent ly of each other , unless the LH540202 becomes
either tota lly full or else totally empty. Data flow at a port
is initiated by asserting either of two asynchronous, as­sertive- LOW con trol input s: Wr ite (W) for data ent r y at t he
input por t, or Read ( R) for data retrieval at the output port .

Full, Half-Full, and Empty status flags monitor the
extent to which the interna l memory has been filled. The
system may make use of these status outputs to avoid
the risk of data loss, which otherwise might occur either
by attempt ing to write addition al words into an already-f ull
LH540202, or by att empting to r ead additional words from
an already-empty LH540202. When an LH540202 is
operating in a depth-cas caded configuration, the Half-Full
Flag is not available.

540202-2D

1

2
3
4
5
6

7
8
9

10

11
12
13
14

W

D

8

D

3

D

2

D

1

D

0

XI
FF
Q

0

Q

1

Q

2

Q

3

Q

8

V

SS

28
27
26
25
24
23
22

21
20
19
18
17
16
15

D

7

FL/RT
RS
EF

XO/HF

Q

5

Q

4

R

Q

6

Q

7

D

6

D

5

D

4

V

CC

28-PIN PDIP
28-PIN SOJ

*

TOP VIEW

Figure 1. Pin Connections for PDIP and

SOJ * Packages

5
6
7
8
9

10

D

2

XI

FF

11

2

3

4

32

31

30

29
28
27
26
25
24

NC

EF

D3D

8

W

NC

*

V

CC

D

4

D

5

14

15

16

20

19

18

17

FL/RT
RS

23

XO/HF
22
21

12NC
13

1

Q

3

Q

8

V

SS

NC

*

R

Q

4

Q

5

540202-3D

D

1

D

0

Q

0

Q

1

Q

2

D

6

D

7

Q

7

Q

6

32-PIN PLCC

TOP VIEW

NOTE: * = No external electrical connections are allowed.

Figur e 2. Pin Connections for PLCC Package

* This is a final dat a sheet; except t hat all references to the SOJ package have Advance Information status.

1

Data w ords are read out from the LH540202’s output
port in precisely the same order that the y were writt en in
at its input port; that is, according to a First-In, First Out
(FIFO) queue discipline. Since the addressing sequence
for a FIFO device’s memory is internally predefined, no
external addr essing inform ation is required for the opera­tion of the LH540202 device.

Drop-in-replacement compatibility is maintained with
both larger sizes and smaller sizes of industry-standard
nine-bit asynchronous FIFOs. The only change is in the
number of internally-stored data words implied by the
states of the Full Flag and the Half-Full Flag.

The Retrans mit (RT) cont r ol s ignal c auses the int ern a l
FIFO- memo ry- ar ray re ad- addr ess po in ter t o be set back
to zero, to point to the LH540202’s f irs t physical mem ory
location, without affecting the internal FIFO-memory­array write -ad dress po inter. Thus, the Retrans mit contro l
signal provides a mechanism whereby a block of data,
delimited by the zero physical address and the current
write-a ddr ess- po int er value, may be read out

repeated ly

an arbit rary number of times. The o nly restr iction s are that
neither the read-address pointer nor the write-address
pointer ma y ‘wrap ar ound’ dur ing t his entire process , i.e.,
advance past physical location zero after traversing the
entire memory. The retransmit facility is not available
when an LH540202 is operating in a depth-expanded
configuration.

The Reset (RS) control signal returns the LH540202 to
an initial s tate, empty and ready to be filled. An LH540202
should be reset during every system power-up sequence .
A r eset op era tion causes the int ern al FIFO -mem ory- array
write -address pointer, as well as the r ead-addres s pointer ,
to be set back to zero, to point to the LH540202’s first
physical memory location. Any information which pre­viously had been stored within the LH540202 is not
rec over able afte r a reset oper ation .

A cascading (depth-expansion) scheme may be imple­mented by using the Expansion In (XI) input signal and
the Expansion Out (XO/H F) output signal. This allows a
deeper ‘effective FIFO’ to be implemented by using two
or more LH540202 devices, without incurring additional
laten cy (‘fallthro ugh’ or ‘bubblethrough’) d elays, and with­out the necessity of storing and r et rieving any given dat a
word more than once. In this cascaded operating mode,
one LH540202 device must be designated as the ‘first­load’ or ‘master’ device, by grounding its First-Load
(FL/RT) control input; the remaining LH540202 devices
are designated as ‘slaves,’ by tying their FL/RT inputs
HIGH. Because of the need to share control signals on
pins, the Half-Full Flag and the retransm ission ca pability
are not available for eit her ‘master’ or ‘slave’ LH540202
devices operating in cascaded mode.

FUN CTIONAL DESCRIPTION (con t’d)

DATA OUTPUTS

Q0 - Q

8

FLAG

LOGIC

WRITE

POINTER

READ

POINTER

DATA INPUTS

D0 - D

8

1024 x 9

EF
FF

. . .

540202-1

DUAL-PORT

RAM

ARRAY

INPUT

PORT

CONTROL

R

W

RESET

LOGIC

RS

OUTPUT

PORT

CONTROL

EXPANSION

LOGIC

XO/HF

XI

FL/RT

Figure 3. LH540202 Block Diagr am

LH540202 CMOS 1024 × 9 Asynchronous FIFO

2

OPERATIONAL DESCRI PT ION

Reset

The LH540 202 is r eset whenever the Reset input (RS)
is taken LO W. A reset operat io n in itializes bot h the read­address pointer and the write- add res s point er to point to
location zero, the first physical memory location. During
a reset operation, the state of the XI and FL/RT inputs
determines whethe r the device is in standalone mode or
in depth-cascaded mode. (See Tables 1 and 2.) The
reset operation forces the Empty Flag EF to be asser t e d
(EF = LOW), and t he Half-Full Flag HF and the Full Flag
FF to be de assert ed (HF = FF = HIGH); the Data Out pins
(D0 – D8) are for ced int o a high-im peda nce st ate.

A reset oper at ion is r equired whenever the LH540 202
first is powered up. The Read (R) and Write (W) inputs
may be in any state when the re set oper ation is initiat ed;
but they must be HIGH, before the reset operation is
terminated by a rising edge of RS, by a time t

RRSS

(for

Read) or t

WRSS

(for Write) respectively. (See Figure 10.)

Write

A write cycle is initiated by a falling edge of the Write
(W) contr ol input . Data setup times and hold times must
be observed for the data inputs (D0 – D8). Write opera­tions may occur independently of any ongoing read op­eration s. However , a write operat ion is possible only if the
FIFO is not full, (i. e., if the Fu ll Flag FF is HIGH).

At the fa lling e dge of W for the first write o peration after
the memory is half filled, the Half-Full Flag is asserted
(HF = LOW). It remains asserted until the difference
between the write pointer and the read pointer indicates
that the data words remaining in the LH540202 are filling
the FIFO memory to less than or equal to one-half of its
total capacity. The Half-Full Flag is deasserted
(HF = HIGH) by the appropriate rising edge of R. (See
Table 3.)

The Full F lag is as serted (FF = LOW) at the falling edge
of W for the write operation which fills the last available
location in th e FIFO memory array. FF = LOW inhibits
further write oper ations until FF is cleared by a va lid r ead

operation. The Full Flag is deasser ted (FF = HIGH) after
the next rising edge of R releases anot he r mem ory lo ca­tion. (See Table 3.)

Read

A read cycle is initiated by a falling edge of the Read
(R) control input. Read data becomes valid at the data
output s (Q0 – Q8) after a time tA from the falling e dge of
R. After R goes HIGH, the data outputs return to a
high-impedance stat e. Read oper ations m ay occur in de­pendently of any ongoing write operations. However, a
read operation is possible only if the FIFO is not empty
(i.e., if the Empty Flag EF is HIGH).

The LH540202’s in ternal read -ad dress and wri te­addres s point er s oper ate in suc h a way that con secut ive
read operations always access data words in the same
order that they wer e written . The Empty Flag is asse rted
(EF = LOW) after that falling edge of R which accesses
the last available data word in the FIFO memory. EF is
deasserted (EF = HIGH) after the next rising edge of W
loads another valid data word. (See Table 3.)

Data Flow-Through

Read-data flow- throu gh mode occurs when the Read
(R) cont rol inpu t is brought LOW while the FIFO is empty ,
and is held LOW in antic ipation of a write cycle. At the end
of the next write cycle, the Empty F lag EF momentarily is
deasserted, and the data word just written becomes
available at the data outputs (Q0 – Q8) after a maxi­mum time of t

WEF

+ tA. Additional write operations may occur
while the R input remains LOW; but only data from the
first write operation flows through to the data outputs.
Additional data words, if any, may be accessed only by
toggling R.

Write-data flow-through mode occurs when the Write
(W) input is brought LOW while t he FIFO is full, and is
held LOW in anticipation of a read cycle. At the end of the
read cycle, the Full Flag momentarily is deasserted, but
then immediately is reasserted in response to W being
held LOW. A data word is written into the FIFO on the
rising edge of W, which may occur no sooner than
t

RFF

+ t

WPW

after the read oper ation.

PIN DESCRIPT IONS

PIN PIN TYPE

1

DESCRIPTION

D0 – D

8

I

Input Data Bus

Q0 – Q

8 O/Z

Out put Data Bu s

W

I

Write Request
R I Read Request
EF

O

Empt y Flag
FF

O

Full Flag

PIN PIN TYPE

1

DESCRIPTION

XO/HF

O

Expansion Out/Half-Full Flag

XI

I

Expansion In

FL/RT

I

First Load/Retransmit
RS I Res et
V

CC V

Positive Power Supply
V

SS

V

Ground

NOTES:

1. I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level

CMOS 1024 × 9 Asynchronous FIFO LH540202

3

OPERATIONAL DESCRIPTION (cont’d)

Retransmit

The FIFO can be made to reread previously-read data
by means of the Retransmit function. A retransmit opera­tion is initiated by pulsing the

RT input LOW. Both R and
W must be deasserted (HIGH) for the duration of the
retransmit pulse. The FIFO’s internal read-address
pointer is reset to point to location zero, the first physical
memory location, while the internal write-address pointer
remains unchanged.

After a retransmit operation, those data words in the
region in between the read-address pointer and the
write-address pointer may be reaccessed by subsequent
read operations. A retransmit operation may affect the
state of the status flags

FF, HF, and EF, depending on
the relocation of the read-address pointer. There is no
restriction on the number of times that a block of data
within an LH540202 may be read out, by repeating the
retransmit operation and the subsequent read operations.

The maximum length of a data block which may be
retransmitted is 1024 words. Note that if the write-address
pointer ever ‘wraps around’ (i.e., passes location zero
more than once) during a sequence of retransmit opera­tions, some data words will be lost.

The Retransmit function is not available when the
LH540202 is operating in depth-cascaded mode,
because the

FL/RT control pin must be used for first-load

selection rather than for retransmission control.

Table 1. Grouping-Mode Determination

During a Reset Operation

XI

FL/

RT

MODE

XO/HF

USAGEXIUSAGE

FL/RT

USAGE

H 1H

Cascaded
Slave

2

XO XI FL

H

1

L

Cascaded
Master

2

XO XI FL

L

X

Standalone

HF (none) RT

NOTES:

1. A rese t operation forces

XO HIGH for the nth FIFO, thus fo rcing XI

HIGH for the (n+1)st FIFO.

2. The terms ‘master’ a nd ‘slave’ refer to operation in depth-c as-

caded groupin g m o de.

3. H = HIGH; L = LOW; X = Don’t Care.

Table 2. Expansion-Pin Usage Acco rding t o

Grouping Mode

I/O PIN

STANDALONE

CASCADED

MASTER

CASCADED

SLAVE

I

XI Grounded

From

XO
(n-1st
FIFO)

From XO
(n-1st
FIFO)

O

XO/HF

Becomes
HF

To

XI
(n+1st
FIFO)

To XI
(n+1st
FIFO)

I

FL/RT

Becomes
RT

Grounded
(Logic
LOW)

Logic
HIGH

Table 3. Status Flags

NUMBER OF UNREAD DATA

WORDS PRESENT WITHIN

1024 × 9 FIFO

FF HF EF

0HHL

1 to 512 H H H

513 to 1023 H L H

1024 L L H

LH540202 CMOS 1024 × 9 Asynchronous FIFO

4

OPERATIONAL MO DES

Standalo n e Configuration

When depth cascading is not required for a given
application, the LH540202 is placed in st anda lone mode
by tying the Expansion In input (XI) to ground. This
input is interna lly sampled during a reset operatio n. (See
Table 1.)

Width Expansion

Word-width expansion is implemented by placing
multiple LH540202 devices in parallel. E ach LH540202
should be configured for standalone mode. In this ar­rangem ent, the behavior of the status flags is ident ical for
all devices; so, in principle, a representative value for
each of these flags could be der ived from any one device .
In practice, it is better to derive ‘composite’ flag values
using external logic, since there may be minor speed
variatio ns between differe nt actual devices. (See Figures
4, 5, a n d 6 .)

WRITE

DATA IN

D

0

- D

8

9

FULL FLAG

RESET

XI

RT

RETRANSMIT

EMPTY FLAG

9

READ

HF

LH540202

W

FF

RS

R

EF

DATA OUT

Q

0

- Q

8

540202-17

Figure 4. Standalone FI FO

(1024 × 9)

DATA IN

D

0

- D

17

18

WRITE

FULL FLAG

RESET

9

READ

EMPTY FLAG

R

EF

XI

RT

R

W

540202-18

RS

RETRANSMIT

RT

XI

HF

W
FF
RS

9

18

DATA OUT

Q

0

- Q

17

9

HF

9

LH540202

LH540202

Figur e 5. FIFO Word- W idth Expansi on

(1024 × 18 )

CMOS 1024 × 9 Asynchronous FIFO LH540202

5

OPERATIONAL MO DES (cont’d)

Depth Cascading

Depth cascading is implemented by configuring the
required nu mber of LH540202s in dept h-casca ded mode.
In this arrangem ent, the FIFOs are c onnected in a circular
fashion, with the Expansion Out output (XO) of each
device tied to the Expansion In input (XI) of the next
device. One FIFO in the c ascad e must be designat ed as
the ‘f irst - load’ device, by t ying its First Load input ( FL/RT)
to ground. Al l ot her devices m ust have the ir FL/R T inpu ts
tied HIGH. In this mo de, W and R signals are shared by
all devices, while logic within each LH540202 controls the
steering of data. Only one LH540202 is enabled during
any given write cycle; thus, the common Data In inputs of

all devices are tied together. Likewise, only one
LH540202 is enabled during any given read cycle; thus,
the common Da ta Out outputs of all devices are wire­ORed toget her

In depth-cascaded mode, external logic should be
used t o gene rate a composite F u ll Flag and a compos ite
Empty Flag, by ANDing the FF ou tputs of all LH540202
devices together and ANDing the EF outputs of all devices
together. Since FF and EF are assertive-LOW signals,
this ‘ANDing’ actually is implemented using an assert ive­HIGH physical OR gate. The Half-Full Flag and the
Retr ansm it funct ion are not available in depth- casc aded
mode.

RS

RS

FF

9

9

RS

W

FF

DATA IN

D

0

- D

8

RS

FF

9

9

9

R

9

DATA OUT

Q

0

- Q8

FL

FL

EF

XI

XO

FL

EF

Vcc

Vcc

XO

XO

9

9

XI

540202-19

XI

EMPTY

FULL

EF

LH540202

LH540202

LH540202

Figure 6. FIF O Depth Cas cading

(3072 × 9)

LH540202 CMOS 1024 × 9 Asynchronous FIFO

6