Sharp LH5324500N Datasheet
LH5324500
FEATURES
•• 3,145,7 28 w ords × 8 bi t organ izatio n
(Byte mode)
1,572,8 64 w ords × 16 bit orga niza tio n
(Word mode)
•• Access time: 150 ns (MAX.)
•• Power consu mption :
Operating : 357.5 mW (MAX.)
Standb y: 550 µW (MAX.)
•• Static operation
•• TTL compatible I/O
•• Three-state outputs
•• Singl e +5 V p owe r su ppl y
•• Packa ge: 44-pi n , 600 -mil SO P
DESCRIPTION
The LH5324500 is a 24M-bit mask-programmable
ROM organized a s 3 ,145,728 × 8 bits (Byte mode) or
1,572,864 × 16 bits (Word mode) that can be selected
by a BYTE input pin. It is fabricated using silicon-gate
CMOS process technology.
PIN CONNECTIONS
5324500-1
TOP VIEW
2
3
4
5
8
9A
2
A
5
39
38
37
36
35
34
31
28
A
7
A
6
6
7
A
3
A
4
33
32
A
10
A
11
A
13
A
15
BYTE
GND
D
14
10
11
12
4140A
9
A
1
13
30
D
15/A-1
(LSB)
29
D
7
OE
A
0
CE
A
12
44-PIN SOP
14
15
16
17
18
19
20
21
25
27
26
24
23
D
13
D
5
D
12
D
4
D
2
D
10
D
9
GND
D
8
D
1
D
0
D
3
D
11
V
CC
A
8
A
14
A
16
D
6
42
1
A
18
NC
22
44
43
A
17
A
19
A
20
Figure 1. Pin Connect ions for SOP Package
CMOS 24M (3M × 8/1. 5M × 16 ) M RO M
1
NOTE:
1. The D15/A–1 pin becom es LSB address input (A–1) when the B YTE pin is set to be LOW in byte mode, and data output (D15) when set to
be HIGH in word mode. When the address inputs become ’High’ to both A19 and A20, the data outputs become ‘ Unspecified’
since the data does n ot exist in this address area.
5324500-2
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
31
38
39
40
41
5
8
9
10
A
7
A
6
V
CC
A
4
MEMORY
MATRIX
(3,145,728 x 8)
(1,572,864 x 16)
SENSE AMPLIFIER
4
GND
7
42
A
5
6
A
13
37
ADDRESS BUFFER
A
0
11
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
A
14
36
A
15
35
12
TIMING
GENERATOR
A
16
34
A
-1
D
3
D
2
D
1
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
4
D
5
D
13
D
0
D
14
D
15
DATA SELECTOR/OUTPUT BUFFER
23 32
OE
BUFFER
ADDRESS
BUFFER
BYTE/WORD
SWITCHOVER
CIRCUIT
33
OE
CE
BYTE
22
20
18
16
26
19
17
15
21
30
24
25
27
29
31
14
A
17
3
A
19
43
28
A
18
2
13
A
20
44
Figure 2. LH5324500 Block Diagram
PIN DESCRIPTI ON
SIGNA L PIN NAME NOTE
A–1 – A
20
Addr ess in put 1
D
0
– D
15
Data ou tput 1
BYTE Byte /wo rd m ode sw itc h 1
CE Chip En abl e i npu t
SIGNAL PIN NAME NOTE
OE Outpu t E nab le inp ut
V
CC
Power su ppl y ( +5 V)
GND Groun d
NC No co nne cti on
LH5324500 CMOS 24M MROM
2
TRUTH TABLE
CE OE BYTE
A
–1
(D15)
DATA OUTPUT ADDRESS INPUT
SUPPLY
CURRENT
D0 – D
7
D8 – D
15
LSB MSB
H X X X High-Z High-Z – – Standby (ISB)
L H X X High-Z High-Z – – Operating (I
CC
)
LL H – D
0
– D7D8 – D
15
A
0
A
20
Operating (ICC)
LL L L D
0
– D
7
High-Z A
–1
A
20
Operating (ICC)
LL L H D
8
– D
15
High-Z A
–1
A
20
Operating (ICC)
NOTE:
X = H or L; High-Z = High-impedance
The D
15/A–1
pin becom es LSB address input (A–1) when the B YTE pin is set to be LOW in byte mode, and data output (D15) when set to
be HIGH in word mode. When the address i nput at both A
19
and A20 is HIGH level, the data outputs become high-impedance because
this data does not have data.
TRUTH TABLE WHEN BOTH A20 ADN A19 ARE HIGH
CE OE BYTE
A
–1
(D15)
A
20
A
19
DATA OUTPUT ADDRESS INPUT
SUPPLY
CURRENT
D
0
– D
7
D8 – D
15
LSB MSB
H X X X X X High-Z High-Z – – Standby (ISB)
L X H – H H High-Z High-Z A
0
A
20
Operating (ICC)
L X H – H H High-Z High-Z A
–1
A
20
Operating (ICC)
NOTE:
X = H or L; High-Z = High-impedance
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Suppl y v olt age V
CC
–0.3 to +7.0 V
Input vol tage V
IN
–0.3 to VCC + 0.3 V
Output vo lta ge V
OUT
–0.3 to VCC + 0.3 V
Operat ing te mpe ratu re
Topr 0 to +70 °C
Storag e t emp era ture Tstg –65 to +150
°C
RECOMMENDED OPERATING CON DITIONS (TA = 0°C to +70°C)
PARAMETER SYMBOL MIN. TY P. MAX. UNIT
Suppl y v olt age V
CC
4.5 5.0 5.5 V
DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C)
PAR AMETER SYMBOL CONDITIONS MIN. MAX. UNIT NO TE
Input ‘Hi gh’ voltage V
IH
2.2 VCC + 0.3 V
Input ‘Lo w’ voltage V
IL
–0.3 0.8 V
Output ‘H igh ’ vol tag e V
OH
IOH = –400 µA 2.4 V
Output ‘L ow’ v olt age V
OL
IOL = 2 .0 mA 0.4 V
Input leakage current | ILI |VIN = 0 V to V
CC
10 µA
Output le aka ge cur ren t
| ILO |
V
OUT
= 0 V to V
CC
10 µA1
Operat ing cu rre nt
I
CC1
tRC = 15 0 n s 65
mA 2
I
CC2
tRC = 1 µs
55
Standb y c urr ent
I
SB1
CE = V
IH
2mA
I
SB2
CE = VCC – 0.2 V 100
µA
Input cap acitan ce C
IN
f = 1 MHz
T
A
= 25° C
10 pF
Output ca pac ita nce C
OUT
10 pF
NOTES:
1. CE/OE = V
IH
2. VIN = VIH or VIL, CE = VIL, outputs open
CMOS 24M MROM LH5324500
3
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