Sharp LH532100BU-1, LH532100BSR-1, LH532100BS-1, LH532100BN-1, LH532100BD-1 Datasheet
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LH532100B-1
CMOS 2 M (256K × 8) MROM
FEATURES
•• 262,144 w ords × 8 b it organ izatio n
•• Access time: 120 ns (MAX.)
•• Static operation
•• TTL compatib le I/O
•• Three-state outputs
•• Singl e +5 V po we r su ppl y
•• Powe r consu mption :
Operating : 27 5 mW (MAX.)
Standby: 550 µW (MAX.)
•• Mask-programmable control pin:
Pin 1 = OE
1
/OE1/DC
Pin 24 = OE/
OE
•• Packages:
32-pi n , 600 - mil D IP
32-pi n , 525 - mil S OP
32-pi n , 450 -mi l Q FJ (PLC C)
32-pi n , 8 × 20 mm
2
TSOP (Typ e I)
32-pi n , 400-mi l TSOP (Type II )
DESCRIPTION
The LH532100B-1 is a CMOS 2M-bit mask-programmable ROM organized a s 262,144 × 8 bits. It is fabricated using silicon-gate process technology.
PIN CONNECTIONS
532100B1-1
TOP VIEW
1
2
3
4
5
6
9
10
A
2
A
5
V
CC
28
27
26
25
24
23
20
17
A
7
A
6
7
8
A
3
A
4
22
21
A
15
A
12
GND
A
13
A
8
A
11
A
10
CE
D
7
D
6
D
3
11
12
13
32
31
30
29
A
14
A
1
14
15
16
19
D
5
18
D
4
D
1
D
2
A
0
D
0
A
9
A
16
OE/OE
32-PIN DIP
32-PIN SOP
OE1/OE1/DC
DC
A
17
Figure 1. Pin Connections for DIP and
SOP Packages
21
22
23
24
25
26
27
D
7
CE
A
10
A
9
A
8
13
12
11
10
9
8
D
0
A
0
A
1
A
2
A
5
5
30 31 32 4321
28
29
A
13
A
14
6
A
7
7
DC
17181920 16 15 14
D6D5D4D3GND
D2D
1
32-PIN QFJ TOP VIEW
532100B1-7
OE/OE
A
11
A
3
V
CC
OE
1
/OE
1
/DC
A
16A15A12
A
17
A
4
A
6
Figure 2. Pin Connections fo r QFJ
(PLCC) Package
1
532100B1-2
TOP VIEW
2
3
4
5
8
9
V
CC
A
14
29
28
27
26
25
24
21
18
A
8
A
13
6
7
23
22
D
7
A
2
10
11
12
31
30
A
16
13
20
19
OE
1
/OE1/DC
32-PIN TSOP (Type I)
14
15
16
17
A
3
32
1
A
9
A
10
D
6
D
4
D
3
GND
D
2
D
5
D
0
A
0
A
1
A
11
A
15
A
12
A
7
A
6
A
5
A
17
DC
OE/OE
CE
A
4
D
1
Figure 3. Pin Connections fo r TSOP
(Type I) Package
1
2
3
4
7
8
A
7
30
29
28
27
26
25
22
19
A
15
A
12
5
6
A
6
24
23
A
16
DC
A
14
A
8
A
10
CE
D
5
9
10
11
32
31
12
21
D
7
20
D
6
A
0
D
0
A
2
A
1
A
13
13
14
A
9
532100B1-3
TOP VIEW32-PIN TSOP (Type II)
NOTE: Reverse bend available on request.
D
1
D215
16
GND
17
D
3
18
D
4
OE/OE
A
11
OE1/OE1/DC
A
5
A
4
A
3
A
17
V
CC
Figure 4. P in Connections for TSOP
(Type II) Package
LH532100B-1 CMOS 2M MROM
2
532100B1-4
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
32
4
25
23
26
6
9
10
11
A
7
A
6
V
CC
A
4
18
19
20
13
21
D
0
MEMORY
MATRIX
(262,144 x 8)
SENSE AMPLIFIER
OUTPUT BUFFER
16
5
GND
D
1D2D3D4D5D6D7
17
14
15
8
27
A
5
7
A
13
28
ADDRESS BUFFER
CE
A
0
12
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
A
14
29
A
15
3
22
TIMING
GENERATOR
A
16
2
1
OE1/OE1/DC
A
17
30
24
OE/OE
NOTE: Pin numbers apply to the 32-pin DIP, SOP, QFJ, or TSOP (Type II).
Figure 5. LH532100B-1 Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME NOTE
A0 – A
17
Addres s i npu t
D
0
– D
7
Data o utp ut
CE Chip e nab le inp ut
OE/
OE Output en abl e i npu t 1
SIGNAL PIN NAME NOTE
OE1/OE1/DC Output ena ble input 1, 2
V
CC
Power sup ply (+5 V)
GND Ground
NOTES:
1. Active levels of OE/OE and OE1/OE1/DC are mask-programmable. Selecting DC all ows the outputs to be active for both high and low levels
applied t o this p in. It is recommended to apply either a HIGH or a LOW to the D C p in.
2. DC = Don’t care.
CMOS 2M MROM LH532100B-1
3
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