Sharp LH532000BTR-1, LH532000BN-1, LH532000BD-1, LH532000BT-1 Datasheet
LH532000B-1
FEATURES
•• 262,144 words × 8 b it organ izatio n
(Byte mode)
131,072 w ords × 16 bit orga niza tio n
(Word mode)
•• Access time: 120 ns (MAX.)
•• Power consu mption :
Operating : 27 5 mW (MAX.)
Standb y: 550 µW (MAX.)
•• Mask-programmable c ontrol pin
(for 40-pin DIP/40-pi n SOP) :
Pin 1 = O E
1
/OE1/DC
Pin 12 = OE/
OE
•• Static operation
•• TTL compatible I/O
•• Three-state outputs
•• Singl e +5 V p owe r su ppl y
•• Packa ges:
40-pi n , 600 -mil DIP
40-pi n , 525 -mil S OP
48-pi n , 1 2 × 18 mm
2
TSOP (Type I)
DESCRIPTION
The LH532000B-1 is a C MOS 2M-bit mask-programmable ROM org anized as 262,144 × 8 bits (Byte mode)
or 131,072 × 16 bits (Word m ode) that can be selected
by BYTE input pin. It is fabricated using silicon -gate
CMOS process technology.
PIN CONNECTIONS
CMOS 2M (256K × 8/1 28K × 16) MROM
532000B1-1
TOP VIEW
1
2
3
4
7
8
A
2
A
5
38
37
36
35
34
33
30
27
A
7
A
6
5
6
A
3
A
4
32
31
OE
1
/OE1/DC
A
10
A
11
A
13
A
15
BYTE
GND
D
14
9
10
11
40
39
A
9
A
1
12
29
D15/A
-1
28
D
7
OE/OE
A
0
CE
A
12
40-PIN DIP
40-PIN SOP
13
14
15
16
17
18
19
20
24
21
26
25
23
22
D
13
D
5
D
12
D
4
D
2
D
10
D
9
GND
D
8
D
1
D
0
D
3
D
11
V
CC
A
8
A
14
A
16
D
6
Figure 1. Pin Connections for DIP and
SOP Packages
1
532000B1-2
TOP VIEW
2
3
4
5
8
9
A
10
A
13
45
44
43
42
41
40
37
34
A
15
A
14
6
7A
11
A
12
39
38
D
7
D
3
10
11
12
47
46
D
15/A-1
A
9
13
36
35
A
8
48-PIN TSOP (Type I)
14
15
16
17
18
19
20
21
31
28
33
32
30
29
D
2
D
9
D
1
D
8
OE/OE
D
10
GND
48
1
A
16
BYTE
22
27
D
0
GND
23
26
V
CC
24
25
GND
NC
OE
1
/OE1/DC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
GND
D
14
D
13
D
5
D
12
D
4
D
6
V
CC
GND
D
11
GND
NC
NC
NOTE: Reverse bend available on request.
Figure 2. Pin Connecti ons for TSOP Package
LH532000B-1 CMOS 2M MROM
2
NOTES:
1. D15/A–1 pin becomes LSB address input (A–1) when t he B YTE pin is set to be LOW in byte mode,
and data output (D
15
) when set to be HIGH i n word mode.
2. The active levels of OE/
OE and OE1/OE1/DC are mask-program mable.
532000B1-3
21
A
-1
22
24
261328
D
0
MEMORY
MATRIX
(262,144 x 8 )
(131,072 x 16 )
SENSE AMPLIFIER
30
GND
D
1D2D3D4D5D6D7
12
19
15
17
OE/OE
ADDRESS BUFFER
CE
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
OE
BUFFER
10
TIMING
GENERATOR
DATA SELECTOR/OUTPUT BUFFER
BYTE/WORD
SWITCHOVER
CIRCUIT
ADDRESS
BUFFER
31
BYTE
A
6
A
5
A
4
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
7
A
8
A
16
A
3
A
2
A
1
A
0
36
39
3
4
38
2
37
40
5
6
7
8
9
33
34
35
32
1
11
GND
29
V
CC
2325271429
D
8D9D10D11D12D13D14D15
2016
18
OE1/OE1/DC
NOTE: Pin numbers apply to 40-pin DIP or SOP.
Figure 3. LH532000B-1 Block Diagram
PIN DESCRIPTI ON
SIGNA L PIN N AME NOT E
A–1 – A
16
Addre ss inp ut 1
D
0
– D
15
Data out put 1
BYTE Byte /wo rd m ode sw itc h 1
CE Chip ena ble in put
SIGNAL PIN NAME NO TE
OE/OE Outpu t en abl e i npu t 2
OE
1
/OE1/DC Outpu t en abl e i npu t 2
V
CC
Power su ppl y (+ 5 V)
GND Ground
CMOS 2M MROM LH532000B-1
3
Loading...