Sharp LC-46X8E/S/RU Service Manual

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LC-46X8E/S/RU
SERVICE MANUAL
No. S38G2LC46X8E/
LCD COLOUR TELEVISION
MODELS
In the interests of user-safety (Required by safety regulations in some countries) the set should be restored to its orig­inal condition and only parts identical to those specified should be used.
LC-46X8E/S/RU
OUTLINE
This Service Manual covers the differences from LC-46X8E/S/RU. For other technical information, refer to the LC-42X20E/S/RU (No. S87O8LC46X20E) for Service Manual.
CONTENTS
SAFETY PRECAUTION
PRECAUTION.....................................................i
Precautions for using lead-free solder ...............ii
CHAPTER 1. OPERATION MANUAL
[1] SPECIFICATIONS ......................................... 1-1
[2] OPERATION MANUAL .................................. 1-2
[3] DIMENSIONS ................................................ 1-7
CHAPTER 2. REMOVING OF MAJOR PARTS
[1] REMOVING OF MAJOR PARTS ................... 2-1
CHAPTER 3. ADJUSTMENT PROCEDURE
[1] ADJUSTMENT PROCEDURE ....................... 3-1
CHAPTER 4. TROUBLESHOOTING TABLE
[1] TROUBLESHOOTING TABLE ....................... 4-1
CHAPTER 5. MAJOR IC INFORMATIONS
[1] MAJOR IC INFORMATIONS.......................... 5-1
CHAPTER 6. BLOCK DIAGRAM/WIRING DIAGRAM
[1] SYSTEM BLOCK DIAGRAM .........................6-1
[2] TERMINAL BLOCK DIAGRAM .....................6-2
[3] MAIN BLOCK DIAGRAM...............................6-3
[4] WIRING DIAGRAM .......................................6-4
CHAPTER 7. PRINTED WIRING BOARD
[1] MAIN UNIT PRINTED WIRING BOARD........7-1
[2] TERMINAL UNIT PRINTED WIRING
BOARD.......................................................... 7-5
[3] R/C, LED UNIT/KEY UNIT PRINTED
WIRING BOARD ...........................................7-8
[4] MINI AV UNIT PRINTED WIRING
BOARD.......................................................... 7-9
CHAPTER 8. SCHEMATIC DIAGRAM
[1] DESCRIPTION OF SCHEMATIC
DIAGRAM...................................................... 8-1
[2] SCHEMATIC DIAGRAM ................................8-2
Parts Guide
Parts marked with " " are important for maintaining the safety of the set. Be sure to replace these parts with specified ones for maintaining the safety and performance of the set.
This document has been published to be used for after sales service only. The contents are subject to change without notice.
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LC46X8E
Service Manual
SAFETY PRECAUTION
IMPORTANT SERVICE SAFETY PRECAUTION
WARNING
1. For continued safety, no modification of any circuit should be attempted.
2. Disconnect AC power before servicing.
BEFORE RETURNING THE RECEIVER (Fire & Shock Hazard)
Before returning the receiver to the user, perform the following safety checks:
3. Inspect all lead dress to make certain that leads are not pinched, and check that hardware is not lodged between the chassis and other metal parts in the receiver.
4. Inspect all protective devices such as non-metallic control knobs, insulation materials, cabinet backs, adjustment and compartment covers or shields, isolation resistor-capacitor networks, mechanical insulators, etc.
5. To be sure that no shock hazard exists, check for leakage current in the following manner.
• Plug the AC cord directly into a 220~240 volt AC outlet.
• Using two clip leads, connect a 1.5k ohm, 10 watt resistor paral­leled by a 0.15µF capacitor in series with all exposed metal cabinet parts and a known earth ground, such as electrical conduit or elec­trical ground connected to an earth ground.
• Use an AC voltmeter having with 5000 ohm per volt, or higher, sen­sitivity or measure the AC voltage drop across the resistor.
• Connect the resistor connection to all exposed metal parts having a return to the chassis (antenna, metal cabinet, screw heads, knobs and control shafts, escutcheon, etc.) and measure the AC voltage drop across the resistor. All checks must be repeated with the AC cord plug connection reversed. (If necessary, a nonpolarized adaptor plug must be used only for the purpose of completing these checks.) Any reading of 1.05 V peak (this corresponds to 0.7 mA peak AC.) or more is excessive and indicates a potential shock hazard which must be corrected before returning the monitor to the owner.
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
SAFETY NOTICE
Many electrical and mechanical parts in LCD color television have special safety-related characteristics.
These characteristics are often not evident from visual inspection, nor can protection afforded by them be necessarily increased by using replacement components rated for higher voltage, wattage, etc.
Replacement parts which have these special safety characteristics are identified in this manual; electrical components having such features
are identified by “ ” and shaded areas in the Replacement Parts List and Schematic Diagrams.
For continued protection, replacement parts must be identical to those used in the original circuit.
The use of a substitute replacement parts which do not have the same safety characteristics as the factory recommended replacement parts shown in this service manual, may create shock, fire or other hazards.
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
Service work should be performed only by qualified service technicians who are thoroughly familiar with all safety checks and the
servicing guidelines which follow:
CAUTION:
FOR CONTINUED PROTECTION AGAINST A RISK OF FIRE REPLACE ONLY WITH SAME TYPE FUSE.
F7000 (6.3A/250V)
DVM
AC SCALE
1.5k ohm 10W
TO EXPOSED METAL PARTS
CONNECT TO KNOWN EARTH GROUND
0.15µF
TEST PROBE
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LC-46X8E/S/RU
ii
Precautions for using lead-free solder
Employing lead-free solder
• “PWBs” of this model employs lead-free solder. The LF symbol indicates lead-free solder, and is attached on the PWBs and service manuals. The alphabetical character following LF shows the type of lead-free solder.
Example:
Using lead-free wire solder
• When fixing the PWB soldered with the lead-free solder, apply lead-free wire solder. Repairing with conventional lead wire solder may cause dam­age or accident due to cracks.
As the melting point of lead-free solder (Sn-Ag-Cu) is higher than the lead wire solder by 40 °C, we recommend you to use a dedicated soldering bit, if you are not familiar with how to obtain lead-free wire solder or soldering bit, contact our service station or service branch in your area.
Soldering
• As the melting point of lead-free solder (Sn-Ag-Cu) is about 220 °C which is higher than the conventional lead solder by 40 °C, and as it has poor solder wettability, you may be apt to keep the soldering bit in contact with the PWB for extended period of time. However, Since the land may be peeled off or the maximum heat-resistance temperature of parts may be exceeded, remove the bit from the PWB as soon as you confirm the steady soldering condition.
Lead-free solder contains more tin, and the end of the soldering bit may be easily corroded. Make sure to turn on and off the power of the bit as required.
If a different type of solder stays on the tip of the soldering bit, it is alloyed with lead-free solder. Clean the bit after every use of it.
When the tip of the soldering bit is blackened during use, file it with steel wool or fine sandpaper.
• Be careful when replacing parts with polarity indication on the PWB silk.
Lead-free wire solder for servicing
Part No. Description Code
ZHNDAi123250E J φ0.3mm 250g (1roll) BL ZHNDAi126500E J φ0.6mm 500g (1roll) BK ZHNDAi12801KE J φ1.0mm 1kg (1roll) BM
L Fa
Indicates lead-free solder of tin, silver and copper.
L F a/a
Indicates lead-free solder of tin, silver and copper.
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LC46X8E
Service Manual
CHAPTER 1. OPERATION MANUAL
[1] SPECIFICATIONS
When using Wall-mount bracket AN-52AG4
Wall bracket B has an attachment pitch of 400 mm. Assemble wall brackets using mark “C” on wall bracket A and mark “A” on wall bracket B. Mark “b” on wall bracket B shows the center position for the LCD TV. Install the Wall-mount Brackets using screw holes 2 . Refer to the Wall-mount bracket operation manual for details.
The listed optional accessories are available for the LCD colour TVs. Please purchase them at your nearest shop.
Additional optional accessories may be available in the near future. When purchasing, please read the newest catalogue for compatibility and check the availability.
No. Part name Part number
1 Wall mount bracket AN-52AG4
Specifications
Item
46" LCD COLOUR TV, Model: LC-46X8E, LC-46X8S
LCD panel
46" Advanced Super View & BLACK TFT LCD
Resolution
2,073,600 pixels (1920 1080)
Video Colour System PAL/SECAM/NTSC 3.58/NTSC 4.43/PAL 60
TV Function TV-Standard Analogue CCIR (B/G, I, D/K, L/L’)
Digital DVB-T (2K/8K OFDM)
Receiving Channel
VHF/UHF E2-E69ch, F2-F10ch, I21-I69ch, IR A-IR Jch (Digital: E5-E69ch)
CATV Hyper-band, S1-S41ch
TV-Tuning System Auto Preset 999 ch (ATV: 99 ch), Auto Label, Auto Sort
STEREO/BILINGUAL NICAM/A2
Brightness 450 cd/m
2
(at “DYNAMIC” mode)
Viewing angles H : 176° V : 176°
Audio amplifier
15W 2
Speaker
(100 mm 40 mm) 4
Terminals Antenna
UHF/VHF 75 Din type (Analogue & Digital)
RS-232C D-Sub 9 pin male connector
EXT1 SCART (AV input, Y/C input, RGB input, TV output)
EXT2 SCART (AV input/monitor output, Y/C input, AV Link, RGB input)
EXT3 S-VIDEO (Y/C input), RCA pin (AV input)
EXT4 HDMI
EXT5 HDMI
EXT6 HDMI, Ø 3.5 mm jack
EXT7 15 pin mini D-sub, Ø 3.5 mm jack
EXT8 COMPONENT IN: Y/P
B(CB)/PR(CR), RCA pin (L/R)
DIGITAL AUDIO OUTPUT Optical SPDIF Digital audio output
C. I. (Common Interface) EN50221, R206001
OUTPUT RCA pin (Audio)
Headphones Ø 3.5 mm jack (Audio output)
OSD language Czech, Danish, Dutch, English, Estonian, Finnish, French, German, Greek, Hungarian, Italian,
Latvian, Lithuanian, Norwegian, Polish, Portuguese, Russian, Slovak, Slovene, Spanish, Swedish, Turkish
Power Requirement AC 220 - 240 V,50 Hz
Power Consumption 245 W (0.5 W Standby) (Method IEC60107)
Weight 22.5 kg (Without stand), 26.5 kg (With stand)
Operating temperature
0°C to 40°C
As a part of policy of continuous improvement, SHARP reserves the right to make design and specification changes for product improvement without prior notice. The performance specification figures indicated are nominal values of production units. There may be some deviations from these values in individual units.
NOTE
Refer to the inside back cover for dimensional drawings.
Optional accessory
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[2] OPERATION MANUAL
15
16 17
18 19
20 21
22
23
24
25
4
3
2
5 6
7 8
9
10
11
12
13
14
1
(Standby/On)
Buttons for useful operations
(Teletext)
ATV: Display analogue teletext. DTV: Select MHEG-5 and teletext for DTV.
(Reveal hidden Teletext)
(Subtitle)
Switch subtitle languages on/off.
(Freeze/Hold)
Press to freeze a moving image on the screen. TELETEXT: Stop updating Teletext pages automatically or release the hold mode.
(Subpage)
(Top/Bottom/Full)
Set the area of magnification in teletext mode.
0 - 9 numeric buttons
Set the channel. Enter desired numbers. Set the page in teletext mode.
The channel display for the LC­46X8S model has 4-digits and the LC-46X8E model has 3-digits.
(Flashback)
Press to return to the previous image in normal viewing mode.
DTV
Press to access DTV mode.
ATV
Press to access conventional analogue TV mode.
(Sound mode)
Select the sound multiplex mode.
( / ) (Volume)
Increase/decrease TV volume.
(Mute)
TV sound on/off.
(WIDE MODE)
Select the wide mode.
AV MODE
Select a video setting.
/ / / (Cursor)
Select a desired item on the setting screen.
OK
Execute a command within the “MENU” screen. ATV/DTV: Display the programme list when no other “MENU” screen is running.
END
Exit the “MENU” screen.
1
2
3
4
5
6
7
8
9
10
11
12
13
R/G/Y/B (Colour) buttons
The coloured buttons are correspondingly used to select the coloured items on the screen. (e.g. EPG, MHEG-5, TELETEXT)
(INPUT SOURCE)
Select an input source.
EPG
DTV: Display the EPG screen.
RADIO
DTV: Switch between Radio and Data mode.
When only data broadcasting (no radio broadcasting) is transmitted by DVB, the radio broadcasting will be skipped.
P. INFO
Press to display programme information which is transmitted through digital video broadcasting in the upper left corner of the screen. (DTV only)
P( / )
Select the TV channel.
(Display information)
Press to display the station information (channel number, signal, etc.) in the upper right corner of the screen.
SLEEP
Press to schedule a time for the TV to automatically standby.
MENU
“MENU” screen on/off.
(Return)
Return to the previous “MENU” screen.
ACTION (Action Mode)
This key does not work on this model.
AQUOS LINK buttons
If external equipment such as a AQUOS BD Player is connected via HDMI cables and is AQUOS LINK compatible, you can use these AQUOS LINK buttons.
14
15
16
17
18
19
20
21
22
23
24
25
Remote control unit
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2
3
4
12
13
16
6 7891011
1
15
14
5
AC INPUT terminal EXT3 terminals EXT4 (HDMI) terminal Headphones SERVICE socket
1 2 3 4 5
TV (Front view)
TV (Rear view)
EXT1 (RGB) terminal EXT2 (RGB) terminal EXT8 (COMPONENT/AUDIO) terminals Antenna terminal OUTPUT (AUDIO) terminals DIGITAL AUDIO OUTPUT terminal
6 7 8
9 10 11
COMMON INTERFACE slot RS-232C terminal EXT5 (HDMI) terminal EXT6 (HDMI/AUDIO) terminals EXT7 (ANALOGUE RGB/AUDIO) terminals
12 13 14 15 16
Remote control sensor
OPC sensor
OPC indicator
SLEEP indicator
(Standby/On) indicator
MENU button
(Power) button
( / ) Volume buttons
P (/ ) Programme (channel) buttons
(INPUT SOURCE)
button
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Confirm that there are 8 screws (4 short screws and 4 long screws) with the stand unit.
Attach the supporting post for the stand unit onto the base using the 4 long screws with the hex key (supplied) as shown.
1
2
Preparation
Inserting the stand.
Insert the stand into the openings on the bottom of the TV. (Hold the stand so it will not drop from the edge of the base area.)
Insert and tighten the 4 short screws into the 4 holes on the rear of the TV.
3
1
2
NOTE
To detach the stand unit, perform the steps in reverse order.
Attaching the stand unit
Before attaching (or detaching) the stand, unplug the AC cord from the AC INPUT terminal. Before performing work spread cushioning over the base area to lay the TV on. This will prevent it from being damaged.
CAUTION
Attach the stand in the correct direction. Be sure to follow the instructions. Incorrect installation of the stand may result in the TV falling over.
Hex key
Hex key
Long screw
Short screw
Soft cushion
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Preparation
Inserting the batteries
Before using the TV for the first time, insert two “AAA” size batteries (supplied). When the batteries become depleted and the remote control unit fails to operate, replace the batteries with new “AAA” size batteries.
Open the battery cover. Insert two supplied “AAA” size batteries.
Place batteries with their terminals corresponding to the (
) and ( ) indications in the battery compartment.
Close the battery cover.
CAUTION
Improper use of batteries can result in chemical leakage or explosion. Be sure to follow the instructions below.
Do not mix batteries of different types. Different types of batteries have different characteristics. Do not mix old and new batteries. Mixing old and new batteries can shorten the life of new batteries or cause chemical leakage in old batteries. Remove batteries as soon as they have worn out. Chemicals that leak from batteries can cause a rash. If you find any chemical leakage, wipe thoroughly with a cloth. The batteries supplied with this product may have a shorter life expectancy due to storage conditions. If you will not be using the remote control unit for an extended period of time, remove the batteries from it.
Note on disposing batteries:
The batteries provided contain no harmful materials such as cadmium, lead or mercury. Regulations concerning used batteries stipulate that batteries may no longer be thrown out with the household rubbish. Deposit any used batteries free of charge into the designated collection containers set up at commercial businesses.
Using the remote control unit
Use the remote control unit by pointing it towards the remote control sensor. Objects between the remote control unit and sensor may prevent proper operation.
1 2
3
Cautions regarding the remote control unit
Do not expose the remote control unit to shock. In addition, do not expose the remote control unit to liquids, and do not place in an area with high humidity. Do not install or place the remote control unit under direct sunlight. The heat may cause deformation of the unit. The remote control unit may not work properly if the remote control sensor of the TV is under direct sunlight or strong lighting. In such case, change the angle of the lighting or TV, or operate the remote control unit closer to the remote control sensor.
30° 30°
5m
Remote control sensor
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Appendix
Troubleshooting
Problem Possible Solution
No power.
Check if you pressed on the remote control unit. If the indicator on the TV lights up red, press . Is the AC cord disconnected? Check if you pressed on the TV.
Unit cannot be operated. External influences such as lightning, static electricity, etc., may cause improper operation. In
this case, operate the unit after first turning the power off, or unplugging the AC cord and re­plugging it in after 1 or 2 minutes.
Remote control unit does not operate.
Are batteries inserted with polarity ( , ) aligned? Are batteries worn out? (Replace with new batteries.) Are you using it under strong or fluorescent lighting? Is a fluorescent light illuminated onto the remote control sensor?
Picture is cut off. Is the image position correct?
Are screen mode adjustments (WIDE MODE) such as picture size made correctly?
Strange colour, light colour, or dark, or colour misalignment.
Adjust the picture tone. Is the room too bright? The picture may look dark in a room that is too bright. Check the “Colour System” setting.
Power is suddenly turned off. The unit’s internal temperature has increased.
Remove any objects blocking the vent or clean. Is the “Sleep Timer” set? Select “Off” from the “Sleep Timer” menu. Is “No Signal Off” or “Ecology” activated?
No picture. Are connections to external equipment correct?
Is the input signal type selected correctly after connection? Is the correct input source selected? Is a non-compatible signal being input? Is the picture adjustment correct? Is the antenna connected properly? Is “On” selected in “Audio Only”?
No sound. Is the volume too low?
Make sure that headphones are not connected. Check if you pressed on the remote control unit.
The TV sometimes makes a cracking sound.
This is not a malfunction. This happens when the cabinet slightly expands and contracts according to change in temperature. This does not affect the TV’s performance.
Cautions regarding use in high and low temperature environments
When the unit is used in a low temperature space (e.g. room, office), the picture may leave trails or appear slightly delayed. This is not a malfunction, and the unit will recover when the temperature returns to normal. Do not leave the unit in a hot or cold location. Also, do not leave the unit in a location exposed to direct sunlight or near a heater, as this may cause the cabinet to deform and the LCD panel to malfunction. Storage temperature: +5°C to +35°C.
Information on the software license for this product
Software composition
The software included in this product is comprised of various software components whose individual copyrights are held by SHARP or by third parties.
Software developed by SHARP and open source software
The copyrights for the software components and various relevant documents included with this product that were developed or written by SHARP are owned by SHARP and are protected by the Copyright Act, international treaties, and other relevant laws. This product also makes use of freely distributed software and software components whose copyrights are held by third parties. These include software components covered by a GNU General Public License (hereafter GPL), a GNU Lesser General Public License (hereafter LGPL) or other license agreement.
Obtaining source code
Some of the open source software licensors require the distributor to provide the source code with the executable software components. GPL and LGPL include similar requirements. For information on obtaining the source code for the open source software and for obtaining the GPL, LGPL, and other license agreement information, visit the following website:
http://www.sharp-eu.com/gpl/
We are unable to answer any questions about the source code for the open source software. The source code for the software components whose copyrights are held by SHARP is not distributed.
Acknowledgements
The following open source software components are included in this product:
• linux kernel • modutils • glibc • zlib • libpng
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[3] DIMENSIONS
480.0 480,0
400.0 400,0
400.0
400,0
1023.4 1023,4
1101.0 1101,0
575.6
575,6
62.0
62,0
433.9
433,9
285.0 285,0
105.5 105,5
97.6 97,6
64.0 64,0
175.0
175,0
760.0
760,0
698.0
698,0
Unit: mm
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LC46X8E
Service Manual
CHAPTER 2. REMOVING OF MAJOR PARTS
[1] REMOVING OF MAJOR PARTS
1. Remove the 2 lock screws , 6 lock screws , 3 lock screws and the 4 lock screws . Detach the Rear Cabinet.
1
2
3
4
REAR CABINET
1
2
3
4
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2. Remove all the connectors from PWBs.
3. Remove the 2 lock screws . and detach the Speaker L/R.
Wire "SP"
Wire "SP-L"
Wire "LB"
Wire "LA"
Wire "SP" to PIN Wire "SP" to WH
Wire "SP"
5
Speaker R
Speaker L
5
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4. Remove all the connectors from PWBs.
#For EMC Set Wire "VD" under Wire "SP-R" (with core)
VD
SP-R
for Wire "VD"
Wire "US" to WH
Wire "KM" to Hook
WH locks Core like this. Lock side set to Panel side #Prevention of contact to CAB-B
Wire "VD","KM to WH
Wire "HM","KM" to WH
Wire "KM" to WH
Wire "VD" to WH
Wire "VD"
Wire "US"
Wire "KM"
Wire "LB", "FR" to WH
Wire "LW" to WH
Wire "LB", "LA" to WH
# For EMC Set Wire "LW" under other wires
Stick insulation tape so as not to put stress on root of wire
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5. Remove all the connectors from PWBs.
6. Remove the R/C, LED Unit.
7. Remove all the connectors from PWBs.
Wire "RA"
R/C, LED PWB Back side
Pull out Wire "RA" from
1st, Set R/C, LED PWB under LIB
Next, Push PWB hooked
Set Wire "RA" to panel hollow
# Set PWB to guide lib
R/C, LED PWB
Wire "RA"
R/C, LED PWB Front side
R/C, LED PWB (with wire)
Wire "RA" to WH
Wire "KM"
Wire "LW"
Wire "PL" Wire "FR"
Wire "LA"
Wire "VD"
FFC "HM"
Wire "US"
Set taping to core inside.
To Main PWB
To Key PWB
Wind wire "KM" one time to core.
Wire "LB"
# For EMC, Set Wire "LW" under other wires
for Wire "KM"
# Wind Wire "KM" one time to core
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8. Remove the 2 lock screws . Detach the MINI AV Sub Ass’y.
9. Remove the 3 lock screws , and 11 lock screws . Detach the Chassis Tray and Side Key Angle.
6
# While fix screw, forcing Mini AV PWB to M-AV KEY
Mini AV Sub Ass'y
6
7
8
Chassis Tray
Side KEY Angle
8
7
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10.Remove the 14 lock screws . and detach the Panel Support Angle.
9
PNL SUPPORT ANG
9
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11.Remove the 4 lock screws , 4 lock screws , and the 4 lock hooks . Detach the LCD Panel Module.
10
11
12
Cushion with washer
10
11
LCD MODULE
12
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12.Remove the 1 lock screw . and detach the Bottom Cover.
13
FRONT CABINET
BOTTOM COVER
13
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13.Remove the 5 lock hooks , 1 lock screw , and 6 lock hooks . and detach the KEY Unit.
14.Remove the 2 lock screws . Detach the MINI AV Unit.
14 15
16
17
M-AV KEY COV
Top View
#Set PWB under LIB
MINI AV PWB
KEY PWB
Back View
15
14
CONTROL BUTTON
KEY PWB
16
MINI AV PWB
MINI-AV SHIELD
17
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15.Remove all the connectors from PWBs.
16.Remove the 10 lock screws . and detach the Main Shield and AV Shield.
18
Wire "LW" to WH
Wire "LW"
AV SHIELD
MAIN SHIELD
Wire "LW"
Pull out Wire "LW" form Opening < Positioning of Wire "PD" >
Wire "PD"
18
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17.Remove all the connectors from PWBs.
18.Remove the 2 lock screws , and the 1 lock screw . Detach the Terminal Angle Bottom.
B to B connection
Pull same time
19
20
TML ANG BTM
19 20
SCART ANGLE
#SCART Angle Stepping on terminal
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19.Remove all the connectors from PWBs.
Wire "VD" to WH #Set Wire "VD" under
Wire "SP-R" FOR EMC
Wire "KM"
FFC "HM"
Wire "RA","US","VD" to WH
#For EMC,Set Wire "VD" under "US","RA"
Wire "KM,"HM" to WH
Wire "RA","US","KM" to WH
Wire "US" Wire "RA"
#Don't make mistake Wire "VD" and "RA"
for Wire "US","RA"
Wire "VD"
Wire "SP-R" #Set at SRC
Core for "SP-R" #Set at SRC
VD
SP-R
FFC "HM" to WH
Wire "VD"
Wire "RA"
Wire "US"
FFC "HM"
Wire "KM"
Wire "LB"
Wire "LA"
Wire "PL"
Wire "FR"
Wire "LB","FR" to WH
Unnecessary
Wire "LB"
Wire "PL"
Wire "FR"
Wire "LW"
Wire "LW"
Wire "LB","FR","PL" to WH
Wire "LB" to WH
Wire "LA"
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LC46X8E
Service Manual
CHAPTER 3. ADJUSTMENT PROCEDURE
[1] ADJUSTMENT PROCEDURE
1. Adjustment method after PWB and/or IC replacement due to repair
The unit is set to the optimum at the time of shipment from the factory. If any value should become improper or any adjustment is necessary due to the part replacement, make an adjustment according to the following procedure.
1. Procure the following units in order to replace the main unit, IC3301, IC8101, IC3501, IC3502, IC8301, IC8302, IC8303, or IC8304.
NOTE: [Caution when replacing ICs in the main unit (IC1501/IC1502/IC1503/IC2002) or the mini av unit (IC802)]
The above ICs are EEPROMs storing the EDID data of HDMI and the monitor microcomputer. Before replacing the relevant part, procure the following parts in which the data have been rewritten.
2. After replacing the LCD panel or LCD control PWB, check PANEL_SIZE in the following procedure.
1) Enter the process adjustment mode.
2) Use the cursor keys ( / ) and P ( / ) of R/C to select the item [PANEL_SIZE] on the page 33/33.
3) Verify that the panel size is displayed.
4) If the size doesn't match, select the values of the panel size with the VOL (+/-) keys.
5) After selection in Step 4), press the OK key, and it is completed with OK displayed.
3. After replacing the LCD panel or LCD control PWB, adjust the VCOM in the following procedure.
1) Enter the process adjustment mode.
2) Use the cursor keys ( / ) and P ( / ) of R/C to select the item [VCOM ADJ] on the page 10/33.
3) Press the OK key to verify that the adjustment pattern is displayed.
4) Use the VOL keys (+/-) of R/C to adjust the flicker in the center of the screen to minimum.
5) When the optimal state is achieved in Step 4, press the OK key to turn the pattern to OFF.
MAIN UNIT: DUNTKE186FM02
IC2002 RH-IXB986WJN8Q Monitor microcomputer IC802 RH-IXC284WJQZS HDMI_EXT4 IC1501 RH-IXC285WJQZS HDMI_EXT5 IC1502 RH-IXC286WJQZS HDMI_EXT6 IC1503 RH-IXC287WJQZS PGB (PC)_EXT7
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2. Entering and exiting the adjustment process mode
1. Press the “POWER” key on the set of running TV set to force off the power.
2. While holding down the “VOL (-)” and “INPUT” keys on the set at once, press the “MAIN POWER” key on the set to turn on the power or plug in the AC power cord to turn on the power.
The letter “K” appears on the screen.
3. Next, hold down the “VOL (-)” and “P (V)” keys on the set at once.
Multiple lines of character string appearing on the screen indicate that the set is now in the adjustment Process mode. If you fail to enter the adjustment process mode (the display is the same as normal startup), retry the procedure. (Another procedure)
4. Another procedure
1) Press the “MENU” key on the main unit to display OSD.
2) Move the cursor to SERVICE (OSD) using the cursor keys on the remote control.
Then press the “MENU” key on the remote control to enter the service mode (adjustment process mode).
5. To exit the adjustment process mode after the adjustment is done, unplug the AC power cord to force off the power. (When the power is turned off with the remote controller, once unplug the AC power cord and plug it in again. In this case, wait 10 seconds or so before plugging.)
3. Remote controller key operation and description of display in adjustment process mode.
1. key operation
Input mode is switched automatically when relevant adjustment is started so far as the necessary input signal is available.
4. Description of display
CAUTION: Use due care in handling the information described here lest the users should know how to enter the adjustment process mode. If the
settings are tampered with in this mode, unrecoverable system damage may result.
Remote controller key Main unit key Function
P (/) P (/)
Moving an item (line) by one (UP/DOWN)
VOL (+/-) VOL (+/-) Changing a selected item setting (+1/-1)
Cursor ( / )
Turning a page (PREVIOUS / NEXT)
Cursor ( / )
Changing a selected line setting (+10/-10)
INPUT SOURCE on remote controller
Input source switching (toggle switching) (TV→EXT1~8)
RETURN Returning to a present page OK Executing a function
No. Description Display specification
(1) Present page/number of total pages 2char/2char Decimal Number mark. (2) Page present title It bundles it by Max. 15 char “[“ ”]”. (3) Input that has been selected now TV/INPUT1/INPUT2/INPUT3/INPUT5/INPUT6/INPUT7/INPUT8 (4) Present colour system NTSC/PAL/SECAM/COMP15K/COMP33K/COMP45K/COMP28K/COMP31K (5) Inducing display EUROPE/RUSSIA/SWEDEN (6) Model name MODEL NAME (7) Item name Max. 30 char (8) Parameter Max. 60 char
(1) Present page/number of total pages (5) Inducing display
(3) Input that has been selected now
(2) Page present title (4) Present colour system (6) Model name
1/33 [INFO] INPUT1 AUTO EURO 46E_X8E
MAIN Version BOOT Version Monitor Version
CPLD Version
FRC Version
EQ DATA CHECKSUM LAMP ERROR MONITOR ERR CAUSE NORMAL STANDBY CAUSE ERROR STANDBY CAUSE
1.10 (E 2008/02/10 D)
1.08
1.05 a6 ROM
0 11 11 11 11 0
1) 0 2) 0 3) 0
0H 0M 0H 0M 0H 0M
4) 0 5) 0
0H 0M 0H 0M
(7) Item name (8) Parameter
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5. Adjustment process mode menu
The character string in brackets [ ] will appear as a page title in the adjustment process menu header.
Page Line Item Description Remarks (adjustment detail, etc.)
1/33 [INFO]
1 MAIN Version Main software version 2 BOOT Version BOOT Version. 3 Monitor Version Monitor software version 4 FRC Version FRC Version 5 CPLD Version CPLD Version. 6 EQ DATA CHECKSUM Audio data checksum. 7 LAMP ERROR Number of termination due to lamp error. 8 MONITOR ERR CAUSE Last error standby cause. 9 NORMALSTANDBY CAUSE Situation that became standby at the end.
(Excluding the error)
10 ERROR STANDBY CAUSE [1] 00H 00M Error standby cause Total operating time before error.
[2] 00H 00M [3] 00H 00M [4] 00H 00M [5] 00H 00M
2/33 [INIT]
1 INDUSTRY INIT Enter Initialization to factory settings execution. 2 INDUSTRY INIT(-Hotel) OFF Initialization to factory settings execution.
(Hotel mode is excluded) 3 HOTEL MODE OFF Hotel mode setting execution. 4 Center Acutime 5H 0M Main operating hours. 5 RESET OFF Main operating hours reset. 6 Backlight Acutime 19H 35M Backlight operating hours. 7 RESET OFF Backlight operating hours reset. 8 LAMP ERROR RESET OFF Lamp error reset. 9 ADJ PARAM SET Enter ADJ PARAM SET
10 VIC XPOS 0 X-coordinate setting for VIC READ 11 VIC YPOS 0 Y-coordinate setting for VIC READ 12 VIC SIGNAL TYPE MAIN Signal type setting for VIC READ 13 VIC READ OFF Picture level acquisition function
(Level appears in green on the upper right)
3/33 [TUNER ADJ]
1 RF AGC ADJ Enter RF-AGC auto adjustment execution 2 TUNER ADJ Enter TUNER auto adjustment execution 3 PAL+TUNER ADJ Enter PAL TUNER auto adjustment execution 4 RF AGC ADJ(CA-8CH) Enter RF-AGC auto adjustment execution (CA-8CH) 5 TUNER ADJ(CA-8CH) Enter TUNER auto adjustment execution (CA-8CH) 6 PAL+TUNER ADJ(CA-8CH) Enter PAL TUNER auto adjustment execution (CA-8CH) 7 RF AGC 16 RF AGC adjustment 8 TUNER DAC 150 TUNER signal level adjustment 9RF AGC READ OFF
4/33 [PAL MAIN]
1 PAL ADJ Enter PAL adjustment 2 SECAM ADJ Enter SECAM adjustment 3 N358 ADJ Enter N358 adjustment 4 PAL CONTRAST 130 PAL contrast adjustment 5 SECAM CONTRAST 137 SECAM CONTRAST adjustment 6 N358 CONTRAST 120 N358 CONTRAST adjustment
5/33 [CEC TEST]
1 HDMI CEC TEST Enter CEC test 2 INSPECT USB TERM Enter 3 MONIDATA READ[TEMP/OPC] OFF MONITOR Temperature/ OPC Acquisition tool. 4 CAUSE RESET Enter
6/33 [COMP15KMAIN]
1 COMP15K ALL ADJ Enter Component 15K picture level adjustment 2 COMP15K MAIN Y GAIN 194 Y GAIN adjustment value 3 COMP15K MAIN CB GAIN 215 Cb GAIN adjustment value 4 COMP15K MAIN CR GAIN 212 Cr GAIN adjustment value 5 COMP15K Y OFFSET 66 Y OFFSET adjustment value 6 COMP15K CB OFFSET 512 Cb OFFSET adjustment value 7 COMP15K CR OFFSET 513 Cr OFFSET adjustment value
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Page Line Item Description Remarks (adjustment detail, etc.)
7/33 [HDTV]
1 HDTV ADJ Enter HDTV video level adjustment 2 HDTV Y GAIN 195 HDTV Y GAIN adjustment value 3 HDTV CB GAIN 205 HDTV Cb adjustment value 4 HDTV CR GAIN 203 HDTV Cr adjustment value 5 HDTV Y OFFSET 65 HDTV Y OFFSET adjustment value 6 HDTV CB OFFSET 512 HDTV Cb OFFSET adjustment value 7 HDTV CR OFFSET 512 HDTV Cr OFFSET adjustment value
8/33 [ANALOG PC]
1 ANALOG PC ADJ Enter DVI ANALOG video level adjustment 2 R OFFSET 64 R CUTOFF adjustment value 3 G OFFSET 64 G CUTOFF adjustment value 4 B OFFSET 66 B CUTOFF adjustment value 5 R GAIN 193 R DRIVE adjustment value 6 G GAIN 189 G DRIVE adjustment value 7 B GAIN 194 B DRIVE adjustment value
9/33 [SCART]
1 SCART RGB ADJ Enter SCART RGB level adjustment 2 SCART R CUTOFF 65 SCART R CUTOFF adjustment value 3 SCART G CUTOFF 60 SCART G CUTOFF adjustment value 4 SCART B CUTOFF 64 SCART B CUTOFF adjustment value 5 SCART R GAIN 200 SCART R GAIN adjustment value 6 SCART G GAIN 195 SCART G GAIN adjustment value 7 SCART B GAIN 201 SCART B GAIN adjustment value
10/33 [LUMAADJ]
1VCOM ADJ 69 2 LCD LUMA ADJ Enter 3 LCD LUMA UP 26 4 LCD LUMA DOWN 13
11/33 [FR DDRTEST]
1 DDRA TEST1 Enter 2 DDRA TEST2 Enter 3 DDRB TEST1 Enter 4 DDRB TEST2 Enter 5 DDRB TEST3 Enter 6 FRC ON/OFF Enter 7 SOUSAM DDR BIST Enter 8 SOUSAS DDR BIST Enter
12/33 [LEV]
1 LEV1 176 2 LEV2 352 3 LEV3 528 4 LEV4 656 5 LEV5 800 6 LEV6 928
13/33 [MGXX1]
1 MG1R 178 W/B adjustment, gradation 1R adjustment value 2 MG1G 184 W/B adjustment, gradation 1G adjustment value 3 MG1B 138 W/B adjustment, gradation 1B adjustment value 4 MG2R 227 W/B adjustment, gradation 2R adjustment value 5 MG2G 232 W/B adjustment, gradation 2G adjustment value 6 MG2B 177 W/B adjustment, gradation 2B adjustment value 7 MG3R 316 W/B adjustment, gradation 3R adjustment value 8 MG3G 322 W/B adjustment, gradation 3G adjustment value 9 MG3B 249 W/B adjustment, gradation 3B adjustment value
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Page Line Item Description Remarks (adjustment detail, etc.)
14/33 [MGXX2]
1 MG4R 474 W/B adjustment, gradation 4R adjustment value 2 MG4G 485 W/B adjustment, gradation 4G adjustment value 3 MG4B 384 W/B adjustment, gradation 4B adjustment value 4 MG5R 791 W/B adjustment, gradation 5R adjustment value 5 MG5G 815 W/B adjustment, gradation 5G adjustment value 6 MG5B 673 W/B adjustment, gradation 5B adjustment value 7 MG6R 905 W/B adjustment, gradation 6R adjustment value 8 MG6G 948 W/B adjustment, gradation 6G adjustment value 9 MG6B 800 W/B adjustment, gradation 6B adjustment value
15/33 [ACTIVEBL1]
1 ABL TEST MODE Enter 2 PRINT DEBUG OFF
16/33 [SOUND1]
1 AUDIO_PARAMETER_SWITCH ROM 2AU_FLAT 3 INPUT_MIXER_GAIN 4 OUTPUT_MIXER_GAIN 5 PEQ1_F0 6 PEQ1_Q 7 PEQ1_GAIN 8 PEQ2_F0 9 PEQ2_Q
10 PEQ2_GAIN 11 PEQ3_F0 12 PEQ3_Q 13 PEQ3_GAIN
17/33 [SOUND 2]
1 PEQ4_F0 2 PEQ4_Q 3 PEQ4_GAIN 4 PEQ5_F0 5 PEQ5_Q 6 PEQ5_GAIN 7 GAIN_ADJUSTER1 8 GAIN_ADJUSTER2 9 GAIN_ADJUSTER3
10 GAIN_ADJUSTER4 11 GAIN_ADJUSTER5 12 GAIN_ADJUSTER6_SP 13 GAIN_ADJUSTER6_HP
18/33 [SOUND 3]
1 LOUT1_VOLUME_CONTROL 2 ROUT1_VOLUME_CONTROL
19/33 [M PWM]
1 2PWM 3PWM FREQ 4 PWM DUTY 5OSC FREQ 6 OSC DUTY
20/33 [M OPC1]
1 OPC LDUTY0 2 OPC LDUTY1 3 OPC LDUTY2 4 OPC LDUTY3 5 OPC LDUTY4 6 OPC LDUTY5 7 OPC LDUTY6 8 OPC LDUTY7 9 OPC LDUTY8
10 OPC LDUTY9 11 OPC LDUTY10 12 OPC LDUTY11
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Page Line Item Description Remarks (adjustment detail, etc.)
21/33 [M OPC2]
1 OPC LDUTY12 2 OPC LDUTY13 3 OPC LDUTY14 4 OPC LDUTY15 5 OPC LDUTY16 6 OPC LDUTY17 7 OPC LDUTY18 8 OPC LDUTY19 9 OPC LDUTY20
10 OPC LDUTY21 11 OPC LDUTY22
22/33 [M OPC3]
1 OPC LDUTY23 2 OPC LDUTY24 3 OPC LDUTY25 4 OPC LDUTY26 5 OPC LDUTY27 6 OPC LDUTY28 7 OPC LDUTY29 8 OPC LDUTY30 9 OPC LDUTY31
10 OPC LDUTY32
23/33 [M ADL1]
1 OPC33 ADLEVEL 0 2 OPC33 ADLEVEL 1 3 OPC33 ADLEVEL 2 4 OPC33 ADLEVEL 3 5 OPC33 ADLEVEL 4 6 OPC33 ADLEVEL 5 7 OPC33 ADLEVEL 6 8 OPC33 ADLEVEL 7 9 OPC33 ADLEVEL 8
10 OPC33 ADLEVEL 9 11 OPC33 ADLEVEL 10 12 OPC33 ADLEVEL 11
24/33 [M ADL2]
1 OPC33 ADLEVEL 12 2 OPC33 ADLEVEL 13 3 OPC33 ADLEVEL 14 4 OPC33 ADLEVEL 15 5 OPC33 ADLEVEL 16 6 OPC33 ADLEVEL 17 7 OPC33 ADLEVEL 18 8 OPC33 ADLEVEL 19 9 OPC33 ADLEVEL 20
10 OPC33 ADLEVEL 21 11 OPC33 ADLEVEL 22
25/33 [M ADL3]
1 OPC33 ADLEVEL 23 2 OPC33 ADLEVEL 24 3 OPC33 ADLEVEL 25 4 OPC33 ADLEVEL 26 5 OPC33 ADLEVEL 27 6 OPC33 ADLEVEL 28 7 OPC33 ADLEVEL 29 8 OPC33 ADLEVEL 30 9 OPC33 ADLEVEL 31
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Page Line Item Description Remarks (adjustment detail, etc.)
26/33 [M V6THE]
1V6 OS THERMO 1 64 2V6 OS THERMO 2 77 3V6 OS THERMO 3 87 4V6 OS THERMO 4 97 5 V6 OS THERMO 5 108 6 V6 OS THERMO 6 119 7 V6 OS THERMO 7 131
27/33 [M V5THE]
1V5 OS THERMO 1 64 2V5 OS THERMO 2 77 3V5 OS THERMO 3 87 4V5 OS THERMO 4 97 5 V5 OS THERMO 5 108 6 V5 OS THERMO 6 119 7 V5 OS THERMO 7 131
28/33 [M BLCTL TEMP]
1BL TEMP1 2BL TEMP2 3BL TDUTY
29/33 [M EEP SET]
1 MONITOR TIME OUT ON Monitor and the main communication time-out setting 2 MONITOR MAX TEMP 43 MONITOR MAX temperature setting 3 MONITOR EEP READ / WRITE WRITE MONITOR EEPROM READ/WRITE Setting/execution 4 MONITOR EEP ADR 0x 0 MONITOR EEPROM arbitrary addressing 5 MONITOR EEP DATA 0x 0 MONITOR EEPROM arbitrary data specification
30/33 [M TEST PATTERN]
1 LCD TEST PATTERN OFF Pattern with built-in LCD controller display
31/33 [MEM CLEAR]
1 KEY LOCK(1217) Enter 2 KOUTEI AREA ALL CLEAR Adjustment value clearness in all areas in process 3 A MODE AREA CLEAR Adjustment value clearness of process A mode 4 BACKUP AREA CLEAR Adjustment value clearness in process backup area 5 B MODE AREA CLEAR Adjustment value clearness of process B mode 6 EXECUTION Clear execution
32/33 [FR REGI]
1 READ/WRITE READ 2 SLAVE ADDRESS SLAVE0 3 REGISTOR ADDRESS 0x 0
0x 0
4 WRITE DATA 0x 0
0x 0
5 READ DATA 0x 0
0x 0
33/33 [ETC]
1 EEP SAVE OFF Writing setting values to EEPROM. 2 EEP RECOVER OFF Reading setting values from EEPROM. 3 MONITOR ERROR CAUSE RESET OFF Reset of monitor error cause. 4 STANDBY CAUSE RESET OFF Reset stand by cause. 5 MODEL NAME X8E Model name setting 6 PANEL SIZE 46 Panel size setting. 7 PRODUCT EEP ADR 0x 0 8 PRODUCT EEP DATA 0x 0
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6. Special features
1. NORMAL STANDBY CAUSE (Page 1/33)
Display of a cause (code) of the last standby.
The cause of the last standby is recorded in EEPROM whenever possible.
Checking this code will be useful in finding a problem when you repair the troubled set.
2. EEP SAVE (Page 33/33)
Storage of EEP adjustment value
3. EEP RECOVER (Page 33/33)
Retrieval of EEP adjustment value from storage area.
7. Lamp error detection
1. Function
This LCD color TV set incorporates a lamp error detection feature that automatically turns off the power for safety under abnormal lamp or lamp circuit conditions. If by any chance anything is wrong with the lamp or lamp circuit or if the lamp error detection feature is activated for some rea­son, the following will result.
1) The power is interrupted in about 6 seconds after it is turned on.
(The power LED on the front of the TV set turns red from green and keeps blinking in red: ON for 250 ms and OFF for 1 sec.).
2) If the above phenomenon 1) occurs 5 times consecutively, it becomes impossible to turn on the power. (The power LED remained red).
2. Measures
1) Checking with lamp error detection OFF
Enter the adjustment process mode, referring to 2. Entering and exiting the adjustment process mode.
If there is a problem with the lamp or lamp circuit, the lamp will go out. (The power LED is green.)
Then, you can check the operation to see if the lamp and lamp circuit are in trouble.
2) Resetting the lamp error count
After the lamp and lamp circuit are found out of trouble, reset the lamp error count. If a lamp error is detected five consecutive times, the power cannot be turned on. Using the cursor (UP/DOWN) key, move to the cursor to [LAMP ERROR RESET], Line 8 on adjustment process mode service page 2/33. With the cursor (LEFT/RIGHT) keys, select the [LAMP ERROR RESET] value. Finally press the cursor (OK) keys to reset the value to “0”.
Table of contents of adjustment process mode Page 2/33
[INIT]
INDUSTRY INIT Enter INDUSTRY INIT(-Hotel) OFF HOTEL MODE OFF Center Acutime RESET
OFF
Backlight Acutime RESET
OFF
LAMP ERROR RESET
OFF ADJ PARAM SET Enter VIC XPOS 0 VIC YPOS 0 VIC SIGNAL TYPE MAIN VIC READ OFF
Resetting to "0"
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8. Public Mode (Hotel Mode)
1. Starting the Public Mode
• There are two following ways to display the PUBLIC Mode setting screen.
1) On the process adjustment mode screen (2/33), set the “HOTEL MODE” Flag to ON.
Turn off the power, and turn it on again, pressing the and keys of the main unit at the same time.
2) Enter the Pass Word, and start the unit.
a) Turn on the power, pressing the and keys of the main unit at the same time.
b) Display the Pass Word input screen.
Operation procedure
• The initial input position is the digit at the left end.
• For the numeric keys to of R/C, key input is accepted. Input of the other keys is prohibited.
• Change “-” to “*” by inputting the numeric key at the input position, and shift the input position rightward one digit.
• When three digits are completely input, the Pass Word is judged.
c) Check the Pass Word by inputting three digits.
If the Pass Word is , it shifts to the PUBLIC Mode setting screen.
In another case, the screen is erased, and it operates in the ordinary mode.
2. Exiting the Public Mode screen
• There are two following ways to exit the Public Mode setting screen.
1) Turn off the power.
2) Select “EXECUTE” in the PUBLIC_Mode to execute it.
Activate the restart under the set content. Here, the START input SOURCE setting is excluded since this item is referred to only when the power is turned on.
3. Set value of the Public Mode
• Each set value in the PUBLIC Mode is initialized when the factory setting is applied.
(The setting of the PUBLIC MODE Flag in the process adjustment mode screen is not changed.)
CHANNEL UP
Volume UP
INPUT
Volume UP
0
9
0
2 7
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4. Basic operation in the Public Mode
5. Operation after “RESET”
Select “RESET” in the PUBLIC Mode, and it operates as follows when it is executed (refer to the basic operation).
• The set contents in the PUBLIC mode are initialized.
• It does not exit the PUBLIC mode.
• PUBLIC MODE Flag does not change. (It is not set to OFF.)
Volume (+/-) or Cursor ( / )
Change or execution of the set value.
Channel ( / ) or Cursor ( / )
Movement to the selected item.
Decision (ok) Execution (Used by the items “Execution” and “RESET”.) PUBLIC Mode R/C Ordinary operation mode: It enters the PUBLIC Mode.
PUBLIC MODE Flag is set to “ON”.
PUBLIC Mode: It exits the PUBLIC Mode.
PUBLIC MODE Flag does not change. Any set item in PUBLIC Mode is not initialized.
Public Mode
POWER ON FIXED [VARIABLE]
SHUT DOWN MODE [NORMAL]
MAXIMUM VOLUME [60]
VOLUME FIXED [VARIABLE]
VOLUME FIXED LEVEL [20]
RC BUTTON [RESPOND]
PANEL BUTTON [RESPOND]
MENU BUTTON [RESPOND]
AV POSITION FIXED [VARIABLE]
ON SCREEN DISPLAY [YES]
INPUT MODE START [NORMAL]
INPUT MODE FIXED [VARIABLE]
LOUD SPEAKER [ON]
RC PATH THROUGH [OFF]
232C POWON [DISABLE]
HOTELMODE [ON]
RESET
EXECUTE
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6. Setting items (* Item names and selective items are expressed in English.)
1) Power ON Fixed (POWER ON FIXED)
If the power button is pressed in the ordinary mode when set to “FIXED”, the caution is displayed for 5 seconds.
When power button on the main unit is pressed When power button on R/C is pressed
* The OSD display is an example.
If another ODS is previously displayed, the status is reset (MENU or similar).
2) Volume Maximum Level [MAXIMUM VOLUME]
3) Volume Fixed [VOLUME FIXED]
4) Volume Fixed Level [VOLUME FIXED LEVEL]
Selection “VARIABLE” or “FIXED” is selectable. (Loop is provided.) Default “VARIABLE” Function • When "FIXED" is set, “Power ON/Standby Key” of the main unit and R/C is disabled. Keys disabled when not set to Default
• OFF_TIMER (SLEEP)
Remarks The function does not work for any other standby factors (see below).
• No operation OFF
• No signal OFF (including the power management)
Selection 0~60 (Loop is not provided.) Default 60 Function • Even if VOL is adjusted to a value higher than the adjusted one, it is not set to that value. (Only the speakers of
the main unit) Exception Remarks • When it is set to 59 or less, the number is displayed and the volume bar is not displayed during operation in the
ordinary mode.
• VOLUME can be abbreviated to VOL.
Selection “VARIABLE” or “FIXED” is selectable. (Loop is provided.) Default “VARIABLE” Function It is selectable whether or not the volume is fixed to the value adjusted in the volume fixed level mode. (Only the
speakers of the main unit) Exception • In the adjustment process, the volume can be set as desired regardless of this setting. Keys disabled when not
set to Default
• Volume high/low (VOL+/-) (Both R/C and main unit)
• Mute (MUTE)
Remarks • Volume Fixed is prior to Volume Maximum Level.
• Even if the above disabled keys are operated, the volume is not displayed.
• VOLUME can be abbreviated to VOL.
Selection 0~60 (Loop is not provided.) Default Currently set volume Function The volume is fixed to the adjusted value. (Only the speakers of the main unit) Exception • In the adjustment process, the volume can be set as desired regardless of this setting. Keys disabled when not set to Default Remarks • When Volume Fixed is set to “VARIABLE”, the setting is inhibited to change.
• VOLUME can be abbreviated to VOL.
No Power off by power button. No Power off by remote control.
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5) R/C Operation [RC BUTTON]
6) Main Unit Operation [PANEL BUTTON]
7) MENU Operation [MENU BUTTON]
8) OSD Display [ON SCREEN DISPLAY]
9) Start Mode [INPUT MODE START]
Selection “RESPOND” or “NO RESPOND” is selectable. (Loop is provided.) Default RESPOND Function R/C key operation is set.
When set to “NO RESPOND”, the R/C keys are disabled in the ordinary mode.
The power key (Power ON/Standby Key) is also disabled. Exception • Regardless of the setting contents, the process mode, inspection mode and PUBLIC_Mode Key are enabled.
• Regardless of the setting contents, all keys can be used while entering the process mode, inspection mode or PUBLIC_Mode.
Remarks The CARD function stops all functions including the input switching and direct key when set to “NO RESPOND”.
Selection “RESPOND” or “NO RESPOND” is selectable. (Loop is provided.) Default RESPOND Function NO RESPOND: Excluding power supply (Video/Standby key), the main unit keys are disabled. Exception • Regardless of the setting contents, the start operation of the process mode, inspection mode and PUBLIC_Mode
is enabled.
• Regardless of the setting contents, all keys can be used while entering the process mode, inspection mode and PUBLIC_Mode.
Selection “RESPOND” or “NO RESPOND” is selectable. (Loop is provided.) Default RESPOND Function The MENU keys on the main unit and R/C MENU are disabled. Exception • Regardless of the setting contents, the start operation of the process mode, inspection mode and PUBLIC_Mode
is enabled.
• Regardless of the setting contents, all keys can be used whileentering the process mode, inspection mode or PUBLIC_Mode.
Key that becomes invalid excluding Default besides MENU Key because of setting
ON_TIMER, Auto Preset, Manual_Memory, and clock setting All Direct Shift keys to the MENU display
Remarks When set to “NO RESPOND”,
• ON_TIMER is set to “OFF”.
Selection “YES” or “NO” is selectable. (Loop is provided.) Default YES Function When set to “NO”, the following OSD is not displayed.
Register, Setting, Adjustment MENU, Channel_Call, Volume Bar In the case of Wide Model, if the following operation is performed, it is immediately switched (since MENU can not be displayed).
Input switching Keys which can be enabled (Exquisite
example)
Brightness sensor, light control
Keys disabled when not set to Default (Example)
Still screen, screen display, MENU, OFF_TIMER, A V Position, Wide Mode switch, Auto Instolation
Remarks • When set to “NO”,
a) The OFF_TIMER (SLEEP TIMER) setting time is cleared.
Selection “NORMAL”, “TV(*Channel)”, “INPUT1”, “INPUT2” (Loop is provided.) Default NORMAL Function When the power is ON, the input source or channel to start is set.
In the NORMAL mode, it follows the contents of Last_Memory. Remarks • When set to a mode other than “NORMAL”,
a) It is inhibited to display the Channel Setting MENU and to set the Channel. b) On start with “ON_TIMER”, the set Channel of ON_TIMER is prior.
• When set to “NORMAL”, “Mode Fixed (START MODE FIXED)” is set to “VARIABLE” to inhibit the selection.
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10)Mode Fixed [INPUT MODE FIXED]
9. Video signal adjustment procedure
* The adjustment process mode menu is listed in Section 4.
Signal generator level adjustment check (Adjustment to the specified level)
1. Entering the adjustment process mode
Enter the adjustment process mode according to Section 2.
2. RF AGC adjustment
3. PAL signal & tuner adjustment
Selection “VARIABLE” or “FIXED” is selectable. (Loop is provided.) Default VARIABLE Function When set to “FIXED”, it is disable to switch to other channel or input after start in the set value of “Start Mode (INPUT
MODE START)”. Keys disabled when not set to Default (Example)
Channel UP/Down, Direct, Channel Button, FLASHBACK, INPUT, STILL, Digit Select and Direct input switching
Remarks • When “START MODE” is set to “NORMAL”, this item is disable to set. (Automatically set to “VARIABLE”.)
• When set to “FIXED”, The Channel setting MENU (Menu-setup-Auto Installation, Programme setup and Child Lock item hatching) and Input Selection MENU in MENU are not displayed.
• Composite signal PAL : 0.7Vp-p ± 0.02Vp-p (Pedestal to white level)
• RGB signal : 0.7Vp-p ± 0.02Vp-p
• 15K component signal (50 Hz) : Y level : 0.7Vp-p ± 0.02Vp-p (Pedestal to white level) : PB, PR level : 0.7Vp-p ± 0.02Vp-p
Adjustment point Adjustment Conditions Adjustment procedure
1 Setting [Signal]
PAL Split Field Colour Bar RF signal U/V
[Terminal] TUNER
• Feed the PAL Split Field colour bar signal (E-12ch) to TUNER. Signal level: 55 dB µV ± 1dB (75 LOAD)
2 Auto adjustment
performance
Page 3/33 Bring the cursor on [RF AGC ADJ] and press [OK] [RF AGC ADJ OK] appears
when finished.
Adjustment point Adjustment Conditions Adjustment procedure
1 Setting [Signal]
PAL Full Field Color Bar Composite or RF signal
[Terminal] EXT1 SCART IN TUNER
• Feed the PAL full field colour bar signal (75% colour saturation) to EXT1 SCART IN.
• Feed the RF signal (PAL colour bar) to TUNER.
• Make sure the PAL colour bar pattern has the sync level of 7:3 with the pic­ture level.
2 Auto adjustment
performance
Page 3/33 Bring the cursor on [PAL+TUNER ADJ] and press [OK] [PAL+TUNER ADJ OK]
appears when finished.
[E-12CH]
100% white
100% white
VIDEO IN SIGNAL]
100% white
[RF Signal]
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4. SECAM adjustment
5. ADC adjustment (Component 15K)
6. ADC adjustment (Component 33K)
Adjustment point Adjustment Conditions Adjustment procedure
1 Setting [Signal]
SECAM Full Field Colour Bar signal
[Terminal] EXT1 SCART IN
• Feed the SECAM full field colour bar signal (75% colour saturation) to EXT1 SCART IN.
2 Auto adjustment
performance
Page 4/33 Bring the cursor on [SECAM ADJ] and press [OK] [SECAM ADJ OK] appears
when finished.
Adjustment point Adjustment Conditions Adjustment procedure
1 Setting [Signal]
COMP15K, 50Hz 100% Full Field Colour Bar sig­nal
[Terminal] EXT8 COMPONENT IN
• Feed the COMPONENT 15K 100% full field colour bar signal (100% colour saturation) to EXT8 COMPONENT IN.
2 Auto adjustment
performance
Page 6/33 Bring the cursor on [COMP15k ALL ADJ] and press [OK] [COMP15k ALL ADJ
OK] appears when finished.
Adjustment point Adjustment Conditions Adjustment procedure
1 Setting [Signal]
COMP33K, 50Hz 100% Full Field Colour Bar sig­nal
[Terminal] EXT8 COMPONENT IN
• Feed the COMPONENT 33K 100% full field colour bar signal (100% colour saturation) to EXT8 COMPONENT IN.
2 Auto adjustment
performance
Page 7/33 Bring the cursor on [HDTV ADJ] and press [OK] [HDTV ADJ OK] appears when
finished.
100% white
Black
100% white
Black
100% white
Black
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7. DVI-I adjustment (ANALOG D-sub15PIN)
8. RGB adjustment (SCART)
10. White Balance Adjustment
Adjustment gradation values (IN) appear on page 12/33 of process adjustment, and adjustment initial values (offset value) appear on pages 13/33 and 14/33.
For white balance adjustment, adjust the offset values on pages 13/33 and 14/33.
[Condition of the unit for inspection]: Modulated light: MAX (+8)
[Adjustment reference device] : Minolta CA-210
[Adjustment]
Check that the values on page 12/33 of process adjustment are set as below. If not, change them accordingly.
1) Display the current adjustment status at point 6. (Page 12/33 of process adjustment)
The display for checking the adjustment status is toggled by pressing the “6” button on the remote control.
(Normal OSD display “6” display for check (OSD disappears) “6” normal OSD display . . . )
2) Read the value of the luminance meter. x=0.272, y =0.277
3) Change MG6R/MG6B (Adjustment offset value) on page 14/33 of process adjustment so that the values of the luminance meter approach x=0.272 and y =0.277.
(Basically, G is not changed. If adjustment fails with R and B, change G. When G is lowered, the weaker of R and B must be fixed.)
4) Display the adjustment status of the current point 5. (Each time the “5” button on the remote control is pressed, the adjustment status check dis­play is toggled.)
(Normal OSD display “5” Check display (OSD disappears) “5” Normal OSD display . . . )
Change MG5R/MG5B (adjustment offset value) on page 14/33 of process adjustment so that the values of the luminance meter approach x =
0.272 and y = 0.277.
Adjustment point Adjustment Conditions Adjustment procedure
1 Setting [Signal]
XGA 60Hz 100% Full Field Colour Bar sig­nal
[Terminal] EXT7 PC IN
• Feed the XGA 60Hz 100% full field colour bar signal (100% colour satura­tion) to EXT7 PC IN.
2 Auto adjustment
performance
Page 8/33 Bring the cursor on [ANALOG PC ADJ] and press [OK] [ANALOG PC ADJ OK]
appears when finished.
Adjustment point Adjustment Conditions Adjustment procedure
1 Setting [Signal]
RGB15K, 50Hz 100% Full Field Colour Bar sig­nal
[Terminal] EXT1 SCART IN
• Feed the RGB15k 50Hz 100% full field colour bar signal (100% colour satu­ration) to EXT1 SCART IN.
2 Auto adjustment
performance
Page 9/33 Bring the cursor on [SCART RGB ADJ] and press [OK] [SCART RGB ADJ OK]
appears when finished.
Point 1 (LEV1) 176 Point 2 (LEV2) 352 Point 3 (LEV3) 528 Point 4 (LEV4) 656 Point 5 (LEV5) 800 Point 6 (LEV6) 928
100% white
Black
100% white
Black
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5) Repeat step 4) for points 4, 3, 2, and 1.
[Adjustment reference standard value]
Adjustment spec ± 0.002 Inspection spec ± 0.004 (point 1 and 2)
Adjustment spec ± 0.001 Inspection spec ± 0.002 (Excluding the above-mentioned)
* Adjusting procedure by use of [RS-232C]
1. Get ready the PC with COM port (RS-232C) running on Windows 95/98/ME/2000/XP operating system, as well as the RS-232C cross cable.
2. Start the unit with the RS-232C cable connected.
3. Start the terminal software. (The freeware readily available on the Internet will do.)
4. Make the following settings.
5. If the settings are correct, the terminal software indicates “ERR” against pressing of the “ENTER” key.
6. After the settings are done correctly, it is possible to make an adjustment by typing in the command shown in the table below and pressing the “ENTER” key on the keyboard.
7. Command entry is successful if the terminal software indicates “OK” when the “ENTER” is pressed. If “ERR” is shown, retry to enter the command.
8. Send the process mode switching command to switch from the RS232C operation mode to the process mode.
KRSW0001: “ERR” is returned.
KKT10037: When “OK” is returned, the process mode becomes active. When “ERR”, start over from KRSW0001.
9. Send each adjustment command.
RS-232C command list
Baud rate 9,600 bps Data LENGTH 8 bit Parity bit None Stop bit 1 bit Flow control None
Command Function Remarks
KYOF0000 Remote control disabled OSDS0001 OSD display inhibited SBSL0016 Light control level MAX MSET0001 Background adjustment start MSET0004 Initialization of adjustment value LEV60928 Graduation 6 (928-graduation adjustment) MG6G **** Adjustment of G of graduation 6 0000 ~ 4095 MG6R **** Adjustment of R of graduation 6 0000 ~ 4095 MG6B **** Adjustment of B of graduation 6 0000 ~ 4095 LEV50800 Graduation 5 (800-graduation adjustment) MG5G **** Adjustment of G of graduation 5 Calculated value MG5R **** Adjustment of R of graduation 5 0000 ~ 4095 MG5B **** Adjustment of B of graduation 5 0000 ~ 4095 LEV40656 Graduation 4 (656-graduation adjustment) MG4G **** Adjustment of G of graduation 4 Calculated value MG4R **** Adjustment of R of graduation 4 0000 ~ 4095 MG4B **** Adjustment of B of graduation 4 0000 ~ 4095 LEV30528 Graduation 3 (528-graduation adjustment) MG3G **** Adjustment of G of graduation 3 Calculated value MG3R **** Adjustment of R of graduation 3 0000 ~ 4095 MG3B **** Adjustment of B of graduation 3 0000 ~ 4095 LEV20352 Graduation 2 (352-graduation adjustment) MG2G **** Adjustment of G of graduation 2 Calculated value MG2R **** Adjustment of R of graduation 2 0000 ~ 4095 MG2B **** Adjustment of B of graduation 2 0000 ~ 4095 LEV10184 Graduation 1 (176-graduation adjustment) MG1G **** Adjustment of G of graduation 1 Calculated value MG1R **** Adjustment of R of graduation 1 0000 ~ 4095 MG1B **** Adjustment of B of graduation 1 0000 ~ 4095 MSET0003 Writing of adjustment value
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11. Confirmation item
1. Magi-Link Inspection
The thing that the Magi-Link circuit operates is confirmed.
2. HDMI-CEC Inspection
The thing that the HDMI-CEC circuit operates is confirmed.
12. Initialization to factory settings
13. Upgrading the software
1. Turn off the AC power (Unplug the AC power cord).
2. Insert the upgrading USB flash memory for upgrade into the service slot.
3. While holding down the power button, plug in the AC power cord of the main unit to turn on the power.
4. Upgrade begins automatically.
After the set starts, the upgrade screen like the figure below is displayed.
CAUTION: When the factory settings have been made, all user setting data, including the channel settings, are initialized.
(The adjustments done in the adjustment process mode are not initialized.) Keep this in mind when initializing these settings.
Adjustment item Adjustment conditions Adjustment procedure
1 Factory settings ends by turning off the
MAIN POWER key. (See to below caution)
[Factory setting with adjustment process mode]
• Enter the adjustment process mode.
• Move the cursor to [INDUSTRY INIT] on page 2/33.
• Use the R/C key to select a region from [EUROPE/RUSSIA/SWEDEN] and press the [OK] key.
• “EXECUTING” display appears.
• After a while, “SUCCESS” display appears, the setting is completed.
When succeeding: Background color (green) When failing: Background color (red) The following items are initialized in the factory setting.
1) User settings
2) Channel data (e.g. broadcast frequencies)
3) Maker option setting
4) Password data
After adjustments, exit the adjustment process mode. To exit the adjustment process mode, turn off the MAIN power key. When the power is turned off with the remote control, unplug the AC power cord and plug it back in.
<SYSTEM UPGRADE>
System Version: E0708021
BANK 1
BANK 2
STATUS UPDATING. . .
30%
0%
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5. If any of the procedures fails, the following upgrade failure screen shows up. For the failing procedure, the “NG” marking turns red.
NOTE: In such case, try to upgrade the software again. If it still fails, the hardware may be in trouble.
6. When all the procedures are complete, the following upgrade success screen shows up. The new software version can be confirmed on screen. The version number appears when each item has been successfully upgraded. Finally the main version number appears on screen.
7. Turn off the AC power (Unplug the AC power cord). Take out the upgrading USB flash memory.
8. Now the software has been upgraded.
NOTE: Then get the set started and call the process adjustment screen 1/33 to check the main software version.
CAUTION
1) Do not take out and put in the USB flash memory during formatting.
2) It takes about one minute to the rewriting completion.
Please confirm the upgrade status on the screen becomes 100%.
<SYSTEM UPGRADE>
System Version: E0708021
BANK 1
OK
BANK 2
STATUS UPDATING. . .
100%
44%
<SYSTEM UPGRADE>
System Version: E0708021
BANK 1
OK
BANK 2
OK
STATUS
UPGRADE COMPLETE
100%
100%
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LC46X8E
Service Manual
CHAPTER 4. TROUBLESHOOTING TABLE
[1] TROUBLESHOOTING TABLE
Power unit operation check.
Are the power cord and harness in the unit properly connected? NO Connect the power cord and harness properly, and turn on the
power.
LINE_FILTER_UNIT: YES Is F7000 normal?
NO
LINE_FILTER_UNIT: Isn't FL7001, L7001, R7002, CX7000-1, Z7000, etc. out of order? Moreover, whether the short-circuit with the circumference circuit is checked. POWER_UNIT: BD7000, TH7000-1, IC7801,Z7800, etc. out of order? Moreover, whether the short-circuit with the circumference circuit is checked.
POWER_UNIT YES Is B_BUS (+320V) output? (Set the main power SW to OFF.)
* When power on/off switch is on • • • About +400V
NO Does the PFC circuit operate normally?
(L7800, L7801, T7800, D7806, Q7804-5, IC7800-1 and etc. And, the circuit around the protection circuit etc. is checked.)
YES
Is a voltage of BU5V applied to pin (8) of connector (PD)? (Set the main power SW to OFF.)
NO Does the switching circuit operate normally?
Check circuit around the primary side (T7901, IC7905, Q7902, Q7912-3, D7908-9, D7904, D7910, etc.), the secondary side (D7918, L7900, etc.), the AC_DET circuit (D7911-2, IC7909, IC7902, Q7910, Q7901, etc.), and the protection circuit.
YES Are INV60V, UR15, and S15V output as for the power on/off switch when it is on?
NO Does the inverter circuit operate normally?
Check circuit around the primary side (T7001, T7601, IC7603, IC7601, IC7600, Q7600-2, D7608, D7610, D7613, etc.), the sec­ondary side (D7560-3, L7560, D7150-1, L7150, L7152, Q7911, etc.), the PS_ON circuit (Q7300-1, etc.), and the protection cir­cuit.
YES Similarly, is PNL12V output as for the power on/off switch when it is on?
NO Check PNL_POW circuit of Q7121-2, etc. and the circuit around
the regulator circuit etc. of IC7121, L7121, D7121, etc.
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The sound is not emitted from the speaker though the picture has come out.
No sound output in all modes.
TERMINAL UNIT: Is the audio signal (L/R) output from pins (38, 39) of IC1404 (CODEC) normal?
NO Check IC1404 and its peripheral circuits.
YES Is audio signal (L/R) input to pin (5, 9) of IC1301 (AMP)? NO Check the line between IC1404 and IC1301.
YES Is MUTE circuit [SP_MUTE_LINE, S_STBY_LINE] normal? NO This signal is usually “L”.
Check the SP_MUTE_LINE and S_STBY_LINE. (Q1302, etc.)
YES Is the audio signal (L/R) output from pins (1, 2) and pins (3, 4) of P1301 (AOUDIO-CONNECTOR) normal?
NO Check IC1301 and its peripheral circuits.
YES Check Speaker Box (right and left) and wire harness.
No sound (during the reception of TV(ANALOG) broadcasting)
The sound does not come out though the picture come out when UHF\VHF is received.
TERMINAL UNIT: Is the IF signal output from pin (17) of TUNER (TU7501)? NO Check the tuner and its peripheral circuits.
Replace as required.
YES Is the SIF signal sent to pins (23) and (24) of IC7504 (IFDE-
MOD)?
NO Check FL7501 and its peripheral circuits.
YES Is the SIF signal input from pin (12) of IC7504 to pin (3) of IC1402 (SOUND MULTIPLEX DECODER)?
NO Check the line between IC7504 and IC1402.
(Q7504, etc.)
YES Is audio signal (L/R) input from pin (24, 22) of IC1402 to pin (61,
62) of IC1404 (CODEC)?
NO Check the line between IC1402 and IC1404.
YES Refer to “No sound output in all modes”.
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No sound (during the reception of TV (DIGITAL) broadcasting)
The sound does not come out though the picture come out when DTV is received?
MAIN UNIT: Is DTV_SPDIF audio signal output from pin (T2) of IC8101 (CPU/ DECODER) to pin (42) of connector SC1101?
NO Check the line between IC8101 and SC1101, and their peripheral
circuits.
TERMINAL UNIT: YES Is DTV_SPDIF audio signal input from pin(42) of connector
SC501 to pin(4) of IC1404(CODEC)?
NO Check the line between SC501 and IC1404.
(SC1101/SC501, etc.)
YES Refer to “No sound output in all modes”.
No sound from external input devices (1)
The audio input from EXT-1 doesn’t come out. The audio input from EXT-2 doesn’t come out.
TERMINAL UNIT: EXT1 Is the audio signal (IN1_L/IN1_R) properly sent to pins (6, 2) of SCART1 (SC502)?
NO Check the setting of an external input device that connects of
SC502.
EXT2 Is the audio signal (IN2_L/IN2_R) properly sent to pins (6, 2) of SCART2 (SC503)?
NO Check the setting of an external input device that connects of
SC503.
YES EXT1 Is the audio signal (IN1_L/IN1_R) properly sent to pins (51, 52) of IC1404 (CODEC)?
NO Check the line between SC502 and IC1404.
EXT2 Is the audio signal (IN2_L/IN2_R) properly sent to pins (53, 54) of IC1404 (CODEC)?
NO Check the line between SC503 and IC1404.
YES Refer to “No sound output in all modes”.
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No sound from external input devices (2)
The sound input from EXT3 doesn’t come out.
MINI AV_UNIT: Is audio signal (IN3_L/R) input from pins (5, 4) of EXT3 terminal (J901) to pins (3, 1) of connector (P901)?
NO Check connection of between from J901 to P901 and the exter-
nal input device.
TERMINAL UNIT: YES Is audio signal (IN_3_L/IN_3_R) input to pins (3, 1) of connector
(P501)?
NO Check the connector (P901/P501).
YES Is audio signal (IN3_L/IN_3_R) input to pins (55, 56) of IC1404 (CODEC)?
NO Check the line between P501 and IC1404.
YES Refer to “No sound output in all modes”.
No sound from external input devices (3)
The audio input from EXT4/5/6 (HDMI) doesn’t come out.
Is the picture of the signal input from EXT4/5/6 displayed? NO Check the connection of EXT4/5/6 and an external device.
MAIN UNIT: YES Is the HDMI_SPDIF audio signal output from pin (W12) of IC3301 (VIDEO PROCESSOR) to pin (44) of connector (SC1101)?
NO Check the line between IC3301 and SC1101, and their peripheral
circuits.
TERMINAL UNIT: YES Is HDMI_SPDIF audio signal input from pin (44) of connector
(SC501) to pin (5) of IC1404 (CODEC)?
NO Check the line between SC501 and IC1404.
(SC1101/SC501, etc.)
YES Refer to “No sound output in all modes”.
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No sound from external input devices (4)
The sound input from EXT6 (analog HDMI) doesn’t come out. The sound input from EXT7 (analog RGB audio) doesn’t come
out.
MAIN UnIT:
Check whether “Analog” has selected in MENU-Option -HDMI Audio Select.
MAIN UNIT: YES
Is audio signal (L/R) sent from pins (2, 3) of EXT6 terminal (J1502) to pins (1, 6) of IC1504 (SW)?
YES Is audio signal (L/R) sent from pins (2, 3) of EXT7 terminal
(J1501) to pins (3, 7) of IC1504 (SW)?
NO NO Check the J502 (EXT6), peripheral circuit and connection of external input devices.
Check the J501 (EXT7), peripheral circuit and connection of external input devices.
Is audio signal (HDMI_PC_L/HDMI_PC_R) output from pins (15, 11) of IC1504 to pins (24, 26) of connector (SC1101)?
TERMINAL UNIT: YES
NO Check the line between IC1504 and SC1101, and their peripheral circuits.
Is audio signal (HDMI_PC_L=MAIN_L, HDMI_PC_R=MAIN_R) sent to pins (24) and (26) of SC501?
NO Check the connector (SC1101/SC501)
YES Is audio signal (MAIN_L/MAIN_R) input to pins (59, 60) of IC1404 (CODEC)?
NO Check the line between SC501 and IC1404.
YES Refer to “No sound output in all modes”.
No sound from external input devices (5)
The sound input from EXT8 doesn’t come out.
TERMINAL UNIT: Is audio signal (IN4_L/IN4_R) input from pins (2, 4) of the EXT8
terminal (J502)?
NO Check the connection to J502 and external devices.
YES Is audio signal (IN4_L/IN4_R) input to pins (57, 58) of IC1404 (CODEC)?
NO Check the line between J502 and IC1404.
YES Refer to “No sound output in all modes”.
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The audio signal is not output (1)
The audio signal of UHF/VHF and DTV is not output from EXT1 (SCART1).
TERMINAL UNIT: Is audio signal (L/R) output from pins (3, 1) of SCART1 (SC502)? YES Check the connection to SCART1 and external devices.
NO
Is S-MUTE signal [MAIN_UNIT pin (93) of IC9101 (CPLD)] at H? YES This signal should be “L”.
Check the peripheral circuits of IC9101 and S-MUTE signal. (Q502, Q504, etc.)
NO
Is audio signal (L/R) output from pins (24, 22) of IC1402 (SOUND MULTIPLEX DECODER)?
YES Check the line between SC502 and IC1402.
(Q508, Q507, IC1407, etc.)
NO
Check IC1402 and its peripheral circuits.
The audio signal is not output (2)
The audio signal of UHF/VHF and DTV is not output from EXT2 (SCART2).
TERMINAL UNIT: Is audio signal (L/R) output from pins (3, 1) of SCART2 (SC503)? YES Check the connection to SCART2 and external devices.
NO Is S2-MUTE signal [MAIN_UNIT pin (91) of IC9101 (CPLD)] at H?
YES This signal should be “L”.
Check the peripheral circuits of IC9101 and S2-MUTE signal. (Q501, Q503, etc.)
NO Is audio signal (L/R) output from pins (3, 13) of IC7510 (SW)? YES Check the line between IC7510 and SC503.
(Q506, Q505, etc.)
NO Is audio signal (L/R) input to pins (2, 15) of IC7510 (SW)? YES Check IC7510 or peripheral circuits.
(SC_AUD_SEL signal, etc.)
NO Is audio signal (L/R) output from pins (24, 22) of IC1402 (SOUND MULTIPLEX DECODER)?
YES Check the line between IC7510 and IC1402.
(IC1407, etc.)
NO Check IC1402 and its peripheral circuits.
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The audio signal is not output (3)
The audio signal of MONITOR is not output from EXT2 (SCART2).
TERMINAL UNIT: Is audio signal (L/R) sent to pins (3, 1) of SCART2 (SC503)? YES Check the connection to SCART2 and external devices.
NO Is S2-MUTE signal [MAIN_UNIT pin (91) of IC9101 (CPLD)] at
H?
YES Check the peripheral circuits of IC9101 and S2-MUTE signal.
(Q501, Q503, etc.)
NO Is audio signal (L/R) sent to pins (3, 13) of IC7510 (SW)? YES Check the line between IC7510 and SC503.
(Q506, Q505, etc.)
NO Is audio signal (L/R) input to pins (1, 12) of IC7510 (SW)? YES Check IC7510 or peripheral circuits.
(SC_AUD_SEL signal, etc.)
NO Is audio signal (L/R) output from pins (40, 41) of IC1404 (CODEC)?
YES Check the line between IC7510 and IC1404.
(IC1405, etc.)
NO Check IC1404 and its peripheral circuits.
The audio signal is not output (4)
No audio signal output from AUDIO_OUTPUT terminal.
TERMINAL UNIT: Is audio signal (L/R) output from pins (2, 4) of audio output termi­nal (J503)?
YES Check the connection to J503 and external devices.
NO MONITOR_MUTE signal [pin (72) of IC506
(VIDEO_SELECTOR)] or MUTE-A_ALL signal [pin (55) of IC2002 (UCON)] will be “H”?
YES This signal should be “L”.
Check IC506, IC2002, and its peripheral circuits.
NO Is the audio signal (L/R) output from pins (40, 41) of IC1404
(CODEC)?
YES Check the line between IC1404 and J503.
(IC1405, Q509, Q510, etc.)
NO Check IC1404 and its peripheral circuits.
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The audio signal is not output (5)
No audio signal output from DIGITAL_AUDIO_OUTPUT terminal.
TERMINAL UNIT: Is digital audio signal (OPT_OUT) output to pin (1) of optical fiber transmitter (D501)?
YES Check D501 or peripheral circuits.
(B3.3V_LINE, etc.)
NO SPDIF_MUTE signal [pin (92) of IC9101 (CPLD)] or MUTE-
A_ALL signal [pin (55) of IC2002 (UCON)] will be “H”?
YES This signal should be “L”.
Check IC9101, IC2002, and its peripheral circuits.
NO Is digital audio signal (OPT_OUT) output from pin (23) of IC1404 (CODEC) to pin (2) of IC502 (AND GATE)?
YES Check IC502 or peripheral circuits.
NO Check IC1404 and its peripheral circuits.
The audio signal is not output (6)
No sound from HEADPHONE_OUTPUT terminal.
MINI AV_UNIT: When headphone is connected, does the HP_PLUG signal of the
pin (6) become “H” (about 3.3V) from “L” (0V).
NO Check the line between J802 and IC9101.
(P801/P1101, IC9105, etc.)
YES Is the audio signal (HP_L/HP_R) output to pins (2, 3) of head­phone terminal J802?
YES Check HEAD-PHONE (J802) or peripheral circuits.
MAIN UNIT: NO Is the audio output signal (HP_LOUT/HP_ROUT) send from pins (68, 70) of connector (SC1101) to pins (5, 7) of connector (P801/
P1101)?
YES Check the line between P1101 and J802.
(P801/P1101, etc.)
TERMINAL UNIT: NO Is audio output signal (HP_LOUT/HP_ROUT) sent to pins (68,
70) of connector (SC501)?
YES Check the connector SC501/SC1101.
NO Is audio output signal (HP_LOUT/HP_ROUT) output from pins
(36, 35) of IC1404 (CODEC)?
YES Check the connector SC501/SC1101.
NO Check whether the HP_MUTE signal is “H” [pin (86) of IC9101 (CPLD)]. This signal should be “L”.
YES Check Q1401, Q1402 or peripheral circuits.
NO Check IC1404 (CODEC) or peripheral circuits.
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No picture on the display (1)
The picture doesn't appear in all modes.
MAIN UNIT: Is LVDS signal output from 1st_channel and 2nd_channel of IC3301(VIDEO PROCESSER) in each mode? TA1 ± (A14/B14), TB1± (A15/B15), TC1± (A16/B16), TD1± (A18/B18), TE1± (A19/B19), TCLK1± (A17/B17), TA2± (A20/B20), TB2± (C20/D19),
TC2± (D20/E19), TD2± (F20/G19), TE2± (G20/H19), TCLK2± (E20/F19)
YES
NO Check IC3301 and its peripheral control circuits. (IC2002 (UCON), IC8101 (DECODER), IC3501 (SRAM), IC3502 (SRAM), etc.)
Is the above-mentioned LVDS signal output to connector (P2601)?
NO Check the line between IC3301 and P2601.
YES Is LCD controller's control signal normal? NO Check control signal line.
(R/L, U/D, TEMP1/2/3, DET_PNL12V, ROMSEL0/1)
LCD_CONT_UNIT: YES Similarly, is the LVDS signal input to the connector (CN4804) of LCD_CONT_UNIT?
NO Check wire harness (LW).
YES
Check the LCD_CONT_UNIT.
No picture on the display (2)
The picture doesn’t come out when VHF/UHF is received.
TERMINAL UNIT: Is IF signal output from pin (17) of TUNER (TU7501)? NO Check whether I2C signal is normally accessed between TU7501
and IC7507 (COFDM).
YES
Is IF signal input to pin (1) and (2) of IC7504 (IF-DEMO)? NO Check the FL7502 (VIF_SAW) and their peripheral circuits.
YES Is video signal (TUNER_CVBS) input from pin (17) of IC7504 to pin (9) of IC506 (VIDEO_SELECTOR)?
NO Check the line between IC7504 and IC506.
(Q7505, IC7508, etc.)
YES Is CVBS signal (MAIN_Y/V) output from pin (52) of IC506 to pin
(2) of connector SC501?
NO Check the line between IC506 and SC501.
MAIN UNIT: YES Is CVBS signal (MAIN_Y/V) input to pin (2) of connector SC1101?
NO Check the connector SC501/SC1101.
YES Is CVBS signal (MAIN_Y/V) input to pin (Y4) of IC3301 (VIDEO_PROCESSOR)?
NO Check the line between SC1101 and IC3301.
YES Refer to “The picture doesn't appear in all modes.”
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No picture on the display (3)
The picture doesn’t come out when DTV is received.
TERMINAL UNIT: Is the regulated power supplied to TUNER (5V/5VCONT) and IC7507 (B3.3V/B1.8V)?
NO Each power supply circuit is checked.
YES Is IF signal output from pins (20, 21) of TUNER (TU7501) to pins
(30, 31) of IC7507 (COFDM)?
NO Check the tuner, IC7507 and their peripheral circuits.
Replace as required.
TERMINAL UNIT: YES Does serial control signal (SDA/SCL) operate with pins (15, 14) of TUNER and pins (5, 4) of IC7507?
NO
YES Does X7502 (20.48MHz) of IC7507 oscillate? NO Check X7502 and its peripheral circuits.
YES Is MPEG data (FECLK/FED_D/FESTR_PSYNC/FEVAL_DEN) from IC7507 output to pins (1, 3) of connector (P7501) and pins (51, 50) of connector (SC501)?
NO Is the control signal named IC7507 and IC9101 (CPLD) normal?
(FE_RST_LINE, FEERR_LINE, FEPG0_COMP_LINE, FEPG1_LOCK_LINE, etc.)
MAIN UNIT: YES Is the digital signal (FECLK/FED_D/FESTR_PSYNC/
FEVAL_DEN) sent to pins (1, 3) of connector (P1103) and pins (51, 50) of connector (SC1101)?
NO Check connector (SC501/SC1101 and P7501/P1103).
YES Is the digital signal (FECLK/FED_D/FESTR_PSYNC/ FEVAL_DEN) input to pins (AF3, AF2, AF4, AH3) of IC8101
(CPU/DECODER)?
NO Check the line between SC1101,P1103 and IC8101.
YES Does X8101 (24.00MHz)/X8102 (32.768kMHz) of IC8101 oscil­late?
NO Check the X8101/ X8102 and their peripheral circuits.
YES Are video signal (VDB_R [0:9], VDB_G [0:9], VDB_B [0:9], and VBD_CLK/DE/HD/VD) are output from IC8101 to IC3301 (VIDEO
PROCESSOR)?
NO Check IC8101, IC3301 and their peripheral circuits.
(IC8301-IC8304 (DDR2_SDRAM), etc.)
YES Refer to “The picture doesn't appear in all modes.”
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<External input EXT1, EXT2> No picture on the display (4)
The CVBS video signal input from EXT1 doesn’t come out in the display. The CVBS video signal input from EXT2 doesn’t come out in the display.
TERMINAL UNIT: <EXT1> Is CVBS signal sent to pin (20) of SCART1 (SC502)?
NO Check the setting of an external input device that connects of
SC502.
<EXT2> Is CVBS signal sent to pin (20) of SCART2 (SC503)?
NO Check the setting of an external input device that connects of
SC503.
YES <EXT1> Is CVBS signal sent to pin (65) of IC506?
NO Check the line between SCART1 (SC502) and IC506.
<EXT2> Is CVBS signal sent to pin (71) of IC506?
NO Check the line between SCART2 (SC503) and IC506.
YES Is CVBS signal (MAIN_Y/V) output from pin (52) of IC506 to pin
(2) of connector (SC501)?
NO Check the line between IC506 and SC501.
MAIN UNIT: YES Is CVBS signal (MAIN_Y/V) input to pin (2) of connector SC1101?
NO Check the connector SC501/SC1101.
YES Is CVBS signal (MAIN_Y/V) input to pins (Y4) of IC3301 (VIDEO_PROCESSOR)?
NO Check the line between SC1101 and IC3301.
YES Refer to “The picture doesn't appear in all modes.”
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<External input EXT1, EXT2> No picture on the display (5)
The R/G/B video signal input from EXT1 doesn’t come out in the display. The R/G/B video signal input from EXT2 doesn’t come out in the display.
TERMINAL UNIT: <EXT1> Is RGB signal (R1/G1/B1) sent to pins (15, 11, 7) of SCART1 (SC502)?
NO Check the setting of an external input device that connects of
SC502.
<EXT2> Is RGB signal (R2/G2/B2) sent to pins (15, 11, 7) of SCART2 (SC503)?
NO Check the setting of an external input device that connects of
SC503.
YES <EXT1> Is RGB signal (R1/G1/B1) sent to pins (25, 21, 23) of IC506 (V_SELECTOR)?
NO Check the line between SC502 and IC506.
<EXT2> Is RGB signal (R2/G2/B2) sent to pins (31, 27, 29) of IC506 (V_SELECTOR)?
NO Check the line between SC503 and IC506.
YES Is RGB signal output from pin (54, 56, 55) of IC506 to pins (12, 14, 16) of connector (SC501)?
NO Check the line between IC506 and SC501.
MAIN UNIT: YES Is RGB signal sent to pins (12, 14, 16) of connector (SC1101)? NO Check the connector (SC501/SC1101)
YES Is RGB signal sent to pins (Y8, V6, W9) of IC3301 (VIDEO_PROCESSOR)?
NO Check the line between SC1101 and IC3301.
(Q1104, Q1105, Q1106, etc.)
YES Refer to “The picture doesn't appear in all modes.”
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<External input EXT1, EXT2> No picture on the display (6)
The Y/C video signal input from EXT1 doesn’t come out in the display. The Y/C video signal input from EXT2 doesn’t come out in the display.
TERMINAL UNIT: <EXT1> Is Y/C video signal sent to pins (20, 15) of SCART1 (SC502)?
NO Check the setting of an external input device that connects of
SC502.
<EXT2> Is Y/C video signal sent to pins (20, 15) of SCART2 (SC503)?
NO Check the setting of an external input device that connects of
SC503.
YES <EXT1> Is Y/C signal sent to pins (67, 69) of IC506?
NO Check the line between SC502 and IC506.
<EXT2> Is Y/C signal sent to pins (73, 75) of IC506?
NO Check the line between SC503 and IC506.
YES Is Y/C signal output from pins (52, 50) of IC506 to pins (2, 4) of
connector (SC501)?
NO Check the line between IC506 and SC501.
MAIN UNIT: YES Is Y/C signal sent to pins (2, 4) of connector (SC1101)? NO Check the connector (SC501/SC1101)
YES Is Y/C signal sent to pins (Y4, V9) of IC3301 (VIDEO_PROCESSOR)?
NO Check the line between SC1101 and IC3301.
YES Refer to “The picture doesn't appear in all modes.”
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<When EXT3 is used for external input> No picture on the display (7)
The picture video signal (CVBS) input from EXT3 doesn’t come out in the display.
MINI AV UNIT: Is the CVBS signal input from pin (6) of EXT3 terminal (J901) to pin (5) of connector (P901)?
NO Check the line between J901 and P901.
TERMINAL UNIT: YES Is the CVBS signal input from pin (5) of connector (P501) to pin
(3) of IC506 (VIDEO SELECTOR)?
NO Check the line between P501 and IC506.
(Connector P901/P501, etc.)
YES Is the V3_PLUG signal (pin (7)) for connection detection of EXT3 terminal (J901) normal? (When connecting terminal: 7V, When opening: 0V)
NO Check J901, pin (2) of IC506 or peripheral circuits.
YES Is video signal (MAIN_Y/V) output from pin (52) of IC506 to pin (2) of connector (SC501)?
NO Check the line between IC506 and SC501.
MAIN UNIT: YES Is video signal (MAIN_Y/V) input to pin (2) of connector SC1101? NO Check the connector (SC501/SC1101)
YES Is video signal (MAIN_Y/V) input to pin (Y4) of IC3301
(VIDEO_PROCESSOR)?
NO Check the line between SC1101 and IC3301.
YES Refer to “The picture doesn't appear in all modes.”
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<When EXT3 is used for external input> No picture on the display (8)
The Y/C video signal input from EXT3 doesn’t come out in the display
MINI AV_UNIT: Is Y/C signal output from pins (3, 4) of J902 (Y/C TERMINAL) to pins (13, 11) of connector (P901)?
NO Check the line between J901 and P901.
TERMINAL UNIT: YES Is Y/C signal output from pins (13, 11) of connector (P501) to
pins (5, 7) of IC506 (VIDEO SELECTOR)?
NO Check the line between P501 and IC506.
(Connector P901/P501, etc.)
YES Is the S3_PLUG signal (pin (6)) for connection detection of Y/C terminal (J902) normal? (When connecting terminal: 7V, When opening: 0V)
NO Check J902, pin (42) of IC506 or peripheral circuits.
YES Is Y/C signal output from pins (52, 50) of IC506 to pins (2, 4) of connector (SC501)?
NO Check the line between IC506 and SC501.
MAIN UNIT: YES Is Y/C signal input to pin (2, 4) of connector SC1101? NO Check the connector (SC501/SC1101)
YES Is Y/C signal input to pin (Y4, V9) of IC3301
(VIDEO_PROCESSOR)?
NO Check the line between SC1101 and IC3301.
YES Refer to “The picture doesn’t appear in all modes.”
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<When EXT4 is used for external input> No picture on the display (9)
The HDMI signal input from EXT4 doesn’t come out in the display.
MINI AV_UNIT: Is the HOT_PLUG detection signal input to pin (19) of the HDMI terminal (SC801) normal?
Is the HOT_PLUG output signal input from pin (18) of HDMI ter­minal (SC801) to pin (51) of IC803?
NO Check the between pin (25) of IC803 (HDMI_BUFFER) and pin
(19) of SC801. (IC807, etc.)
YES
Check the connection and setup with the external HDMI devices.
Is EDID data accessed from pins (5, 6) of IC802 (EEPROM), and is it read from pin (15, 16) of a HDMI terminal (SC801)?
NO Is access possible in the re-writing or exchange of EDID data of
IC802?
YES
NO
Check SC801, IC802, IC803 and peripheral circuits.
Is TMDS signal (RXC± - RX2±) input from EXT4 terminal (SC801) to the pins (28/27-35/34) of IC803 (HDMI)?
NO Check the line between SC801 and IC803.
YES Is TMDS signal (TXC± - TX2±) input from the pins (9-1) of IC803 (HDMI) to pins (12-2) of connector (SC802)?
NO Check the line between IC803 and SC802.
YES Is TMDS signal (TMDS6_D0-D2) input into pins (61-68) of
IC1507 (HDMI_SW)?
NO Check the line between connector (SC802) and IC1507.
(SC802, SC1503 and Wire harness (HM))
YES Is switched TMDS signal (TMDS_D0± - D2±) output from pins (11-1) of IC1507?
NO Is the control signal of IC1507 and IC9101 (CPLD) normal?
(HDMI_SW_INT, HDMI_RST, etc.)
YES Is switched TMDS signal (TMDS_D0± - D2±) input to pins (L2-P1) of IC3301 (VIDEO_PROCESSOR)?
YES NO Refer to “The picture doesn't appear in all modes.” Check the line between IC1507 and IC3301.
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<When EXT5/6 is used for external input> No picture on the display (10)
The HDMI signal input from EXT5/6 doesn’t come out in the display.
MAIN UNIT: EXT5 Is the HOT_PLUG detection signal input to pin (19) of the HDMI
terminal (SC1501) normal?
NO EXT5
Check between pin (19) of SC1501 and pin (16) of IC1507 (HDMI_SW). (IC1506, etc.)
EXT6 Is the HOT_PLUG detection signal input to pin (19) of the HDMI terminal (SC1502) normal?
NO EXT6
Check between pin (19) of SC1502 and pin (36) of IC1507 (HDMI_SW). (IC1506, etc.)
YES
YES Check the connection and setup with the external HDMI devices.
EXT5 Is EDID data (SDA/SCL) of IC1501 (EEPROM) accessed, and is it read from pins (15, 16) of a HDMI terminal (SC1501)?
NO
Check short-circuit or open circuit of the I
2
C line.
EXT6 Is EDID data (SDA/SCL) of IC1502 (EEPROM) accessed, and is it read from pins (15, 16) of a HDMI terminal (SC1501)?
NO
Check short-circuit or open circuit of the I
2
C line.
YES EXT5 Is TMDS signal (RXC± - RX2±) input from SC1501 to the pins
(19/18-28/27) of IC1507?
NO Check the line between SC1501 and IC1507.
EXT6 Is TMDS signal (RXC± - RX2±) input from SC1502 to the pins (39/38-48/47) of IC1507?
NO Check the line between SC1502 and IC1507.
YES Is switched TMDS signal (TMDS_D0± - D2±) output from pins (11-1) of IC1507?
NO Is the control signal of IC1507 and IC9101 (CPLD) normal?
(HDMI_SW_INT, HDMI_RST, etc.)
YES Is switched TMDS signal (TMDS_D0± - D2±) input to pins (L2-P1) of IC3301 (VIDEO_PROCESSOR)?
YES NO Refer to “The picture doesn't appear in all modes.” Check the line between IC1507 and IC3301.
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<When EXT7 is used for external input> No picture on the display (11)
The PC (ANALOG) video signal input from EXT7 (D-SUB-15pin-terminal) doesn’t come out in the display.
MAIN_UNIT: Are the video signal (R, G, B) and the synchronized signal (H/V) input from pins (1, 2, 3) and pins (13, 14) of EXT7 terminal
(SC1504)?
YES Check the connection and setup between SC1504 and its cir-
cumference circuit as well as the external HDMI devices. (IC1503, etc.)
NO Are the video signal (R, G, B) and the synchronized signal (H/V) input from pins (U8, Y7, W10) and pins (V10, U10) of IC3301 (VIDEO PROCESSOR)?
YES Check the line between SC1504 and IC3301.
NO Refer to “The picture doesn't appear in all modes.”
<When EXT8 is used for external input> No picture on the display (12)
The component video signal input to EXT8 doesn’t come out in the display.
TERMINAL UNIT: Is COMPONENT video signal (Y, Pb, Pr) input to pins (6, 5, 4) of EXT8 terminal (J508)?
NO Check the connection of J508 and the external input device.
YES
Is COMPONENT video signal (Y, Pb, Pr) input to pins (33, 35,
37) of IC506 (VIDEO SELECTOR)?
NO Check the line between J508 and IC506.
YES
Is detection signal (COMP1_PLUG) of the COMPONENT video signal from pin (7) of EXT8 terminal (J508) normal? (When connecting terminal: 7V, When opening: 0V)
NO Check from EXT8 terminal (J508) to pin (38) of IC506.
YES Is COMPONENT video signal (Y, Pb, Pr) output from pins (60, 59, 58) of IC506 to pins (6, 8, 10) of the connector (SC501)?
NO Check the line between IC506 and SC501.
(Q516, Q518, Q520, etc.)
MAIN UNIT: YES Is COMPONENT video signal output from pins (6, 8, 10) of the connector (SC1101)?
NO Check the connector (SC501/SC1101)
YES Is COMPONENT video signal input to pins (W6, Y9, W8) of IC3301 (VIDEO_PROCESSOR)?
NO Check the line between SC1101 and IC3301.
YES Refer to “The picture doesn't appear in all modes.”
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<During external connection> No picture on the monitor (1)
No picture appears on EXT1 - connected monitor during the tuner (U/V) reception.
Checklist:
1) Is the Signal Type (item) in MENU-Option-Input Select equal to Signal Type of an external device? ⋅ ⋅ ⋅ Set it to “CVBS”, “Y/C” or “RGB”.
2) Is ANT-CABLE disconnected or connected improperly? ⋅ ⋅ ⋅ Connect it correctly as per the operation manual.
3) The picture is sent to the monitor in a CVBS signal if the source during display is TV, CVBS or Y/C of EXT1-3.
When sent by component, etc., that signal is not sent to the monitor.
4) When the monitor picture is not sent and is not displayed on the monitor, refer to “No picture” for each terminal.
5) The video output from EXT1 is not the monitor output (output of the picture now watching).
The picture of the last selected TV channel is always sent to EXT1. (Specification)
TERMINAL UNIT: Is CVBS signal output into pin (19) of SC502 (SCART1) from pin
(2) of IC1501 (SW)?
YES Check the setting of an external input device that connects of
SC502.
NO
Is TUNRE_CVBS signal input into pin (6) of IC503 (SW)? YES Check the IC501 (SW), IC503 (SW) and their peripheral circuits.
NO
Is TUNRE_CVBS signal output from pin (17) of IC7504 (IF­DEMO)?
YES Check the line between IC7504 and IC503.
(Q7505, IC7508, etc.)
NO
Is IF signal output from pin (17) of TUNRE (TU7501)? YES Check the IC7504/FL7502 (VIF_SAW) and its peripheral circuits.
NO Check whether I2C is normally accessed between TU7501 and IC7507 (COFDM).
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<During external connection> No picture on the monitor (2)
No picture appears on EXT1 - connected monitor during the tuner (DTV) reception.
Checklist:
1) Is the Signal Type (item) in MENU-Option-Input Select equal to Signal Type of an external device? ⋅ ⋅ ⋅ Set it to “CVBS”, “Y/C” or “RGB”.
2) Is ANT-CABLE disconnected or connected improperly? ⋅ ⋅ ⋅ Connect it correctly as per the operation manual.
3) The picture is sent to the monitor in a CVBS signal if the source during display is TV, CVBS or Y/C of EXT1-3.
When sent by component, etc., that signal is not sent to the monitor.
4) When the monitor picture is not sent and is not displayed on the monitor, refer to “No picture” for each terminal.
5) The video output from EXT1 is not the monitor output (output of the picture now watching).
The picture of the last selected TV channel is always sent to EXT1. (Specification)
TERMINAL UNIT: Is CVBS signal outputted from pin (2) of IC1501 (SW) to pin (19)
of SC502 (SCART1)?
YES Check the setting of an external input device that connects of
SC502.
NO Is DTV_CVBS signal sent to pin (4) of IC503 (SW)? YES Check the IC501 (SW), IC503 (SW) and their peripheral circuits.
MAIN UNIT: NO Is DTV_CVBS signal output to pin (18) of connector (SC1101)? YES Check the line between SC1101 (MAIN_UNIT)/ SC501 (TERMI-
NAL UNIT) and IC503.
NO Is DTM_CVBS signal output from pin (AD4) of IC8101? YES Check the line between IC8101 and SC1101.
NO Is digital signal (DTV_SD0, DTV_SCK, DTV_WS) input to the pins (U3, U2, U1) of IC8101?
YES Check IC8101 or peripheral circuits.
NO Is digital signal (DTV_SD0, DTV_SCK, DTV_WS) output from
pins (32, 11, 10) of IC1404 (CODEC)?
YES Check connector (SC502) or connector (P7501).
NO Check IC1404, IC7507 or TU7501. (+B line, I
2
C line or peripheral circuit)
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<During external connection> No picture on the monitor (3)
SCART2: No picture from EXT1 appears on EXT2-connected monitor.
NOTE: Normally, if the screen during display is sent to EXT2, no picture is sent to EXT2.
Checklist:
1) Is the Signal Type (item) in MENU-Option-Input Select equal to Signal Type of an external device? ⋅ ⋅ ⋅ Set it to “CVBS”, “Y/C” or “RGB”.
2) The picture is sent to the monitor in a CVBS signal if the source during display is TV, CVBS or Y/C of EXT1-3.
When sent by component, etc., that signal is not sent to the monitor.
3) When the monitor picture is not sent and is not displayed on the monitor, refer to “No picture” for each terminal.
4) The video output from EXT1 is not the monitor output (output of the picture now watching).
The picture of the last selected TV channel is always sent to EXT1. (Specification)
TERMINAL UNIT: Is CVBS signal output from pin (51) of IC506 to pin (19) of SCART2 (SC503)?
YES Check the setting of an external input device that connects of
SC503.
NO Is CVBS signal (VIN1) sent to pin (65) of IC506 (VIDEO_SELECTOR)?
YES Check the IC506 and its peripheral circuits.
NO Is CVBS signal (VIN1) sent to pin (20) of SCART1 (SC502)? YES Check the line between SC502 and IC506.
NO Check the setting of an external input device that connects of SC502.
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<During external connection> No picture on the monitor (4)
SCART2: No picture from EXT3 appears on EXT2- connected monitor.
Checklist:
1) Is the Signal Type (item) in MENU-Option-Input Select equal to Signal Type of an external device? ⋅ ⋅ ⋅ Set it to “CVBS”, “Y/C” or “RGB”.
2) The picture is sent to the monitor in a CVBS signal if the source during display is TV, CVBS or Y/C of EXT1-3.
When sent by component, etc., that signal is not sent to the monitor.
3) When the monitor picture is not sent and is not displayed on the monitor, refer to “No picture” for each terminal.
4) The video output from EXT1 is not the monitor output (output of the picture now watching).
The picture of the last selected TV channel is always sent to EXT1. (Specification)
TERMINAL UNIT: Is CVBS signal output from pin (51) of IC506 to pin (19) of SCART2 (SC503)?
YES Check the setting of an external input device that connects of
SC503.
NO Is CVBS signal input from pin (5) of the connector P501 to pin (3)
of IC506 (VIDEO SELECTOR)?
YES Check the IC506 and its peripheral circuits.
MINI AV UNIT: NO Is CVBS signal input from pin (6) of the EXT3 terminal (J901) to pin (5) of the connector (P501)?
YES Check the connector (P501/P901)
NO Is V3_PLUG signal of the CVBS signal detection function from
pin (7) of the EXT3 terminal (J901) normal? (When connecting terminal: 7V, When opening: 0V)
YES Check the setting of an external input device that connects of
J901.
NO Check between V3_PLUG_LINE J901 and pin (2) of IC506 in the TERMINAL UNIT. (Connector P901/P501, etc.)
LED flashing patterns for error notification
1) Power red LED Remarks
Error type Power red LED operation (1 cycle) Description
Lamp failure Flashes once: Fast
H: On
L: Off
ERR_PNL (IC2002_43pin): Abnormal L. Confirmed after 5 consecutive detections at 1 second intervals (detected only when the backlight is on). Note that after five detection counts, the lamp cannot be acti­vated except in the monitoring process. (For the first time, only the inverter is reset, and error OFF is not activated) Accumulated counts are cleared to 0 when the correspond­ing setting in the process A is made, when the power is turned on with [CH_DOWN] and [VOL_UP] on the unit down
or after continuous illumination for 3 minutes. Power failure Flashes twice
H: On
L: Off
Refer to “Power failure details”.
Communication failure with main CPU Flashes 3 times
H: On
L: Off
Refer to “Communication failure details”.
Communication line failure or main CPU (IC8101) communi-
cation
failure. → Check main CPU (IC8101). Monitor temp. failure
Flashes 5 times
H: On
L: Off
If the panel temperature is 60°C or more for 15 seconds or
more in a row, CAUTION appears on the OSD of AVC
(flashes in red in the lower right screen).
If the panel temperature is 60°C or more for 28 seconds or
more in a row, error standby is activated.
(MONITOR MAX TEMP of process adjustment (28/31):
Change of temperature failure AD value): Thermistor
250ms 1sec
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2) Power failure details (Power LED flashes twice and OPC LED flashes) Remarks
Error type OPC LED operation (1 cycle) Description
PS_ON 12V failure Flashes once
H: On
L: Off
AC_DET (IC2002_16pin): Abnormal (L). Main converter 12V
is not applied.
If error is detected during operation, the power is turned on
again by interrupt handling (instantaneous blackout process-
ing, no error flashing). PS_ON
10V failure Flashes 3 times
H: On
L: Off
DET_10V (IC2002_57pin): Abnormal (L). Main power
UR15V is not applied.
If error is detected during start-up or operation, the power is
turned on again by polling. D_POW
Digital 3.3V failure Flashes 4 times
H: On
L: Off
DET_D3V3 (IC2002_59pin): Abnormal (L). D3.3V is not
applied.
If error is detected during start-up or operation, the power is
turned on again by polling. PANEL_POW
Panel 5V failure Flashes 5 times
H: On
L: Off
DET_PNL5V (IC2002_58pin): Abnormal (L). Panel power is
not applied.
If error is detected during start-up or operation, the power is
turned on again by polling. Main failure
Flashes 7 times
H: On
L: Off
Main microprocessor detection error
The details are displayed on page 1 of process adjustment
for the main microprocessor (IC8101).
3) Communication failure details (Power LED flashes 3 times and OPC LED flashes) Remarks
Error type OPC LED operation (1 cycle) Description
Initial communication reception failure Flashes once
H: On
L: Off
Initial communication from the main CPU (IC8101) is not
received.
Communication line failure or main CPU (IC8101) start-up
failure Start-up confirmation reception failure
Flashes twice
H: On
L: Off
Start-up reason confirmation from the main CPU (IC8101) is
not received.
Main CPU (IC8101) start-up failure or monitor micropro-
cessor (IC2002) reception failure Regular communication failure Flashes 3 times
H: On
L: Off
Regular communication that is performed at 1 second inter-
vals in the normal operation is interrupted.
Main CPU (IC8101) operation failure or monitor micropro-
cessor (IC2002) reception failure Restart failure
Flashes 4 times
H: On
L: Off
When restarted by a software with the standby off/on, restart
completion notification is not received.
Main CPU (IC8101)restart failure to monitor microproces-
sor (IC2002) reception failure
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LC46X8E
Service Manual
CHAPTER 5. MAJOR IC INFORMATIONS
[1] MAJOR IC INFORMATIONS
1. Detailed ICs Information
1.1. IC402 (VHiBD9305AF-1Y)
1.1.1 Block Diagram
1.1.2 Pin Connections and short description
Pin No. Pin Name I/O Pin Function
1 RT Timing Resistor external terminal. 2 CT Timing Capacitor external terminal. 3 ENB I Control terminal. 4 GD O Gate drive output terminal. 5 VCC Power supply terminal. 6 GND Ground. 7 COMP O Error amplifier output terminal. 8 FB I Error amplifier inverting input terminal.
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1.2. IC506 (VHiMM3151XQ-1Q)
1.2.1 Block Diagram
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1.2.2 Pin Connections and short description
Pin No. Pin Name I/O Pin Function
69 C1 I
Chroma signal input
75 C2 I 1C3 I 7C4 I 70 S1 I
The terminal which detects the connection state of S-connector.76 S2 I 2S3 I 65 V1 I
Composite signal input.
71 V2 I 77 V3 I 3V4 I 9V5 I 15 V6 I 68 S2-1 I
The terminal which detects the aspect ratio information of S-connector. 74 S2-2 I
80 S2-3/ FS3 I
The terminal which detects the aspect ratio information of S-connector, or which detects the
voltage of FS pin of a scart connector. 67 Y1 I
Luminance signal input.
73 Y2 I 79 Y3 I 5Y4 I 14 ADR I Slave address select pin. 16 BIAS I BIAS 32 L13 I The terminal which detects the number of scanning lines information on D-connector. 20 L11/ FS1 I
The terminal which detects the number of scanning lines information on D-connector, or
which detects the voltage of FS pin of a scart connector.
26 L12/ FS2 I 21 CY1 I
Component Y-signal input.27 CY2 I 33 CY3 I 22 L21 I
The terminal which detects the I/P information of D-connector.28 L22 I 34 L23 I 24 L31 I
The terminal which detects the aspect ratio information of D-connector.30 L32 I 36 L33 I 23 PB1 I
Colour difference PB-signal input.29 PB2 I 35 PB3 I 25 PR1 I
Colour difference PR-signal input.31 PR2 I 37 PR3 I 38 SW1 I
The terminal which detects the connection state of D-connector.40 SW2 I 42 SW3 I 45 SDA I/O Data I/O of I2C bus 46 SCL I Clock input of I2C bus 49 DCOUT O DC output for S-terminal. 51 VOUT3 O Monitor output (composite signal) 50 COUT3/ VOUT6 O Monitor output (Chroma or composite signal) 52 YOUT3/ VOUT5 O Monitor output (Luminance or composite signal) 54 PROUT2 O
Colour difference PR-signal output. 58 PROUT1 O
55 PBOUT2/COUT2 O
Colour difference PB-signal or chroma signal output. 59 PBOUT1/ COUT1 O
56 CYOUT2/ YOUT2/ VOUT2 O
Colour difference signal, Luminance signal or composite signal output. 60 CYOUT1/ YOUT1/ VOUT1 O
64 O1 O
Output port.
66 O2 O 72 O3 O 78 O4 O 53, 57 VDD1 Power supply (+9V) 8, 47 VDD2 Power supply (+5V) 18, 44, 62 GND Ground
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1.3. IC1402 (VHiR2S15502-1Y)
1.3.1 Block Diagram
1.3.2 Pin Connections and short description
4, 6, 10, 11, 12, 13, 17, 19, 39, 41, 43, 48, 61, 63
NC Unconnected pins.
Pin No. Pin Name I/O Pin Function
1 AVSS 0V Power Supply for Analog Core 2 AVDD 3.3V Power Supply for Analog Core 3 SIF I Sound IF Input 4 VREF1 ADC Voltage Reference 1 5 VREF2 ADC Voltage Reference 2 6 TEST I Test pin 7 XI I Crystal Oscillator Input 8 XO O Crystal Oscillator Output 9 IVDD 3.3V Power Supply for I/O Buffer 10 IVSS 0V Power Supply for I/O Buffer 11 DVSS 0V Power Supply for Logic Core 12 DVDD 1.5V Power Supply for Logic Core 13 DACCLK I/O DAC Clock 14 BCK I/O Bit Clock 15 LRCK I/O LR Clock 16 SD0 O Digital Output for External DAC 17 SDI I Digital Input for Internal DAC 18 SDA I/O I2C bus Serial Data 19 SCL I I2C bus Serial Clock 20 STATUS I/O PLL Setting / Status Signal 21 RESET I Hardware Reset (Active low) 22 ROUT O Rch Analog Output 23 VCOM DAC Voltage Reference 24 LOUT O Lch Analog Output
Pin No. Pin Name I/O Pin Function
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1.4. IC3301 (RH-iXC010WJQZQ)
1.4.1 Block Diagram
1.4.2 Pin Connections and short description
Pin No. Pin Name I/O Pin Function Sheet Name Destination
Ball Assignments for CPU Host Interface.
K20, K19, K18, K17, L20, L19, L18, L17
A_D[7:0] I/O Multiplexed address and data bus powered by VDDH/VSS. ADAT_O-7 CPU
M17, M18, M19, M20, N20, N19, N18, N17
ADDR[7:0] I CPU Address. (not connected) TP3301-8 CPU
J18 ALE I Address latch enables. 8051_ALE CPU J19 WR# I CPU Write. 8051_WR CPU J20 RD# I CPU Read. 8051_RD CPU H17 SDA I/O I2C data. R-+3.3V H18 SCL I I2C clock. R-+3.3V J17 CPU_CS I UX chip select pin from MCU. Active Low. 8051_CS CPU
Ball Assignments for Analog Support Interface.
W1 XTALI I Input for Clock Synthesizer. Supports 24MHz Oscillator or
crystal powered by analog PLL.
XTAL X-TAL,27M
Y1 XTALO O Used in conjunction with XTALI for 24MHz crystal output
powered by analog PLL.
XTAL X-TAL,27M
U2 MLF1 I Low pass filter node for memory clock PLL powered by
analog PLL.
CR_+B
R4 PLF2 I Low pass filter node for video clock PLL powered by analog
PLL.
+3.3V
Ball Assignments for Analog Input Interface.
Y4 CVBS1 I Composite video input 1. MAIN_Y/V_TR FROM-V-SW V6 Y_G1 I Y input 1 of component or G input 1 of PC RGB. SCART_G_TR FROM-V-SW
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W6 Y_G2 I Y input 2 of component or G input 2 of PC RGB. COMP_Y_TR FROM-V-SW Y6 Y_G3 I Y input 3 of component or G input 3 of PC RGB. DTM_Y open W2 CVBS_OUT1 I CVBS Output 1. (not connected) open V2 CVBS_OUT2 I CVBS Output 2. (not connected) open V9 C I C input of S-Video. MAIN_C_TR FROM-V-SW W9 PB_B1 I PB input 1 of component. SCART_B_TR FROM-V-SW Y9 PB_B2 I PB input 2 of component. COMP_Pb_TR FROM-V-SW Y10 PB_B3 I PB input 3 of component. DTM_Pb open Y8 PR_R1 I PR input 1 of component. SCART_R_TR FROM-V-SW W8 PR_R2 I PR input 2 of component. COMP_Pr_TR FROM-V-SW V8 PR_R3 I PR input 3 of component. DTM_PR open W4, V4 FS2, FS1 I SCART function select 2, 1. W4 R-GND U4, Y5 FB2, FB1 I SCART FB input for Port 2, Port 1. V4 R-GND V10 AIN_H I Hsync input (PC RGB input) PC-H FROM EXT7 U10 AIN_V I Vsync input (PC RGB input) PC-V FROM EXT7 U8 PC_R I PC Red input. PC_R FROM EXT7 Y7 PC_G I PC Green input. PC_G FROM EXT7 W10 PC_B I PC Blue INPUT. PC_B FROM EXT7
Ball Assignments for Capture Interface (TV & RGB).
U18, U19, U20, T20, T18, T17, R19, R20
DPB[15:8] (DP_B[15:8])
I/O Digital input port[15:8] (Output reserved) AD_RA0-8
AD_GA0-8 AD_BA0-8
TO CPU
Y12, U13, V13, W13, Y13, Y14, W14, V14, U14, U15, V15, W15, Y16, W16, V16, U16, U17, V17, W17, Y17, Y18, W18, V18, W19
DPA[23:0] (DP_A[23:0])
I/O Digital input/output port [23:0] AD_RA0-8
AD_GA0-8 AD_BA0-8
TO CPU
T19 DPB_CLK (CLK_B) I/O Digital port B CLK input/output. (no connected) open Y15 DPA_CLK (CLK_A) I/O Digital port A CLK input/output. AD_CLK TO CPU W20 DPE_DE (DE_B) I/O DE input/output of Digital port B. AD_DE TO CPU Y20 DPA_VS (VS_A) I/O Vsync input/output of Digital port A. AD_VD TO CPU Y19 DPA_HS (HS_A) I/O Hsync input/output of Digital port A. AD_HD TO CPU V20 DPB_VS (VS_B) I/O Vsync input/output of Digital port B. (no connected) open V19 DPB_HS (HS_B) I/O Hsync input/output of Digital port B. (no connected) open P19 HS I/O Hsync output for Digital port. R-+B P17 VS I/O Vsync output for Digital port. R-+B
Ball Assignments for Frame Buffer Memory.
D3, C3, C2, C1, A1, A2, A3, C5, A4, B5, A5, D6, A7, B7, C7, D7, D8, C8, B8, A8, D9, D10, C10, B10, A10, A11, B11, C11, D12, A13, B13, C13
MD[31:0] I/O Memory data. WX_MD31-0 TO SDRAM
F1, F2, F3, F4, G4, G3, G2, G1, H1, H2, H3, H4
MA[11-0] I/O Memory Address. WX_MA11-0 TO SDRAM
J2 RAS# O RAS# signal powered by VDDH/VSS. WX_RAS TO SDRAM J1 CAS# O CAS# signal powered by VDDH/VSS. WX_CAS TO SDRAM K1 WE# O WE#, write enable signal powered by VDDH/VSS. WX_WE TO SDRAM J3 CS1# O Chip select 0 for the first 2/4 Mbyte of SGRAM/SDRAM
powered by VDDH/VSS.
WX_CS1 TO SDRAM
J4 CS0# O Chip select 1 for the second 2/4 Mbyte of SGRAM/SDRAM
powered by VDDH/VSS.
WX_CS0 TO SDRAM
D1 MCK0 O Memory clock+. WX_MCLK0 TO SDRAM E1 MCK0# O Memory clock-. WX_MCLK0# TO SDRAM B1, A6, A9, A12 DQM[3:0] O Read/Write bytes enable powered by VDDH/VSS. WX_DQM3-0 TO SDRAM K2 CLKE O Memory Clock Enable. WX_CLKE TO SDRAM B2, B6, B9, B12 DQS[3:0] I/O Memory data strobe. WX_DQS3-0 TO SDRAM E3 MVREF DDR voltage reference. WX_DDR_VREF TO SDRAM K3 BA0 O Bank address select. WX_BA0 TO SDRAM
Pin No. Pin Name I/O Pin Function Sheet Name Destination
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K4 BA1 O Bank address select. WX_BA1 TO SDRAM
Ball Assignments for Power and Ground.
C14, C15, D13, D14, D15, E13, E14, E15, G16, H5, H16, J5, J16, K5, K16, R16, T14, T15
VDDC 1.2V Digital core power. D1.2V
E4, E7 VSSR Digital memory reference Ground. GND E2, E8 VDDR 2.5V Digital power for Memory. 2.5V B4, C4, D4, D5,
D11, E5, E6, E9, E10, E11, E12, F5, G5
VDDM 2.5V Memory interface power. Output driver. 2.5V
L16, M16, N16, P16, T12, T13, R17, R18
VDDH 3.3V Digital I/O power. D3.3V
B3, C6, C9, C12, D2, H8, H9, H10, H11, H12, H13, J8, J9, J10, J11, J12, J13, K8, K9, K10, K11,K12, K13, L5, L8, L9, L10, L11, L12, L13, M8, M9, M10, M11, M12, M13, N8, N9, N10, N11, N12, N13, P18, T16, H20
VSS Core and Digital IO ground. GND
W3 AVSS_BG_ASS ADC ground. GND V3 AVDD3_BG_ASS 3.3V ADC power. R-D3.3V T3 PAVDD1 3.3V power for MCLK PLL. R-D3.3V T2 PAVSS1 — Ground for MCLK PLL. GND R3 PAVSS2 Ground for PCLK PLL. GND T4 PAVDD2 3.3V power for PCLK PLL. R-D3.3V U6, T8, U7, U5 AVDD_ADC[4, 3, 2, 1] 1.2V power for analog ADC. L-D1.2V T6, T9, T7, T5 AVSS_ADC[4, 3, 2, 1] Ground for analog ADC. GND U9, Y3 AVDD3_ADC[2, 1] 3.3V ADC power. L-D3.3V U3 AVDD3_OUTBUF 3.3V power for output buffer. R-D3.3V Y2 AVSS_OUTBUF 3.3V ground for output buffer. GND C18, C19 LVDS_VSSO LVDS out buffer ground. GND C16 LVDS_VSSD LVDS Digital ground. GND E16 LVDS_VSSA LVDS analog ground. GND E18 LVDS_VSSP LVDS PLL GND. GND D18 LVDS_VDDP LVDS PLL VDD. R-D1.2V E17 LVDS_VDDA LVDS analog VDD. R-D3.3V D16 LVDS_VDDD LVDS Digital VDD. R-D3.3V C17, D17 LVDS_VDDO LVDS out buffer VDD. R-D3.3V P20 NC — Not connected. open U1 AVDDAPLL 1.2V analog PLL power. D1.2V V1 AVSSAPLL 1.2V analog GND. GND R2 AVDDLLPLL 1.2V Line Lock PLL power. D1.2V T1 AVSSLLPLL 1.2V Line Lock PLL GND. GND
Miscellaneous Ball Assignments.
F18 RESET I System reset forces the chip to a known state. Active High. SVP_RESET TO CPLD G18 INTN I/O Interrupt signal (active low). N_CPLD_INT TO CPLD G17 PWM0 I/O PWM I/O. (no connected) open F16 V5SF I 5V reference voltage (must be connected to 5V even in
standby mode, when CPU I/O is 5V)
D5V
F17 TESTMODE I Reserved (Connected to ground). - R-GND
LVDS Output Ball Assignments.
A14 TA1P O LVDS 1st Channel Differential positive data out. TA1+ TO LCD CONT B14 TA1M O LVDS 1st Channel Differential negative data out. TA1- TO LCD CONT A15 TB1P O LVDS 1st Channel Differential positive data out. TB1+ TO LCD CONT
Pin No. Pin Name I/O Pin Function Sheet Name Destination
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B15 TB1M O LVDS 1st Channel Differential negative data out. TB1- TO LCD CONT A16 TC1P O LVDS 1st Channel Differential positive data out. TC1+ TO LCD CONT B16 TC1M O LVDS 1st Channel Differential negative data out. TC1- TO LCD CONT A18 TD1P O LVDS 1st Channel Differential positive data out. TD1+ TO LCD CONT B18 TD1M O LVDS 1st Channel Differential negative data out. TD1- TO LCD CONT A19 TE1P O LVDS 1st Channel Differential positive data out. TE1+ TO LCD CONT B19 TE1M O LVDS 1st Channel Differential negative data out. TE1- TO LCD CONT B17 TCLK1M O LVDS 1st Channel Differential positive CLK out. TCLK1- TO LCD CONT A17 TCLK1P O LVDS 1st Channel Differential negative CLK out. TCLK1+ TO LCD CONT F19 TCLK2M O LVDS 2st Channel Differential positive CLK out. TCLK2- TO LCD CONT E20 TCLK2P O LVDS 2st Channel Differential negative CLK out. TCLK2+ TO LCD CONT G20 TE2P O LVDS 2st Channel Differential positive data out. TE2+ TO LCD CONT H19 TE2M O LVDS 2st Channel Differential negative data out. TE2- TO LCD CONT P20 TD2P O LVDS 2st Channel Differential positive data out. TD2+ TO LCD CONT G19 TD2M O LVDS 2st Channel Differential negative data out. TD2- TO LCD CONT D20 TC2P O LVDS 2st Channel Differential positive data out. TC2+ TO LCD CONT E19 TC2M O LVDS 2st Channel Differential negative data out. TC2- TO LCD CONT C20 TB2P O LVDS 2st Channel Differential positive data out. TB2+ TO LCD CONT C19 TB2M O LVDS 2st Channel Differential negative data out. TB2- TO LCD CONT A20 TA2P O LVDS 2st Channel Differential positive data out. TA2+ TO LCD CONT B20 TA2M O LVDS 2st Channel Differential negative data out. TA2- TO LCD CONT
HDMI Interface Ball Assignments.
L4 PVCC TMDS PLL supply voltage. +3.3V M5 ANTSTO O Test pin. (no connected) open M4, N4, N5, P4 AVCC TMDS analog supply voltage. +3.3V L2 RXC- I TMDS differential CLK-. TMDS_CLKN FROM HDMI L1 RXC+ I TMDS differential CLK+. TMDS_CLKP FROM HDMI L3, M3, N3, P3, R1TMDS_GND TMDS GND.
M2 RX0- I HDMI Differential input pair 0- TMDS_D0N FROM HDMI M1 RX0+ I HDMI Differential input pair 0+ TMDS_D0P FROM HDMI N2 RX1- I HDMI Differential input pair 1- TMDS_D1N FROM HDMI N1 RX1+ I HDMI Differential input pair 1+ TMDS_D1P FROM HDMI P2 RX2- I HDMI Differential input pair 2- TMDS_D2N FROM HDMI P1 RX2+ I HDMI Differential input pair 2+ TMDS_D2P FROM HDMI R5 REGVCC ACR PLL Regulator supply voltage. P5 DGND ACR PLL GND. T10 PWR5V I TMDS port Transmitter Detect (5V tolerant). DDC5VOR_A FROM HDMI T11 DSCL I/O DDC I2C clock for DDC (5V tolerant). SCL_SINK U11 DSDA I/O DDC I2C data for DDC (5V tolerant). SDA_SINK U12 WS O I2S Word select output. R-+B V11 SCDT O Indicates Active video at HDMI input port. R-GND V12 SD0 O I2S serial data output. R-+B W11 AUDIOCLK I Audio master clock input reference. R-GND W12 SPDIF O S/PDIF audio output. HDMI_SPDIF TO CODEC Y11 SCK O I2S serial clock output. R-+B
Pin Assignments for Reference Voltage.
V5 VREFN1 ADC1 voltage reference-. C-GND W5 VREFP1 ADC1 voltage reference+. C-GND V7 VREFN2 ADC2 voltage reference-. C-GND W7 VREFP2 ADC2 voltage reference+. C-GND
Pin No. Pin Name I/O Pin Function Sheet Name Destination
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1.5. IC3501 (RH-iXC163WJQZQ)
1.5.1 Block Diagram
1.5.2 Pin Connections and short description
Pin No. Pin Name I/O Pin Function
62, 63 CK, CK
I The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except DQ's and DM's that are sam­pled on both edges of the DQS.
22 CKE I Activates the CK signal when high and deactivates the CK signal when low. By deactivating the
clock, CKE low indicates the Power down mode or Self refresh mode.
12 CS
ICS enables the command decoder when low and disabled the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations con­tinue.
11 R AS
I Latches row addresses on the positive going edge of the CK with RAS low. Enables row access &
precharge.
10 CAS
I Latches column addresses on the positive going edge of the CK with CAS low. Enables column
access.
53 WE
I Enables write operation and row precharge.
Latches data in starting from CAS
, WE active. 1, 28, 7, 34 DQS0-3 I/O Data input and output are synchronized with both edge of DQS. 44, 67, 50, 35 DM0-3 I Data In mask. Data In is masked by DM Latency=0 when DM is high in burst write. DM0 for DQ0 ~
DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31. 40, 78, 41, 42, 2, 46, 3, 4, 26, 65, 27, 66,
29, 68, 30, 69, 48, 5, 49, 6, 51, 8, 9, 52, 31, 32, 71, 33, 37, 38, 75, 39
DQ0-31 I/O Data inputs/Outputs are multiplexed on the same pins.
14, 56 BA0, BA1 I Selects which bank is to be active.
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1.6. IC7504 (VHiTDA9886+-1)
1.6.1 Block Diagram
15, 16, 57, 17, 18, 60, 19, 20, 21, 59, 90, 58
A0-11 I Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7.
Column address CA8 is used for auto precharge. 82, 88, 91, 92, 95, 101, 105, 106
VDD Power for the input buffers and core logic.
89, 94, 109, 115, 116, 117, 118, 124, 126, 127, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144
VSS Ground for the input buffers and core logic.
45, 47, 70, 72, 74, 76, 77, 79, 83, 84, 86, 87, 96, 97, 99, 100
VDDQ Isolated power supply for the output buffers to provide improved noise immunity.
36, 43, 81, 102, 103, 104, 107, 108, 110, 111, 112, 113, 114, 119, 120, 121, 122, 123, 125, 128
VSSQ Isolated ground for the output buffers to provide improved noise immunity.
23 VREF Reference voltage for inputs, used for SSTL interface. 93, 61 RFU1/RFU2 Reserved for Future Use. 13, 24, 25, 54, 55, 64, 73, 80, 85, 98
NC No Connection.
Pin No. Pin Name I/O Pin Function
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1.6.2 Pin Connections and short description
1.7. IC8101 (RH-iXC011WJQZQ)
1.7.1 Block Diagram
Pin No. Pin Name I/O Pin Function
1 VIF1 I VIF differential input 1 2 VIF2 I VIF differential input 2 3 OP1 O Output port 1; open-collector. 4 FMPLL I FM-PLL for loop filter. 5 DEEM O De-emphasis output for capacitor. 6 AFD I AF decoupling input for capacitor 7 DGND Digital ground. 8 AUD O Audio output. 9 TOP I Tuner AGC TakeOver Pint (TOP) for resistor adjustment. 10 SDA I/O I2C-bus data input and output. 11 SCL I I2C-bus clock input. 12 SIOMAD O Sound intercarrier output and MAD select with resistor. 13 N.C. Not connected. 14 TAGC O Tuner AGC output. 15 REF I 4 MHz crystal or reference signal input. 16 VAGC(1) I VIF-AGC for capacitor. 17 CVBS O Composite video output. 18 AGND Analog ground. 19 VPLL I VIF-PLL for loop filter. 20 VP Supply voltage. 21 AFC O AFC output. 22 OP2 O Output port 2; open-collector. 23 SIF1 I SIF differential input 1 and MAD select with resistor. 24 SIF2 I SIF differential input 2 and MAD select with resistor.
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1.7.2 Pin Connections and short description
Pin No. Pin Name I/O Pin Function Sheet Name
DAC Interface
AD2 VDDZ_DAC Digital power for DAC (+3.3V). D3.3V AD3 VSSZ_DAC Digital ground for DAC. GND AD1 DAC_VS I/O DAC vsync. open AE1 DAC_HS I/O DAC hsync. open AE2 DAC_CLK I/O DAC clock open AE4 DAC_DE I/O DAC DE open AE3 DAC_FLD I/O DAC field. open AA5 AVSS51 Analog ground for DAC (for bias circuit). GND AB5 COMP Bias for DAC coupling capacitor. C-D3.3V AB4 IRSET I Bias for DAC current source. R-GND AB3 CVBS_B I DAC blue or PB (no connected). TL8105 AB2 ADVSS2 Analog ground for DAC (for DAC's AVSS52). GND AB1 ADVDD2 Analog power for DAC (+3.3V). D3.3V AC1 C_G I DAC green or Y (no connected). TL8106 AC2 AVSS50 Analog ground for DAC. GND AC3 AVDD50 Analog power for DAC (+3.3V). D3.3V AC4 Y_R I DAC red or PR (no connected). TL8109 AC5 ADVSS2 Analog ground for DAC (for DAC's AVSS52). GND AD5 ADVDD2 Analog power for DAC (+3.3V). D3.3V AD4 VM I DAC VM DTM_CVBS
ADC Interface
N2 AVDD ADC power +3.3V. D3.3V N3 VIN1 I VRADC INPUT1 (no connected) R-GND N4 VIN2 I VRADC INPUT2 (no connected) R-GND N5 AVSS ADC ground. GND
USB Interface
R3 USB_PPON_PP O USB Power on control. USB_PWRON R2 USB_OC_PP I USB over current control. USB_PWRFLT P5 VDDA Analog core +3.3V supply. D3.3V P4 DN O Negative output channel. USB_DN P3 DP O Positive output channel USB_DP P2 VSSA Analog core ground. GND P1 RREFEXT External resistor connection for current reference. R-GND R5 VSSP PLL ground pin Double Bond. GND R4 VDDP PLL +1.2V supply Double Bond. C-GND
LVDS Interface
AJ5 LVDS_VSSP LVDS PLL Ground. GND AJ3 LVDS_VDDP LVDS PLL Power supply (+3.3V). D3.3V AK5 LVDS_VSSO LVDS Output buffer VSS (Long pad) GND AK4 LVDS_VDDO LVDS Output buffer VDD (+3.3V). D3.3V AK1 TF2P O LVDS Positive Output. (no connected) open AK2 TF2M O LVDS Negative Output. (no connected) open AL1 TE2P O LVDS Positive Output. (no connected) open AL2 TE2M O LVDS Negative Output. (no connected) open AM1 TD2P O LVDS Positive Output. (no connected) open AM2 TD2M O LVDS Negative Output. (no connected) open AN1 TCLK2P O LVDS Positive clock Output. (no connected) open AN2 TCLK2M O LVDS Negative clock Output. (no connected) open AP1 TC2P O LVDS Positive Output. (no connected) open AP2 TC2M O LVDS Negative Output. (no connected) open AM4 LVDS_VDDO LVDS Output buffer VDD (+3.3V). D3.3V AP3 TB2P O LVDS Positive Output. (no connected) open AN3 TB2M O LVDS Negative Output. (no connected) open AP4 TA2P O LVDS Positive Output. (no connected) open AN4 TA2M O LVDS Negative Output. (no connected) open AJ6 LVDS_VSSO LVDS Output buffer VSS. GND AP5 TF1P O LVDS Positive Output. (no connected) open AN5 TF1M O LVDS Negative Output. (no connected) open AP6 TE1P O LVDS Positive Output. (no connected) open AN6 TE1M O LVDS Negative Output. (no connected) open AP7 TD1P O LVDS Positive Output. (no connected) open AN7 TD1M O LVDS Negative Output. (no connected) open
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AP8 TCLK1P O LVDS Positive clock Output. (no connected) open AN8 TCLK1M O LVDS Negative clock Output. (no connected) open AP9 TC1P O LVDS Positive Output. (no connected) open AN9 TC1M O LVDS Negative Output. (no connected) open AJ4 LVDS_VDDO LVDS Output buffer VDD (+3.3V). D3.3V AP10 TB1P O LVDS Positive Output. (no connected) open AN10 TB1M O LVDS Negative Output. (no connected) open AP11 TA1P O LVDS Positive Output. (no connected) open AN11 TA1M O LVDS Negative Output. (no connected) open AL5 LVDS_VSSO LVDS Output buffer VSS. GND AM5 LVDS_VDDO LVDS Output buffer VDD (+3.3V). D3.3V AL3 LVDS_VSSA LVDS Analog VSS. GND AL4 LVDS_VDDA LVDS Analog VDD (+3.3V). D3.3V AK3 LVDS_VSSD LVDS Digital VSS. GND AM3 LVDS_VDDD LVDS Digital VDD (+3.3V). D3.3V
PLL Interface
B7 DVSS22 PLL ground related to DVDD22; supply for VCO circuit. GND A7 DVDD22 PLL power= 1.2V; supply for VCO circuit. R-D1.3V A6 DVSS21 PLL ground related to DVDD21; supply for digital circuit. GND B6 DVDD21 PLL power= 1.2V; supply for digital circuit. R-D1.3V C6 AVSS7 PLL ground related to AVDD7. GND D6 MCLK2LF Low pass filter for MCLK2PLL. C-D3.3V E6 AVDD7 PLL analog power= 3.3V; supply for MCLK2PLL. D3.3V D5 AVSS6 PLL ground related to AVSS6. GND C5 MPEGCLK2LF Low pass filter for MPEGCLK2PLL. C-D3.3V B5 AVDD6 PLL analog power= 3.3V; supply for MPEGCLK2PLL. D3.3V A5 AVSS5 PLL ground related to AVSS5. GND A4 MPEGCLK1LF Low pass filter for MPEGCLK1PLL. C-D3.3V B4 AVDD5 PLL analog power= 3.3V; supply for MPEGCLK1PLL. D3.3V C4 AVSS2 PLL ground related to AVSS2. GND D4 PLF Low pass filter for PCLKPLL. C-D3.3V C3 AVDD2 PLL analog power= 3.3V; supply for PCLKPLL. D3.3V B3 AVSS1 PLL ground related to AVSS1. GND A3 MLF Low pass filter for MCLKPLL. C-D3.3V A2 AVDD1 PLL analog power= 3.3V; supply for MCLKPLL. D3.3V B2 AVSS4 PLL ground related to AVSS4. GND A1 IDELF Low pass filter for IDECLKPLL. C-D3.3V B1 AVDD4 PLL analog power= 3.3V; supply for IDECLKPLL. D3.3V C1 AVDD3 PLL analog power= 3.3V; supply for CK48MPLL. D3.3V C2 CK48MLF Low pass filter for CK48MPLL. C-D3.3V D3 AVSS3 PLL ground related to AVSS3. GND D2 XTLI I 24MHz_PLL crystal input. X-TAL D1 XTLO O 24MHz_PLL crystal output. X-TAL E1 DVSS12 PLL ground related to DVDD12; supply for VCO circuit. GND E2 DVDD12 PLL power= 1.2V; supply for VCO circuit. R-D1.3V E3 DVSS11 PLL ground related to DVDD11; supply for digital circuit. GND E4 DVDD11 PLL power= 1.2V; supply for digital circuit. R-D1.3V
FLASH Interface
E25 AD30_FRA14 I/O Flash address 14/PCI AD bus bit 30. FRA_14 D24 AD28_FRA12 I/O Flash address 12/PCI AD bus bit 28. FRA_12 E24 AD26_FRA10 I/O Flash address 10/PCI AD bus bit 26. FRA_10 A23 AD29_FRA13 I/O Flash address 13/PCI AD bus bit 29. FRA_13 B23 AD31_FRA15 I/O Flash address 15/PCI AD bus bit 31. FRA_15 D23 AD24_FRA8 I/O Flash address 8/PCI AD bus bit 24. FRA_8 E23 AD22_FRA6 I/O Flash address 6/PCI AD bus bit 22. FRA_6 A22 CBE3#_FRA19 I/O Flash address 19/PCI CBE#[3]. FRA_19 B22 AD25_FRA9 I/O Flash address 9/PCI AD bus bit 25. FRA_9 C22 AD27_FRA11 I/O Flash address 11/PCI AD bus bit 27. FRA_11 D22 AD20_FRA4 O Flash address 4/PCI AD bus bit 20/POD host interface Card access
register selection.
FRA_4
E22 AD18_FRA2 O Flash address 2/PCI AD bus bit 18/POD host interface Card output
enable.
FRA_2
A21 AD19_FRA3 O Flash address 3/PCI AD bus bit 19/POD host interface Card Write
enable.
FRA_3
B21 AD21_FRA5 O Flash address 5/PCI AD bus bit 21. FRA_5
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C21 AD23_FRA7 O Flash address 7/PCI AD bus bit 23. FRA_7 D21 AD16_FRA0 O Flash address 0/PCI AD bus bit 16/POD host interface Card output
enable.
FRA_0
A20 IRDY_PCAS I/O PCI bus IRDY# signal/M68K CPU interface address strobe signal. PCI_IRDY B20 CBE2#_FRA18 O Flash address 18/PCI CBE#[2]. FRA_18 C20 AD17_FRA1 O Flash address 1/PCI AD bus bit 17/POD host interface Card Write
enable.
FRA_1
A19 CBE1#_FRA17 O Flash address 17/PCI CBE#[1]. FRA_17 E19 AD15_FRD15 I/O Flash Data bus bit 15/PCI AD bus bit 15. FRD_15 A18 AD7_FRD7 I/O Flash Data bus 7/PCI AD bus bit 7. FRD_7 B18 AD10_FRD10 I/O Flash Data bus bit 10/PCI AD bus bit 10/POD host interface address
bit 2.
FRD_10
C18 AD12_FRD12 I/O Flash Data bus bit 12/PCI AD bus bit 12/POD host interface address
bit 10.
FRD_12
D18 AD13_FRD13 I/O Flash Data bus bit 13/PCI AD bus bit 13/POD host interface address
bit 13.
FRD_13
E18 AD11_FRD11 I/O Flash Data bus bit 11/PCI AD bus bit 11/POD host interface address
bit 3.
FRD_11
A17 AD8_FRD8 I/O Flash Data bus bit 8/PCI AD bus bit 8/POD host interface address
bit 0.
FRD_8
B17 AD14_FRD14 I/O Flash Data bus bit 14/PCI AD bus bit 14/POD host interface address
bit 12.
FRD_14
C17 AD9_FRD9 I/O Flash Data bus bit 9/PCI AD bus bit 9/POD host interface address
bit 1.
FRD_9
D17 AD6_FRD6 I/O Flash Data bus bit 6/PCI AD bus bit 6/POD host interface Data bus
bit 6.
FRD_6
E17 CBE0#_FRA16 O Flash address bit 16/PCI CBE#[0]. FRA_16 A16 AD5_FRD5 O Flash Data bus bit 5/PCI AD bus bit 5/POD host interface Data bus
bit 5.
FRD_5
B16 AD1_FRD1 I/O Flash Data bus bit 1/PCI AD bus bit 1/POD host interface Data bus
bit 1.
FRD_1
C16 AD3_FRD3 I/O Flash Data bus bit 3/PCI AD bus bit 3/POD host interface Data bus
bit 3.
FRD_3
D16 AD2_FRD2 I/O Flash Data bus bit 2/PCI AD bus bit 2/POD host interface Data bus
bit 2.
FRD_2
E16 AD4_FRD4 I/O Flash Data bus bit 4/PCI AD bus bit 4/POD host interface Data bus
bit 4.
FRD_4
E15 AD0_FRD0 I/O Flash Data bus bit 0/PCI AD bus bit 0/POD host interface Data bus
bit 0.
FRD_0
D15 FRA25 I/O Flash address bit 25. FRA_25 C15 FRA24 I/O Flash address bit 24. FRA_24 B15 FRA23 I/O Flash address bit 23. FRA_23 A15 FRA22 I/O Flash address bit 22. FRA_22 A14 FRA21 I/O Flash address bit 21. FRA_21 B14 FRA20 I/O Flash address bit 20. FRA_20 C14 GCS3 I/O Flash chip select (0: Active). TL8103 D14 GCS2 I/O Flash chip select (0: Active). TL8104 E14 GCS1 I/O Flash chip select (0: Active). N_CPLD_CS1 E13 GCS0 I/O Flash chip select (0: Active). N_CPLD_CS2 D13 BOOTCS O EPPROM chip select (0: Active). ROM_CE C13 FWE# O Write enable signal of Flash Rom. XEWE B13 FOE# O Read enable signal of Flash Rom. XERE A13 NAND_CE# O Chip select signal of NAND Flash Rom. TL8102 A12 NAND_RDY I Ready signal of NAND Flash Rom. TL8101
PCI Interface
A27 INTA I PCI interrupt A. R-D3.3V C25 INTB I PCI interrupt B. R-D3.3V B27 INTC I PCI interrupt C. R-D3.3V B25 INTD I PCI interrupt D. R-D3.3V D27 GNT0 O PCI gnt signal. (no connected) open D26 GNT1 O PCI gnt signal. (no connected) open E26 GNT2 O PCI gnt signal. (no connected) open D25 GNT3 O PCI gnt signal. (no connected) open C27 PCIRST# O PCIRSTN/68K clock output. R-D3.3V A25 PCICLK O PCI clock. R-D3.3V C24 REQ0 I PCI req signal. R-D3.3V
Pin No. Pin Name I/O Pin Function Sheet Name
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B24 REQ1 I PCI req signal. R-D3.3V A24 REQ2 I PCI req signal. R-D3.3V C23 REQ3 I PCI req signal. R-D3.3V E21 FRAME#_SIZI I/O PCI bus FRAME# signal/68K Transfer size bit 1.
(along with Transfer size bit 0 to indicate the number byte to be transferred during a bus cycle M68K CPU bus.)
PCI_FRAM
A20 IRDY_PCAS I/O PCI bus IRDY# signal/68K address strobe signal. PCI_IRDY B20 CBE2#_FRA18 I/O PCI bus CBE#[2]/Flash address bit 18. FRA_18 D20 TRDY#_SIZ0 I/O PCI bus TRDY# signal/68K Transfer size bit 0. PCI_TRDY B19 SEPR#_DSACK1 I/O PCI bus SERR# signal/68K Data and Size acknowledge signal bit 1. PCI_SERR C19 DVSEL_PCDS I/O PCI bus DEVSEL# signal/68K Data Strobe signal. PCI_DVSL D19 PAR_DSACK0 I/O PCI bus PAR signal/68K Data and Size acknowledge signal bit 0. PCI_PAR E20 STOP#_PCRW I/O PCI bus STOP signal/Flash, 3.3V CMOS IF, 16mA output pad. PCI_STOP
POD Interface
B12 POD_ITX I POD OOB TXI Channel. R-D3.3V C12 POD_WAIT I POD WAIT# signal to expand bus cycle. POD_WAIT D12 POD_CE1 O Card enable. POD_CEI E12 POD_CTX O POD OOB TX Gapped Symbol clock. R-D3.3V A11 POD_DRX O POD OOB RX data. R-D3.3V B11 POD_CD1 I Card Detect. POD_CDI C11 POD_IREQ I Ready/IRQ POD_IREQ D11 POD_CRX O POD OOB RX Gapped clock. R-D3.3V E11 POD_RESET O POD Card reset signal. POD_RESET A10 POD_QTX I POD OOB TX Q Channel. R-D3.3V B10 POD_VS1 I Card voltage Sense. POD_VS1 C10 POD_ETX I POD OOB TX enable. R-D3.3V D10 POD_CD2 I Card Detect. POD_CD2 E10 POD_CE2 O Card enable. POD_CE2 A9 POD_VPP_EN O Slot VPP enable. R-D3.3V B9 POD_OVERLOAD I Current overload detect. R-D3.3V C9 POD_VPP_EN# O Slot VPP enable. R-D3.3V D9 POD_VCC_EN# O Slot VCC enable. R-D3.3V E9 POD_VCC_EN O Slot VCC enable. R-D3.3V A8 POD_A9 O POD Host interface address bit 9. POD_A9 B8 POD_A8 O POD Host interface address bit 8. POD_A8 C8 POD_A7 I/O POD Host interface address bit 7. POD_A7 D8 POD_A6 I/O POD Host interface address bit 6. POD_A6 D7 POD_A5 I/O POD Host interface address bit 5. POD_A5 C7 POD_A4 O POD Host interface address bit 4. POD_A4
VDA Interface
AP13, AN13, AM13, AL13, AK13, AP14, AN14, AM14, AL14, AK14
VDA_R[9:0] I Video input, R channel. (no connected) R-GND
AP15, AN15, AM15, AL15, AK15, AM16, AL16, AK16, AP17, AN17
VDA_B[9:0] I Video input, B channel. (no connected) R-GND
AM17, AL17, AK17, AP18, AN18, AM18, AL18, AK18, AP19, AN19
VDA_G[9:0] I Video input, G channel. (no connected) R-GND
AP16 VDA_CLK I Video input, Clock. (no connected) R-GND AM19 VDA_VS I Video input, Vertical sync. (no connected) R-GND AL19 VDA_HS I Video input, Horizontal sync. (no connected) R-GND AK19 VDA_DE I Video input, Data enable. (no connected) R-GND
VDB Interface, EJTAG, IDE and POD2 share with VDB
AK20 VDB_DE I/O Video input/output: data enable;
IDE: IDE bus interrupt. EJTAG: NOP POD2: POD_CE2B#, the second POD Card enable.
VDB_DE
AL20 VDB_HS I/O Video input/output: Horizontal sync;
IDE: PDIAGCBLID, Passed diagnostics, cable assembly type identi­fier. EJTAG: TDI2, TDI EJTAG input of slave CPU. POD2: POD_A_B5, the second POD host interface address bit 5.
VDB_HS
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AM20 VDB_VS I/O Video input/output: Vertical sync;
IDE: DMAREQ, IDE bus DMA request. EJTAG: NOP POD2: POD_A_B4, the second POD host interface address bit 4.
VDB_VS
AN20 VDB_G0 I/O Video input/output: Green channel bit 0;
IDE: IDE data bus bit 0. EJTAG: TDO2, TDO EJTAG input of slave CPU CPU. POD2: POD_A_B6, the second POD host interface address bit 6.
VDB_G0
AP20 VDB_G1 I/O Video input/output: Green channel bit 1;
IDE: IDE data bus bit 1. EJTAG: TMS2, TMS EJTAG input of slave CPU CPU. POD2: POD_A_B7, the second POD host interface address bit 7.
VDB_G1
AK21 VDB_G2 I/O Video input/output: Green channel bit 2;
IDE: IDE data bus bit 2. EJTAG: TCK2, TCK EJTAG input of slave CPU CPU. POD2: POD_A_B8, the second POD host interface address bit 8.
VDB_G2
AL21 VDB_G3 I/O Video input/output: Green channel bit 3;
IDE: IDE data bus bit 3. EJTAG: DCLK EJTAG output of both CPU CPUs. POD2: POD_A_B8, the second POD host interface address bit 9.
VDB_G3
AM21 VDB_G4 I/O Video input/output: Green channel bit 4;
IDE: IDE data bus bit 4. EJTAG: TPC[0], output as EJTAG PC Trace bus, bit 0. POD2: POD_CD2B#, the second POD interface card detect.
VDB_G4
AN21 VDB_G5 I/O Video input/output: Green channel bit 5;
IDE: IDE data bus bit 5. EJTAG: TPC[1], output as EJTAG PC Trace bus, bit 1. POD2: POD_CD1B#, the second POD interface card detect.
VDB_G5
AP21 VDB_G6 I/O Video input/output: Green channel bit 6;
IDE: IDE data bus bit 6. EJTAG: TPC[2], output as EJTAG PC Trace bus, bit 2. POD2: POD_RSTB, the second POD host interface reset.
VDB_G6
AK22 VDB_G7 I/O Video input/output: Green channel bit 7;
IDE: IDE data bus bit 7. EJTAG: TPC[3], output as EJTAG PC Trace bus, bit 3. POD2: POD_A_B14, the second POD host interface address bit 14.
VDB_G7
AL22 VDB_G8 I/O Video input/output: Green channel bit 8;
IDE: IDE data bus bit 8. EJTAG: TPC[4], output as EJTAG PC Trace bus, bit 4. POD2: POD2_TS2_D0, the second POD TS2 data[0].
VDB_G8
AM22 VDB_G9 I/O Video input/output: Green channel bit 9;
IDE: IDE data bus bit 9. EJTAG: TPC[5], output as EJTAG PC Trace bus, bit 5. POD2: POD2_TS2_D2, the second POD TS2 data[1].
VDB_G9
AN22 VDB_B0 I/O Video input/output: Blue channel bit 0;
IDE: IDE data bus bit 10. EJTAG: TPC[6], output as EJTAG PC Trace bus, bit 6. POD2: POD2_TS2_D2, the second POD TS2 data[2].
VDB_B0
AP22 VDB_B1 I/O Video input/output: Blue channel bit 1;
IDE: IDE data bus bit 11. EJTAG: TPC[7], output as EJTAG PC Trace bus, bit 7. POD2: POD2_TS2_D3, the second POD TS2 data[3].
VDB_B1
AK23 VDB_B2 I/O Video input/output: Blue channel bit 2;
IDE: IDE data bus bit 12. EJTAG: PCST[0], output as EJTAG PC Trace bus, bit 0. POD2: POD2_TS2_D4, the second POD TS2 data[4].
VDB_B2
AL23 VDB_B3 I/O Video input/output: Blue channel bit 3;
IDE: IDE data bus bit 13. EJTAG: PCST[1], output as EJTAG PC Trace bus, bit 1. POD2: POD2_TS2_D5, the second POD TS2 data[5].
VDB_B3
AM23 VDB_B4 I/O Video input/output: Blue channel bit 4;
IDE: IDE data bus bit 14. EJTAG: PCST[2], output as EJTAG PC Trace bus, bit 2. POD2: POD2_TS2_D6, the second POD TS2 data[6].
VDB_B4
AP23 VDB_CLK I/O Video input/output: Clock;
IDE: IDE data bus IO access complete. EJTAG: NOP POD2: POD_CE1B#, the second POD interface card enable.
VDB_CLK
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AK24 VDB_B5 I/O Video input/output: Blue channel bit 5;
IDE: IDE data bus bit 15. EJTAG: PCST[3], output as EJTAG PC Trace bus, bit 3. POD2: POD2_TS2_D7, the second POD TS2 data[7].
VDB_B5
AL24 VDB_B6 I/O Video input/output: Blue channel bit 6;
IDE: Chip Select 0 for IDE interface. EJTAG: PCST[4], output as EJTAG PC Trace bus, bit 4. POD2: POD2_TS2_DEN, the second POD TS2 data valid.
VDB_B6
AM24 VDB_B7 I/O Video input/output: Blue channel bit 7;
IDE: Chip Select 1 for IDE interface. EJTAG: PCST[5], output as EJTAG PC Trace bus, bit 5. POD2: POD2_TS2_CLK, the second POD TS2 clock.
VDB_B7
AN24 VDB_B8 I/O Video input/output: Blue channel bit 8;
IDE: IDE address bus bit 0. EJTAG: PCST[6], output as EJTAG PC Trace bus, bit 6. POD2: POD2_TS2_SYNC, the second POD TS2 SYNC.
VDB_B8
AP24 VDB_B9 I/O Video input/output: Blue channel bit 9;
IDE: IDE address bus bit 1. EJTAG: PCST[7], output as EJTAG PC Trace bus, bit 7. POD2: POD2_TS1_D0, the second POD TS1 data[0].
VDB_B9
AK25 VDB_R0 I/O Video input/output: Red channel bit 0;
IDE: IDE address bus bit 2. EJTAG: PCST[8], output as EJTAG PC Trace bus, bit 8. POD2: POD2_TS1_D1, the second POD_TS1 data[1].
VDB_R0
AL25 VDB_R1 I/O Video input/output: Red channel bit 1;
IDE: IDE bus DMA acknowledge. EJTAG: PCST[9], output as EJTAG PC Trace bus, bit 9. POD2: POD2_TS1_D2, the second POD TS1 data[2].
VDB_R1
AM25 VDB_R2 I/O Video input/output: Red channel bit 2;
IDE: IDE bus IO Read Strobe signal. EJTAG: PCST[10], output as EJTAG PC Trace bus, bit 10. POD2: POD2_TS1_D3, the second POD TS1 data[3].
VDB_R2
AN25 VDB_R3 I/O Video input/output: Red channel bit 3;
IDE: IDE bus IO Write Strobe signal. EJTAG: PCST[11], output as EJTAG PC Trace bus, bit 11. POD2: POD2_TS1_D4, the second POD TS1 data[4].
VDB_R3
AP25 VDB_R4 I/O Video input/output: Red channel bit 4;
IDE: nop. EJTAG: S1=0, select DCLK/TPC[7:0]/PCST[11:0] of host CPU as output. S1=1, select DCLK/TPC[7:0]/PCST[11:0] of slave CPU as output. POD2: POD2_TS1_D5, the second POD TS1 data[5].
VDB_R4
AK26 VDB_R5 I/O Video input/output: Red channel bit 5;
IDE: nop. EJTAG: S1=0, two EJTAG are separately used. S1=1, two EJTAG are used in a daisy chain style. POD2: POD2_TS1_D6, the second POD TS1 data[6].
VDB_R5
AL26 VDB_R6 I/O Video input/output: Red channel bit 6;
IDE: nop. EJTAG: TDI1, TDI EJTAG input of host CPU CPU. POD2: POD2_TS1_D7, the second POD TS1 data[7].
VDB_R6
AM26 VDB_R7 I/O Video input/output: Red channel bit 7;
IDE: nop. EJTAG: TDO1, TDO EJTAG input of host CPU CPU. POD2: POD2_TS1_DEN, the second POD TS1 data valid.
VDB_R7
AN26 VDB_R8 I/O Video input/output: Red channel bit 8;
IDE: nop. EJTAG: TMS1, TMS EJTAG input of host CPU CPU. POD2: POD2_TS1_CLK, the second POD_TS1 clock.
VDB_R8
AP26 VDB_R9 I/O Video input/output: Red channel bit 9;
IDE: nop. EJTAG: TCK1, TCK EJTAG input of host CPU CPU. POD2: POD2_TS1_SYNC, the second POD TS1 SYNC.
VDB_R9
IEEE1394 Interface, 8051 and 656 share with 1394
AM7, AL7, AK7, AK8, AL8, AM8, AK9, AL9
HSD[7:0] I/O 1394: Parallel data.
Video 656 port: 656D[9:2], data[9:2] 8051: AD[7:0], AD bus.
8051_AD[0:7]
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AM9 HSDCLK I/O 1394: clock.
Video 656 port: 656CLK, clock. 8051: RD, ALE, address latch enable.
8051_ALE
AM10 HSDRW I/O 1394: Not used.
Video 656 port: 656HS, horizontal sync. 8051: RD, read signal, low active.
8051_RD
AL10 HSDSYNC I/O 1394: Packet synchronization.
Video 656 port: 656VS, vertical sync. 8051: WR, write signal, low active.
8051_WR
AK10 HSDAV I/O 1394: Not used.
Video 656 port: data[1]. 8051: nop.
EJTAG_S1
AM11 HSDEN I/O 1394: Data valid.
Video 656 port: data[0]. 8051: CS, chip select.
8051_CS
Transport Stream Interface
G4, G5, F1, F2, F3, F4, F5, E5
TS2_D[7:0] I Transport Stream 2, data bus. TS2_D[7:0]
G3 TS2_DEN I Transport Stream 2, data enable. TS2_DEN G2 TS2_SYNC I Transport Stream 2, sync signal. TS2_SYNC G1 TS2_CLK I Transport Stream 2, clock. TS2_CLK J3, J2, J1, H1, H2, H3,
H4, H5
TS1_D[7:0] I Transport Stream 1, data bus. FED[7:0]
J4 TS1_DEN I Transport Stream 1, data enable. FEVAL_DEN_CI J5 TS1_SYNC I Transport Stream 1, sync signal. FESTR_PSYNC_CI K1 TS1_CLK I Transport Stream 1, clock. FECLK_CI Memory Interface Sheet Name AM30 DRVIMP I Driving strength impedance match reference pin. R-GND AP29 MD0 I/O Memory data bus. DDR_DQ3 AP30 MD1 I/O Memory data bus. DDR_DQ1 AN30 MD2 I/O Memory data bus. DDR_DQ6 AN31 MD3 I/O Memory data bus. DDR_DQ4 AM33 DQM0 O Memory data write mask enable for byte 0. DDR_DM0 AM32 DQS0 I/O Data strobe for memory data bus MD[7:0]. DDR_DQS0 AL32 DQS0N I/O Data strobe for memory data bus MD[7:0]. DDR_DQS0# AK30 MD4 I/O Memory data bus. DDR_DQ7 AK31 MD5 I/O Memory data bus. DDR_DQ0 AJ29 MD6 I/O Memory data bus. DDR_DQ5 AJ30 MD7 I/O Memory data bus. DDR_DQ2 AP32 MD8 I/O Memory data bus. DDR_DQ12 AP33 MD9 I/O Memory data bus. DDR_DQ11 AN33 MD10 I/O Memory data bus. DDR_DQ9 AN34 MD11 I/O Memory data bus. DDR_DQ14 AM34 DQM1 O Memory data write mask enable for byte 1. DDR_DM1 AL33 DQS1 I/O Data strobe for memory data bus MD[15:8]. DDR_DQS1 AL34 DQS1N I/O Data strobe for memory data bus MD[15:8]. DDR_DQS1# AK33 MD12 I/O Memory data bus. DDR_DQ15 AK34 MD13 I/O Memory data bus. DDR_DQ8 AJ32 MD14 I/O Memory data bus. DDR_DQ10 AJ33 MD15 I/O Memory data bus. DDR_DQ13 AH33 MCLK0 O Memory clock for MD[31:0]. DDR_CKP0 AH34 MCLK0N O Memory clock for MD[31:0] - active LOW. DDR_CKN0 AG29 MD16 I/O Memory data bus. DDR_DQ19 AG30 MD17 I/O Memory data bus. DDR_DQ17 AF30 MD18 I/O Memory data bus. DDR_DQ22 AF31 MD19 I/O Memory data bus. DDR_DQ20 AE33 DQM2 O Memory data write mask enable for byte 2. DDR_DM2 AE32 DQS2 I/O Data strobe for memory data bus MD[23:16]. DDR_DQS2 AD32 DQS2N I/O Data strobe for memory data bus MD[23:16]. DDR_DQS2# AC30 MD20 I/O Memory data bus. DDR_DQ23 AC31 MD21 I/O Memory data bus. DDR_DQ16 AB29 MD22 I/O Memory data bus. DDR_DQ21 AB30 MD23 I/O Memory data bus. DDR_DQ18 AG32 MD24 I/O Memory data bus. DDR_DQ28 AG33 MD25 I/O Memory data bus. DDR_DQ27 AF33 MD26 I/O Memory data bus. DDR_DQ25
Pin No. Pin Name I/O Pin Function Sheet Name
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AF34 MD27 I/O Memory data bus. DDR_DQ30 AE34 DQM3 O Memory data write mask enable for byte 3. DDR_DM3 AD33 DQS3 I/O Data strobe for memory data bus MD[31:24]. DDR_DQS3 AD34 DQS3N I/O Data strobe for memory data bus MD[31:24]. DDR_DQS3# AC33 MD28 I/O Memory data bus. DDR_DQ31 AC34 MD29 I/O Memory data bus. DDR_DQ24 AB32 MD30 I/O Memory data bus. DDR_DQ26 AB33 MD31 I/O Memory data bus. DDR_DQ29 Y33 ODT O ODT DDR_ODT0 W34 CAS O Column Access Strobe of Port A or SCAN data input. N-DDR-CAS W33 RAS O Row Access Strobe of Port A or SCAN data input. N-DDR-RAS W31 WE O Write Enable of Port A or SCAN data input. N-DDR-WE W30 CKE O Clock enable. DDR-CKE V34 CS0 O Chip select for Ext Mem. N-DDR-CS0 Y32 MAA12 O Memory Address line of Port A or SCAN data output. DDR_A12 U33 MAA10 O Memory Address line of Port A or SCAN data output. DDR_A10 U32 BA1 O Internal Bank Address Select for SDRAM. DDR_BA1 U30 BA0 O Internal Bank Address Select for SDRAM. DDR_BA0 T34 MAA0 O Memory Address line of Port A or SCAN data output. DDR_A0 T31 MAA1 O Memory Address line of Port A or SCAN data output. DDR_A1 T33 MAA2 O Memory Address line of Port A or SCAN data output. DDR_A2 T30 MAA3 O Memory Address line of Port A or SCAN data output. DDR_A3 R32 MAA4 O Memory Address line of Port A or SCAN data output. DDR_A4 R30 MAA5 O Memory Address line of Port A or SCAN data output. DDR_A5 R33 MAA6 O Memory Address line of Port A or SCAN data output. DDR_A6 R29 MAA7 O Memory Address line of Port A or SCAN data output. DDR_A7 P34 MAA11 O Memory Address line of Port A or SCAN data output. DDR_A11 P33 MAA8 O Memory Address line of Port A or SCAN data output. DDR_A8 P30 MAA9 O Memory Address line of Port A or SCAN data output. DDR_A9 N29 MD32 I/O Memory data bus. DDR_DQ35 N30 MD33 I/O Memory data bus. DDR_DQ33 M30 MD34 I/O Memory data bus. DDR_DQ38 M31 MD35 I/O Memory data bus. DDR_DQ36 L33 DQM4 O Memory data write mask enable for byte 4. DDR_DM4 L32 DQS4 I/O Data strobe for memory data bus MD[39:32]. DDR_DQS4 K32 DQS4N I/O Data strobe for memory data bus MD[39:32]. DDR_DQS4# J30 MD36 I/O Memory data bus. DDR_DQ39 J31 MD37 I/O Memory data bus. DDR_DQ32 H29 MD38 I/O Memory data bus. DDR_DQ37 H30 MD39 I/O Memory data bus. DDR_DQ34 N32 MD40 I/O Memory data bus. DDR_DQ44 N33 MD41 I/O Memory data bus. DDR_DQ43 M33 MD42 I/O Memory data bus. DDR_DQ41 M34 MD43 I/O Memory data bus. DDR_DQ46 L34 DQM5 O Memory data write mask enable for byte 5. DDR_DM5 K33 DQS5 I/O Data strobe for memory data bus MD[47:40]. DDR_DQS5 K34 DQS5N I/O Data strobe for memory data bus MD[47:40]. DDR_DQS5# J33 MD44 I/O Memory data bus. DDR_DQ47 J34 MD45 I/O Memory data bus. DDR_DQ40 H32 MD46 I/O Memory data bus. DDR_DQ42 H33 MD47 I/O Memory data bus. DDR_DQ45 G33 MCLK1 O Memory clock for MD[63:32]. DDR_CKP1 G34 MCLK1N O Memory clock for MD[63:32] - active LOW. DDR_CKN1 F29 MD48 I/O Memory data bus. DDR_DQ51 F30 MD49 I/O Memory data bus. DDR_DQ49 E30 MD50 I/O Memory data bus. DDR_DQ54 E31 MD51 I/O Memory data bus. DDR_DQ52 D33 DQM6 O Memory data write mask enable for byte 6. DDR_DM6 D32 DQS6 I/O Data strobe for memory data bus MD[55:48]. DDR_DQS6 C32 DQS6N I/O Data strobe for memory data bus MD[55:48]. DDR_DQS6# B30 MD52 I/O Memory data bus. DDR_DQ55 B31 MD53 I/O Memory data bus. DDR_DQ48 A29 MD54 I/O Memory data bus. DDR_DQ53 A30 MD55 I/O Memory data bus. DDR_DQ50
Pin No. Pin Name I/O Pin Function Sheet Name
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F32 MD56 I/O Memory data bus. DDR_DQ60 F33 MD57 I/O Memory data bus. DDR_DQ59 E33 MD58 I/O Memory data bus. DDR_DQ57 E34 MD59 I/O Memory data bus. DDR_DQ62 D34 DQM7 O Memory data write mask enable for byte 7. DDR_DM7 C33 DQS7 I/O Data strobe for memory data bus MD[63:56]. DDR_DQS7 C34 DQS7N I/O Data strobe for memory data bus MD[63:56]. DDR_DQS7# B33 MD60 I/O Memory data bus. DDR_DQ63 B34 MD61 I/O Memory data bus. DDR_DQ56 A32 MD62 I/O Memory data bus. DDR_DQ58 A33 MD63 I/O Memory data bus. DDR_DQ61
CPU Interface
B26 MASTSEL I Lexra bus master select, H: I2C, L: 1x5180. R-GND
Interrupt Interface
T1 INT1 I External interrupt, low active. Edge or level. N_CPLD_INTO
I2C Interface
W5 SCLMAST2 I/O I2C master 2 clock. SCL1 Y5 SDAMAST2 I/O I2C master 2 data. SDA1 AE5 SCLMAST1 I/O I2C master 1 clock. SCL0 AF5 SDAMAST1 I/O I2C master 1 data. SDA0
I2S Interface
T3 SCKIN O I2S: SCK of I2S input port. (Not used)
AC Link: SDATA_OUT POD2: POD_DRXB, the second POD OOB RX data.
open
T4 WSI2S I I2S: WS of I2S input port. (Not used)
AC Link: ACLINK_RSTN POD2: POD_CRXB, the second POD OOB RX gapped clock.
open
T5 SDI2S I I2S: SD of I2S input port. (Not used)
AC Link: SYNC POD2: POD_QTXB, the second POD OOB TXQ channel.
open
U1 WS O I2S: WS of I2S output port.
AC Link: SDATA_IN_2
DTV_WS
U2 SCK O I2S: SCK of I2S output port.
AC Link: SDATA_IN_3
DTV_SCK
U3 SD1 O I2S: SD of I2S output port.
AC Link: BIT_CLK
DTV_SDO
U4 SD2 O I2S: SD of I2S output port. (Not used)
AC Link: SDATA_IN_0
open
U5 SD3 O I2S: SD of I2S output port. (Not used)
AC Link: SDATA_IN_1
open
V5 I2SCLK O I2S: 1, 2, 4, 8 times of SCK of I2S output port, used by D/A chip. DACCLK V4 SD4 I I2S: SCK of second I2S input port. (Not used)
POD2: POD_ETXB, the second POD OOB TX enable.
open
V3 SD5 I I2S: WS of second I2S input port. (Not used)
POD2: POD_ITXB, the second POD OOB TXI channel.
open
V2 SD6 I I2S: SD of second I2S input port. (Not used)
POD2: POD_CTXB, the second POD OOB TX gapped symbol clock.
open
SPDIF Interface
T2 SPDIF I/O SPDIF output. DTV_SPDIF
UART Interface
Y4 TXD O Data output for UART. UATXD1_1 Y3 RTS O Request to send output for UART (8mA output pad). UATXD2_1 Y2 DTR O Data terminal Ready output for UART (8mA output pad, 5V TTL
interface 25PF, 6ns rise timing).
open
Y1 RXD I Data input for UART. UARXD1_1 AA1 CTS I Clear to send input for UART. UARXD2_1 AA2 DSR I Data set ready for UART. open AA3 DCD I Receive line signal detect for UART. (Not used) open AA4 RI I Ring indicator for UART. (Not used) open
Smart card Interface
V1 SCRST I Smart card reset 0, 8mA open-drain output pad. (Not used) open W1 SCPFET I Smart card power FET control output, 8mA open-drain output. The
smart card reader interface requires this pin to drive an external power FET to supply the current for the Smart Card (65mA typical, 100mA short to ground). (Not used)
open
Pin No. Pin Name I/O Pin Function Sheet Name
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W2 SCIO I/O Smart card serial data, 8mA open-drain in out pad. (Not used) open W3 SCCLK O Smart card clock, 8mA open-drain output pad (7.1M to 3.5M) (Not
used)
open
W4 SCPRES I Smart card present detect. (Not used) open
CIR, RTC Interface
M1 VCCH12 1.2V RTC power for logic. D1.3V N1 VSSH12 RTC ground for logic. GND L1 WDOG O Watch dog reset. TL8108 L2 VCCH33 3.3V RTC power for logic. D3.3V L3 CK32 I 32.768 kHz crystal oscillator input. X-TAL L4 CK32E O 32.768 kHz crystal oscillator output. X-TAL L5 VSSH33 RTC ground for logic. GND M5 CRX0 I CIR0, receive data for CIRo interface. R-GND M4 PWRON O Main power, power On control signal, low active, 4mA output pad.
(Not used)
TL8107
M3 PWRBT I Power switch button. R-3.3V M2 VCCHRST I VCCH RST N_VCCH_RST K4 VCCH12 1.2V RTC power for logic. D1.3V K5 VSSH12 RTC ground for logic. GND R1 CTX0 O Transmission data for CIR interface. open
Program IO
AF4 GP15 I/O Program IO.
PWM: Pulse-Width Modulation. POD: OVERLOAD, the second POD interface current overload.
FESTR_PSYNC
AF3 GP14 I/O Program IO.
PWM: Pulse-Width Modulation. POD: VS1, the second POD interface voltage sense.
FECLK
AF2 GP13 I/O Program IO.
PWM: Pulse-Width Modulation. POD: VPP_EN#, the second POD interface slot VPP enable.
FED_D
AF1 GP12 I/O Program IO.
PWM: Pulse-Width Modulation. POD: VPP_EN, the second POD interface slot VPP enable.
EJTAG_S0
AG1 GP11 I/O Program IO.
PWM: Pulse-Width Modulation. POD: VCC_EN#, the second POD interface slot VCC enable.
TDO_EJTAG
AG2 GP10 I/O Program IO.
PWM: Pulse-Width Modulation. POD: VCC_EN, the second POD interface slot VCC enable.
TDI_EJTAG
AG3 GP9 I/O Program IO.
PWM: Pulse-Width Modulation. POD: WAIT#, WAIT# signal to expend bus cycle.
TMS_EJTAG
AG4 GP8 I/O Program IO.
PWM: Pulse-Width Modulation. POD: Ready and IREQ.
TCK_EJTAG
AG5 GP7 I/O Program IO.
PWM: Pulse-Width Modulation. POD: SI2C1_SDA, I2C bus SDA.
TP8101
AH5 GP6 I/O Program IO.
PWM: Pulse-Width Modulation. POD: SI2C1_SCL, I2C bus SCL.
TP8102
AH4 GP5 I/O Program IO.
PWM: Pulse-Width Modulation. POD: SI2C1_DEVID, I2C bus DEVID.
open
AH3 GP4 I/O Program IO.
PWM: Pulse-Width Modulation. POD: SI2C2_SDA, I2C bus SDA.
FEVAL_DEN
AH2 GP3 I/O Program IO.
PWM: Pulse-Width Modulation.
D8102 LED
AH1 GP2 I/O Program IO.
PWM: Pulse-Width Modulation.
D8101 LED
AJ1 GP1 I/O Program IO.
PWM: Pulse-Width Modulation. POD: SI2C2_SCL, I2C bus SCL.
TP8102
AJ2 GP0 I/O Program IO.
PWM: Pulse-Width Modulation. POD: SI2C2_DEVID, I2C bus DEVID.
open
Pin No. Pin Name I/O Pin Function Sheet Name
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Power and ground pins
A26, AJ20, Y6 V5SF 5V safe power. AA13, AA22, AB13, AB14, AB21, AB22, AD6, AE6, AF6, AG6, AH6,
AJ8, AJ9, AJ10, AJ11, AJ12, AJ16, AJ17, AJ18, AJ19, AK11, AK12, AL11, AL12, AM12, AN12, AP12, E7, E8, F6, F7, F8, F9, G6, H6, J6, N13, N14, N21, N22, P13, P22, T6, U6, V6, W6
VDDC Core power supply= 1.2V
A28, B28, C28, C29, D28, D29, E27, E28, F16, F17, F18, F19, F23, F24, F25, F26, F27, F28, K6, L 6, M6
VDDF Power supply= 3.3V
AE31, AM31, C31, L31 VDDI33 3.3V power for DDR IO input buffer. D3.3V AA29, AA30, AA31,
AA32, AA33, AA34, AD29, AD30, AE29, AE30, AH29, AH30, AH31, AJ27, AJ28, AK27, AK28, AL27, AL28, AM27, AM28, AM29, AN27, AN28, AP27, AP28, G29, G30, G31, K29, K30, L29, L30, V31, V32, W29, Y29, Y30
VDDM 2.5V supply ring for memory interface (Long PAD).
VSS IO ground related to VDDF./Core ground related to VDDC.
A31, A34, AA6, AA14, AA15, AA16, AA17, AA18, AA19, AA20, AA21, AB6, AB15, AB16, AB17, AB18, AB19, AB20, AB31, AB34, AC6, AC29, AC32, AD31, AF29, AF32, AG31, AG34, AH32, AJ13, AJ14, AJ15, AJ21, AJ23, AJ24, AJ25, AJ26, AJ31, AJ34, AK32, AL31, AN16, AN23, AN29, AN32, AP31, AP34, B32, D31, E29, E32, F10, F11, F12, F13, F14, F15, F20, F21, F22, F31, F34, G32, H31, H34, J29, J32, K31, M29, M32, N6, N15, N16, N17, N18, N19, N20, N31, N34, P6, P14, P15, P16, P17, P18, P19, P20, P21, P29, P32, R6, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R31, R34, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T29, T32, U13, U14, U15, U16, U17, U18, U19, U20, U21, U22, U31, V13, V14, V15, V16, V17, V18, V19, V20, V21, V22, V33, W13, W14, W15, W16, W17, W18, W19, W20, W21, W22, W32, Y13, Y14, Y15,
Y16, Y17, Y18, Y19, Y20, Y21, Y22, Y31, Y34 AL29, V29, C30 MVREF Memory interface voltage reference. GND AL30, V30, D30 VDDR 1.8V input buffer reference power. VDDR B29,U34,AK29 VSSR Ground of input buffer reference power. GND
OTHER
C26 RESET# I System reset input, high active. N_COLD_RST AJ7 FULL_EJTAG I 1: Full EJTAG, 0:simple EJTAG. FULL_EJTAG K3 VCOTP O DEMUX output. VCOTP K2 CLK27M I DEMUX input. SB_CLK_27M AM6 PCMOD I 1: PC MODE (Not used) open AL6 TESTCON I Test mode control. TESTCON AK6 TESTMOD I Test mode input. R-GND
Pin No. Pin Name I/O Pin Function Sheet Name
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1.8. IC8301 (RH-iXC154WJQZQ)
1.8.1 Block Diagram
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1.8.2 Pin Connections and short description
Pin No. Pin Name I/O Pin Function
53, 52 CK, CK
I Clock: CK and CK are differential clock inputs.
CMD, ADD inputs are sampled on the crossing of the positive edge of CK and negative edge of CK
.
Output (read) data is referenced to the crossings of CK and CK
(both directions of crossing).
41 CKE I Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signals and device input
buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation(all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK
and CKE are disabled during powerdown.
Input buffers, excluding CKE, are disabled during self refresh.
51 CS
I Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank
selection on systems with multiple banks. CS
is considered part of the command code.
19 ODT I On Die Termination: ODT (registered HIGH) enables termination resistance internal to the gDDR2
SDRAM. When enabled, ODT is only applied to each DQ, UDQS/UDQS
, LDQS/LDQS, UDM, and LDM signal for x16 configurations. The ODT pin will be ignored if the Extended Mode Register (EMRS) is pro­grammed to disable ODT.
77, 76, 70 RAS
, CAS, WE I Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
66, 62 (L) UDM I Input Data Mask: DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH coincident with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading.
42, 71 BA0 - BA1 I Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE
command is being applied. BA0 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.
50, 72, 75, 44, 49, 73, 74, 45, 48, 46, 43, 47, 13
A0 - A12 I Address Inputs: Provided the row address for ACTIVE commands, and the column address and AUTO
PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during MODE REGISTER SET commands.
DQ I/O Data Input/ Output: Bi-directional data bus.
81, 57, 61, 29
LDQS, (LDQS
)
UDQS, (UDQS
)
I/O Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write
data. LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. The data strobes LDQS and UDQS may be used in single ended mode or paired with optional comple­mentary signals LDQS and UDQS to provide differential pair signaling to the system during both reads and writes. An EMRS (1) control bit enables or disables all complementary data strobe signals.
10, 14, 15, 16, 32, 36,
NC/RFU No Connect: No internal electrical connection is present.
3, 7, 22, 24, 26, 28, 63, 67, 80, 84
VDDQ DQ Power Supply: 1.8V ± 0.1V.
33, 35, 37, 39, 54, 56, 58, 60, 82
VSSQ DQ Ground.
9 VDDL DLL Power Supply: 1.8V ± 0.1V. 78 VSSL DLL Ground. 5, 12, 18, 20 VDD Power Supply: 1.8V ± 0.1V.
11. 17, 65, 69 VSS Ground. 40 VREF Reference voltage.
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1.9. IC9101 (RH-iXC121WJN8Q)
1.9.1 Block Diagram
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1.9.2 Pin Connections and short description
Pin No. Pin Name I/O Pin Function
1 D3.3V Power supply (+3.3V) 2 N_CPLD_CS0 I HiDTV CS0 . . . Flash 3 XERE I HiDTV PCI_BUS OE# 4 ROM_CE I BOOT ROM CE input 5 N_CPLD_CS1 I HiDTV CS1 . . . CPLD 6 XEWE I HiDTV PCI_BUS WE# 7 NC O HiDTV PCI_BUS ACK# 8 D3.3V Power supply (+3.3V) 9 FRDA_0 I/O For HiDTV PCI_BUS DATA0/CPLD control 10 FRDA_1 I/O For HiDTV PCI_BUS DATA1/CPLD control 11 FRDA_2 I/O For HiDTV PCI_BUS DATA2/CPLD control 12 FRDA_3 I/O For HiDTV PCI_BUS DATA3/CPLD control 13 FRDA_4 I/O For HiDTV PCI_BUS DATA4/CPLD control 14 FRDA_5 I/O For HiDTV PCI_BUS DATA5/CPLD control 15 FRDA_6 I/O For HiDTV PCI_BUS DATA6/CPLD control 16 FRDA_7 I/O For HiDTV PCI_BUS DATA7/CPLD control 17 FRAA_0 I HiDTV PCI_BUS ADDRESS0 18 GND_B Ground 19 FRAA_1 I For HiDTV PCI_BUS ADDRESS1/CPLD control 20 FRAA_2 I For HiDTV PCI_BUS ADDRESS2/CPLD control 21 FRAA_3 I For HiDTV PCI_BUS ADDRESS3/CPLD control 22 FRAA_4 I For HiDTV PCI_BUS ADDRESS4/CPLD control 23 FRAA_5 I For HiDTV PCI_BUS ADDRESS5/CPLD control 24 N_CPLD2_CNF_DONE I FPGA Config 25 FRAA_6 I For HiDTV PCI_BUS ADDRESS6/CPLD control 26 FRAA_22 I HiDTV PCI_BUS ADDRESS22 27 FRAA_23 I HiDTV PCI_BUS ADDRESS23 28 FRAA_24 I HiDTV PCI_BUS ADDRESS24 29 GND_B Ground 30 SBCLK_27M I HiDTV PCI_BUS CLOCK (27MHz) 31 3.3V_DPOW_DETECT I DPOW system 3.3V detection 32 NACE_N I NAND-FLASH CE output 33 CODEC_RST O CODEC reset 34 N_VCCH_RST O HiDTV standby reset 35 N_COLD_RST O HiDTV Main reset 36 GND_B Ground 37 D3.3V Power supply (+3.3V) 38 CPLD_33M I System clock (33MHz) 39 N_FLS_RST O On-Board Flash reset 40 N_EXT_RST O External Flash reset 41 N_EXT_BOOT I Flash start-up discrimination (H = On-Board, L = External) 42 D3.3V Power supply (+3.3V) 43 ROM_ADD22 O On-Board/External Flash ADDRESS22 44 ROM_ADD23 O On-Board/External Flash ADDRESS23 45 ROM_ADD24 O On-Board/External Flash ADDRESS24 46 N_ROM_RE O On-Board/External Flash OE# 47 GND_B Ground 48 N_ROM_WE O On-Board/External Flash WE# 49 N_EXT_CE O External Flash CE# 50 N_FLS_CS0 O On-Board Flash CE0# 51 N_CPLD_INT0 O HiDTV (Level interrupt, Active Low) 52 N_CPLD_INT1 O SVP_WX (Level interrupt, Active Low) 53 DSP_RST O DSP reset 54 N_TUNER_INT INT CE6353 (Level interrupt, Active Low) 55 D3.3V Power supply (+3.3V) 56 VON O Inverter ON/OFF control 57 PE O PANEL controller control signal 58 A_MUTE_ADIF I HDMI_MUTE control signal 59 BUS_SPLIT O Slow bus/video bus enable (Isolation supported) (L) 60 I2C_EXT O I2C bus enable (Isolation supported) 61 STB O inverter ON/OFF control 62 GND_B Ground 63 CPLD_TDI I CPLD_Test Data Input
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64 PNL_WP O VCOM Write Protect control signal 65 CPLD_TMS O CPLD_Test Mode Select 66 FE_RST O CE6353 reset 67 CPLD_TCK O CPLD_Test Clock 68 FEPG0_COMP O Sleep signal 69 FEPG1_LOCK I Signal LOCK detection 70 FERR_UNCOR I Error flag 71 N_TS1_DEMORST O TS1 demodulator reset 72 GND_B Ground 73 D3.3V Power supply (+3.3V) 74 EXTRG O Partner 75 DRSTMSK O Partner 76 N_IRS_INT I IrSS interrupt request 77 CLON_RC O For controlling clone remote control 78 DTM_RST O Reset signal for DTM 79 N_IRS_RST O IrSS reset signal 80 DTM_GPIO0 I Control signal for DTM (GPIO0) 81 DTM_GPIO1 O Control signal for DTM (GPIO1) 82 DTM_UART_INT I Interrupt request of UART-I2C conversion IC for DTM 83 DTM_UART_RST O Reset of UART-I2C conversion IC for DTM 84 D3.3V Power supply (+3.3V) 85 AGC_SEL O Digital/analog AGC switching control 86 HP_MUTE O HP audio mute control 87 HP_PLUG I HP connection detection (L) 88 CION O VCC/ON signal for PCMCIA 89 GND_B Ground 90 GND_B Ground 91 SC2_MUTE O SCART2 audio mute control 92 SPDIF_MUTE O SPDIF audio mute control 93 SC_MUTE O SCART1 audio mute control 94 S_STBY O Audio AMP shutdown control 95 DU_LINK_ACK0 I ACK from IEEE1394 chip 96 SIF_SW O I2C line SW control of sound multiplex decoder 97 DU_LINK_IRQ I IEEE1394 chip interrupt request 98 CNVSS O Monitor microprocessor write mode control 99 GND_B Ground 100 N_PCI_RST O PCI reset 101 RS_BUF_CNT O Monitor microprocessor UART mode switching 102 PNL_I2C_EN O VCOM/I2C switch control 103 AUDIO_SEL2 O DTV/HDMI analog audio switching control 2 104 PCHD_AUDIO_SEL O PC/HDMI external audio input switching 105 N_DVOUT_EN O DTV/AD YPbPr switching 106 MSP_RESET O MSP reset 107 HDMI_RESET O HDMI-TMDS_SW reset 108 GND_B Ground 109 D3.3V Power supply (+3.3V) 110 SVP_RESET O SVP_WX reset 111 N_PHY_RESET O i.Link PHY reset 112 N_LINK_RESET O i.Link LINK reset 113 FL_VPP0 O Flash WP 114 GND_B Ground 115 AREA_4 I Destination setting (L: Europe/H: Asia) 116 DIG_AD I DTV add-on Unit presence/absence setting 117 HDMI_SEL1 O HDMI_Select_1 118 HDMI_SEL2 O HDMI_Select_2 119 HDMI_SEL3 O HDMI_Select_3 120 HDMI_HPG1 I HDMI_HotPlug_1 (L) 121 HDMI_HPG2 I HDMI_HotPlug_2 (L) 122 CPLD_TDO O CPLD_Test Data Output 123 GND_B Ground 124 HDMI_HPG3 I HDMI_HotPlug_3 (for temporary insertion) (L) 125 HDMI_SW_EMP O HDMI output wave form adjustment 126 HDMI_PLG_EN O HDMI output control 127 D3.3V Power supply (+3.3V)
Pin No. Pin Name I/O Pin Function
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128 MUTE_HDMI O HDMI_MUTE initial value Low 129 HPLUGOUT_A I HDMI Plug Out detection (H) 130 HDMIKEY_WP O EDIT_Write Protect 131 N_CPLD2_RST O CPLD2 reset 132 PNL_POW O Panel power control 133 HDMI_SW_INT INT HDMI SW IC interrupt request 134 HDELAY_DOUT O HDMI Data Delay Serial_Data_OUTPUT 135 N_MICOM_FLSW O Monitor microprocessor write control 136 N_MICOM_RST O Monitor microprocessor reset control 137 SMPOWHOLD O Power holding signal 138 PM_REQ INT Panel Maicon REQ 139 N_DBOOTS I Microprocessor write request 140 CBOOTS I SD card activation detection 141 D3.3V Power supply (+3.3V) 142 N_DBG_RST I Debagger (Partner) reset 143 N_SRESET I System reset 144 GND_B Ground
Pin No. Pin Name I/O Pin Function
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1.10. IC9602 (VHiMP2367DN-1Y)
1.10.1 Block Diagram
1.10.2 Pin Connections and short description
Pin No. Pin Name I/O Pin Function
1 BS I High-Side Gate Drive Boost Input. BS supplies the drive for the high-side N-Channel MOSFET switch.
Connect a 0.01µF or greater capacitor from SW to BS to power the high side switch.
2 IN I Power Input. IN supplies the power to the IC, as well as the step-down converter switches.
Drive IN with a 4.75V to 28V power source. Bypass IN to GND with a suitably large capacitor to eliminate noise on the input to the IC.
3 SW O Power switching output. SW is the switching node that supplies power to the output. Connect the output LC
filter from SW to the output load. Note that a capacitor is required from SW to BS to power the high-side
switch. 4 GND Ground. 5 FB I Feedback Input. FB senses the output voltage to regulate that voltage. Drive FB with a resistive voltage
divider from the output voltage. The feedback reference voltage is 0.8V. 6 COMP I Compensation Node. COMP is used to compensate the regulation control loop. Connect a series RC net-
work from COMP to GND to compensate the regulation control loop. In same cases, an additional capaci-
tor from COMP to GND is required. 7 EN I Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator,
drive it low to turn it off. 8 SS I Soft-start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND to set the
soft-start period.
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CHAPTER 6. BLOCK DIAGRAM/WIRING DIAGRAM
[1] SYSTEM BLOCK DIAGRAM
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SYSTEM BLOCK DIAGRAM
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[2] TERMINAL BLOCK DIAGRAM
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TERMINAL BLOCK DIAGRAM
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[3] MAIN BLOCK DIAGRAM
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MAIN BLOCK DIAGRAM
PST8424N
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[4] WIRING DIAGRAM
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OVERALL WIRING DIAGRAM
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CHAPTER 7. PRINTED WIRING BOARD
[1] MAIN UNIT PRINTED WIRING BOARD
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MAIN Unit (Side A)
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MAIN Unit (
Chip Parts Side A
)
FL2605
C1502
Q1117
FL2607
C1503
Q1119
L3301
C1505
R2095
L3302
C1506
R2096
L3303
L3304
Q1504
L3305
C1509
Q1506
FL2611
Q1121
D1101
Q1122
D1102
C1126
FL2613
C1128
C1510
R1101
C1511
FL2615
C1512
FL2616
C1513
FL2617
C1514
C1515
C1516
Q1517
Q1519
C1136
C9606
C1137
C9607
C1138
C9608
C1520
C1139
C1521
R1112
R1113
C1523
R1114
C1524
C4404
R1115
D1501
Q4401
C4405
D1502
C4406
C4407
C1527
C1140
D1504
C4408
C1141
C9611
R1501
C4409
R1502
D1506
D1507
R1504
D1508
R1505
D1509
X4501
C9618
C1530
C4410
IC1501IC1502
IC1503
C1533
C4413C4414
R1125 R1126
D1512
IC1507
C4417
R1511
C9622
D1518
C9625
C9628
R1518
C1540
C4420
R1519
SC9301
C4421
FB9702
R1133
R1134
R1135
R9607
IC9601
D1525
X2001
R4401
IC9602
D1526
R4402
IC9603
R1523
D1527
R4403
IC9604
D1528
R4404
IC9605
IC9606
R1526
R4406
R1528
R4408
R1529
R4409
IC4401
R1142
IC4402
IC4403
IC4404IC4405
IC4406
IC4407
R4410
IC4409
R4411
R1532
C9642
R1533
R4413
R1534
R1536
R1537
R4417
R1538
R4418
R4419
C9649
R1154 R1155
FB2001
R9625
FB2002
R1157
R1158
R1540
R4420
R1159
R1541
R4421
FB2006
R4422
FB2007
R1543
R4423
FB2008
R1544
R1545
FB2009
R4425
C9656
C9657
R4427
R1160
R1548
R4428
R1161
R1549
R4429
FB2010
R1164
R1165
FB2011
R1166
P8102
FB2012
FB2013
C9660
R1550
R4430
C9662
R1552
R1553
R4433
C9664
R1554
R4434
R4435
FB2402
FB2403
FB2404
R4439R4440
C9671
R4441
C9672C9673
C9674
C9675
R1565
R1566
R4446
R4447
P3301
C8104C8105 C8106 C8107
C8108
C8109
R1575
R1576
R4456
R1577
R4457
R4458
C8301
R4459
C8302
C8110
C8111
R9667
R4460
R4461
R4464
R4465
R4467
L2601
R4469
L2602
L2603
L2604
C8120
L2605
L2606
L2607
L2608
L2609
D8101
R4471
C8702
D8102
R4472
R1593
R4473
R1594
C8704
R4474
Q8701
C8705
R8101
R4475
Q8702
C8706
R4476
C8707
R4477
L2610
C8708
R4478
L2611
R8105
C8709
R4479
L2612
IC8101
R4480
C8135
R8301
R4481
C8136
R4482
R8302
R8303
R4483
R8304
R8111
C8139
R8112
IC8301
R8116
IC8302
R8117
IC8303
C8140
R8118
IC8304
R8119
P9101
R8310
C3518
R8311
C8146
R8120
D8701
C8149
R8123 R8124
R8701
R3306
R8703
R3307
R3308
R8704
C8150
R8705
IC3301
C8151
C8345C8346
R3501 R3502
IC8702
R3503
IC8703 IC8704
R3311
R8131
R3506
R8132
R3507
R8710
R8135
R3509
IC3501
R8136
IC3502
R8137
R8138
R8714
R8139
R8718
C3539
R3512
R8332
R8333
R8140
R3514
R8141
J1501
R8142
J1502
R3516
R8143
R8144
R8145
P4501 P4502
R8147
R8148
R8149
C3548
R8729
R3521
LUG1101
C9116
C8176
LUG1102
LUG1103
C3357
LUG1104
R3524
LUG1105
C8179
R3525
R8152
R3526
R8153
R3527
R8154
R3528
Q1801
Q1804
C8180
R3530
C8379
R3532
SC1101
R3341
P2001
R3342
P2002 P2003
R9103
R3344
C8380
P2004
R3345
C4501
FB1505
R3539
P2005
C4502
FB1506
R8167
R3347
C4503
FB1507
R3348
FB1508
R8169
IC9101
C3374
R3540 R3541
R3542 R3543
C3377
R1604
FB1510
R3544
C3378
L1101
R9111
R3351
L1102
R3352
R9306
R8172
R9112
R3546
L1103
R8173
R9307
R9113
R3354
R8175
R9116
R9117
P2401
SC1501
R1802
SC1502
FB9603
C8397
SC1503
R1804
SC1504
R9311
R9312
R9313
C3388
R9314
R9120
R3554
C3389
R9121
R9315
R3555
C2001
R9316
R3556
C2002
R9317
R3557
C2003
R9318
R3558
R9125
R9319
Q2001
P2601
Q2002
P2602
R9127
P2603
R9129
C2009
R9320
R3560
R9321
R1622
L1506
R9322
L1507
R9323
R9324
L1508
C2010
L1509
R9131
R9325
C2011
R9132
R9326
R9327
R9133
R4507
R4508
R9328
R4509
IC4501
R9329
R9136
R9138
L1510
L1511
R9139
C2019
L1512
C2402
C2403
L1513
C2404
R9330
R3570
C2405
R3571
C2406
R3572
R4513
C2407
R3573
Q2404
C2408
C2020
R3574
L9601
R9335
R3575
L9602
R9336
R3576
L9603
R9143
R9337
Q2407
R3577
L9604
R9144
R4518
R3578
L9605
L9606
SC4602
D2003
C2027
C2028
C2604
C2410
R9149
C2029
L4401
C2605
R2002
C2609
R2005
R2006
R2007
IC2001
R2009
IC2002
R2011
R2012
R2013
D2401
D2402
D2403
R2017
D2404
R9161
TH2001 R2019
IC2011
R9162
R2405
R2407
R2408
R2020
R2409
D2601
IC2401
IC2402
R2022
IC2403
IC2404
R2601
IC2405
R2602
R2027
R2603
R2604
R2410
R2028
R2606
R2608
R2414
R9174
R2415
R9176
IC2602
R9178
X8101
R9179
R2031
X8102
R2610
R2034
R2611
R2612
R2036
R2613
R2614
R9180
R2038
R2615
R2421
R9181
R9182
R2423
R9183
R2617
R2424
R2618
R2425
R2619
R2426
R2427
R2428
R2429
R2041
R2620
R2044
R2045
R2621
R2430
R2048
R2432
FB8101
R2435
R2436
FB8102
FB8105
R2051
FB8107
R2053
R2054
FB8109
X8701
R2055
R2056
R2057
P1101
P1102
P1103
FB8110
C8232
R2062
C8233
R2063
FL2001
R2069
VA1501
VA1502
FB3303
VA1503
FB3304
VA1504
FB3305
VA1505
FB3306
VA1506
VA1507
VA1508
VA1509
R2075
R2076
R2077
FB3501
C1102
C1103
VA1510
VA1511
VA1512
LUG3503
FB3313
Q1103
VA1513
FB3314
Q1104
VA1514
Q1105
VA1515
Q1106
VA1516
R2082
Q1109
P9601
Q1110
FL2601
FL2603
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MAIN Unit (
Side B
)
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MAIN Unit (
Chip Parts Side B
)
C1118
FL2604
C1119
Q1115
C1501
R2091
Q1116
FL2606
R2092
R2093
Q1118
FL2608
C1504
R2094
Q1501
Q1502
C1507
C1120
C1508
C1121
Q1505
C1122
L3306
C1123
Q1120
C1124
C1125
Q1509
C1127
FL2614
C1129
R1102
R1103
R1104
Q1510
R1105
R1106
R1107
C1517
C1130
R1108
C1131
R1109
C9601
C1132
C9602
Q1516
C1133
C9603
C1134
C9604
C1135
Q9601
C9605
Q9603
R1110
Q9604
R1111
Q9605
C9609
Q9606
C1522
Q9607
Q9608
Q9609
C1525
R1116
C1526
R1117
D1503
C9610
R1118
R1119
C9612
C9613
R1503
Q9610
C9614
C9615
C9616
R1506
C9617
R1507
R1120
R1508
R1121
C9619
C1531
R1509
C4411
R1122
C1532
R1123
C1534
R1124
IC1504
C4415
IC1506
C4416
R1127
D1513
R1128
C9620
C1538
R1510
R1129
C9621
D1515
R1512
C9623
R1513
C9624
R1514
D9601
R1515
D1519
D9602
C9626
R1516
C9627
R1517
D9604
R1130
D9605
R1131
R9601
C9629
R1132
D9606
R9602
R9603
D9607
C1543
R9604
D9608
C1544
D1520
D9609
R9605
C1545
R9606
C1546
R1136
R1137
C1547
C9630
R9608
R1520
C1548
R9609
C9631
R1521
C9632
R1522
C9633
D9610
C9634
R1524
D9611
C9635
R4405
C9636
D9612
R4407
C9637
R1527
C9638
R9610
R9611
C9639
C1551
R9612
R9613
R9614
D1530
R9615
D1531
R9616
R9617
R9618
C9640
R1148
IC4408
C9641
R9619
R1149
C9643
C9644
C9645
R1535
C9646
C9647
R9620
C9648
R1151
R9621
R1539
R1152
R9622
R1153
R9623
R9624
R1156
R9626
R9627
FB2003
C9650
R9628
FB2004
R9629
C9651
FB2005
C9652
R1542
C9653
C9654
R4424
C9655
R4426
C9658
R9630
C9659
R9631
R1162
R9632
R9633
R9634
R9635
R9636
R9637
R9638
C1578
C9661
R9639
C1579
R4431
R4432
C9663
C9665
C9666
R4436
R4437
R1558
C9668
R9640
R4438
R1559
C9669
R9641
R9642
C1582
R9643
C1583
R9644
R9645
R9646
C1586
R9647
C1587
R9648
R1560
R9649
R1561
C1589
R1562
R1563
R1568
FL1501
C1591
R9652
FL1502
C1592
R9653
FL1503
R9654
R9655
C8101
R9656
C8102
C1596
R9657
C8103
C1597
R9658
R1570
R9659
C1599
R1571
R4452 R4453
R4454
R4455
R9660
R9661
R1579
R9662
R9663
C8303
R9664
C8304
R9665
R9666
C8112
C8113
R1580
C8114
C8115
C8116
R4462
C8117
R4463
C8118
C8119
R4466
R4468
C8314
C3301
C8121
C8315
C3302
C8122
C8316
C3303
C8123
C8317
C3304
C8124
C8318
R4470
C3305
C8701
C8125
C8319
C3306
C8126
D8103
C3307
C8703
C8127
D8104
C3308
C8128
C3309
C8129
R1595
R8102
R8103
Q8703
R8104
C8320
C8321
R8106
C8322
C3502
R8107
C3503
C3310
C8130
R8108
C3504
C3311
C8131
R8109
C3505
C3312
C8132
C3506
C3313
C8133
C3507
C8327
C3314
C8134
C8328
C3508
C3315
C8329
C8711
C3316
C8712
C3317
C8137
C8713
C3318
C8138
R4484
C8714
C3319
C8715
R8305
R4485
R4486
R8306
R8307
R8113
C8717
R4487
R8308
R8114
C8718
C8330
R8309
R8115
C8331
C8332
C8333
C3513
C3320
C8334
C3514
C3321
C8141
C3515
C8335
C3322
C8142
C3516
C8336
C3323
C8143
C3517
C8337
C3324
C8144
C8338
C3325
D3301
C8145
C8339
C3326
D3302
D3303
C3327
C8147
C3328
C8148
C3329
R3301
R8121
R3302
R8122
R3303
R3304
C8340
C3520
R3305
R8125
C8341
C3521
R8702
R8126
C3522
C8342
R8127
C3523
C8343
C3330
R8128
C8344
C3524
R3309
C3331
R8129
C3525
C3332
C8152
R8706
C3526
C3333
C8153
C8347
C3334
C8154
C8348
C3335
C8155
IC8701
C8349
C3336
C8156
C3337
C8157
C3338
R3310
C8158
R8130
C3339
C8159
R3312
R8133
R3314
C8350
R3315
C3531
C8351
R3316
R8712
C3532
C8352
R3317
C8353
C3533
R8713
R3318
C3340
C8160
C8354
C3534
C3341
R3319
C9101
C8161
C8355
C3535
C3342
C8162
C8356
C3343
C8163
C3537
C8357
C9104
C3344
C8164
C3538
C8358
R3511
C3345
C9105
C8165
Q9101
C8359
C9106
C3346
C8166
Q9102
C3347
R3513
C8167
C9107
C3348
R3320
C8168
C9108
C3349
R3321
C8169
C9109
R3322
R3323
C3540
C8360
R3325
C3541
C9301
C8361
R8146
R8722
C3542
C8362
R3327
R8723
C8363
C3543
R3328
C3350
C8170
C9110
C8364
C3544
FB1101
R3329
C3351
C8171
C9111
C3545
C8365
FB1102
C3352
C8172
C9112
C8366
C3546
FB1103
C3353
C8173
C9113
C3547
C8367
FB1104
C3354
R8728
C8174
C1608
C9114
C8368
FB1105
C3355
C8175
C9115
C8369
C3356
C8177
C9117
R3330
C3358
R8150
C8178
C3359
C1801
R3331
R8151
C1802
R3332
C1803
R3333
C1804
R3334
C8370
R8730
R3335
R8155
C8371
Q1802
R3336
R8156
C8372
R3337
Q1803
R8157
C1613
C8373
C3360
R3338
C1614
R8158
C8374
C3361
R3339
R8159
C8181
C1615
C8375
C3362
C8182
C1616
C8376
C3363
C8183
C8377
C3364
C8184
C8378
Q1808
C3365
D9101
C8185
Q1809
C3366
C8186
C3367
C8187
C3368
R3340
C8188
R8160
C3369
C8189
R8161
FB1501
R9101
R9102
R8162
FB1502
C1813
R3343
R8163
FB1503
R9104
R8164
FB1504
R8165
R9105
C8381
C1816
R3346
R8166
R9106
C8382
R9107
C8383
C3370
C8190
R9108
C8384
C3371
C8191
R3349
R9109
FB1509
C8385
C3372
C8192
C8386
C3373
C8193
C8387
C8194
IC9104
C8388
C3375
R9301
C8195
IC9105
R1601
C8389
C3376
C8196
R9302
IC9106
C8197
R9303
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C3384
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C3385
C3386
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R9123
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C2004
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C2006 C2007
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C3391
C3392
C3393
C3394
C3395
C3396
C3397
R1817
C3398
R9130
C3399
R1819
C2012
C2013
R9134
C2014
R9135
C2015
C2016
R9137
C2017
R1820
C2018
C2401
R9331
R4511
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R9151
R9152
R9153
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R9156
IC2006
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R9158
R2010
IC2008
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R2402
R9163
R2403
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