SHARP L6384, L6385, L6386, L6387 Diagram

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

APPLICATION NOTE

L6384, L6385, L6386 & L6387

APPLICATIONGUIDE

by F. Sandrini, U. Moriconi

The ST L638X is a versatilehigh voltage gate driverfamily. Realised in BCD Off-line technology, these devices are able to operate with high voltage rails up to

600V. The Gate Drivers provide all the functions and current capability necessary for high side and low side Power MOS and IGBT.

L6384-5-6-7are High VoltageDrivers for High and Low Side. Thesedevices can be used in all the applications where high voltage shifted control is necessary.These devices have a fairly high driver current capability and they are also providedwith an internal patentedcircuitry which replaces the externalbootstrap diode. This feature is achieved by means of a high voltage DMOS, synchronouslydriven with the low side gate driver.

The L6384 (Internal diagram in fig. 1) is a half bridge driver with externally adjustable dead-time and shut down function. To disable the driver, the control pin (DT/SD at pin3) must be pulled down below

0.5V. The dead time can be set from 0.5µs to 2.7µs by a simpleresistor between pin3 and ground. Available in Minidip and SO8 packages, this driver can be used in motor controls, resonant converters and lighting applications. In fig. 2 the schematic diagram of the evaluation circuit and the layout of the test PCB are shown.

L6384 PIN DESCRIPTION

N. Name Type Function

1 IN(*) I Logic Input: it is in phasewith HVG and in opposition of phase with LVG. It is

3 DT/SD I High impedence pin with two functionalities. When pulled to a voltage lower thanV

4 GND Ground 5 LVG O Low side driver output: the output stage can deliver 400mA source and 650mA sink

6 Vout O Upperdriver floating reference: layout care has to be taken to avoid undervoltage

compatible to Vcc voltage.

I Supply input voltage: there is an internal clamp [Typ. 15.6V]

There is also an UVLO feature ( Typ. Vcc

[Typ.0.5V] the device is shut down. A voltage higher than Vdtsets the dead time between high side and low side gate driver. The dead time value can be set forcing a certain voltage level on the pin or connectinga resistorbetween pin 3 and ground. Care must be taken toavoid spikes on pin 3 that can cause undesired shut down of the IC. For this reason the connection of the components between pin 3 and ground has to beas shortas possible. This pin can not be letfloating forthe same reason. The pin has not to be pulled through a low impedence to Vcc, because of the drop on the corrent source that feeds Rdt. The operativerange is:V a dt range of 0.4 - 3.1µs.

[Typ. Values]. The circuit guarantees 0.3V max on the pin(@I than the turn on threshold.This allows to omit the bleeder resistor connected between the gate and the the source of the external mosfet normallyused to hold the pin low; the gate driver ensures low impedence also in SD conditions.

spikes on this pin

= 12V, Vcc

th1

= 10V).

th2

... 270K ⋅ Idt, that allows

= 10mA) with Vcc> 3V and lower

sink

June 2002

1/17

AN994 APPLICATIONNOTE

L6384 PIN DESCRIPTION(continued)

N. Name Type Function

7 HVG O Highside driver output:the output stage can deliver 400mA source and 650mA sink

(*) The pull-down internal resistor is typically some hundreds Kohm.

boot

Figure 1. L6384 Internal Block Diagram.

[Typ. Values]. The circuit guarantees 0.3V max between this pinand Vout (@I

= 10mA) with Vcc>

sink

3V and lower than the turn on threshold.This allows to omit the bleeder resistor connected betweenthe gate and the the sourceof the external mosfet normally used to hold the pin low; the gate driver ensures low impedence also in SD conditions.

Bootstrap Supply Voltage: it is the upper driver floatingsupply. The bootstrap capacitor connected between this pin and pin 6 can be fed by an internal structure named ”bootstrap driver” (a patentedstructure). This structure can replace the external bootstrap diode.

BOOT

BOOTSTRAP DRIVER

H.V.

DETECTION

DT/SD

Idt

DEAD

TIME

Vthi

LOGIC

LEVEL

SHIFTER

LSG

DRIVER

Figure 2. L6384 Schematicdiagramof the evaluationcircuit.

CN1

DT/DS

GNDC2C1

L6384

HVG

VBOOT

OUT

LVG C7

HVG

DRIVER

HVG

OUT

LVG

GND

D97IN518A

R4 R5

W1 W2

BOOT

LOAD

CN3

CN2

2/17

R7 R6

D98IN829

Figure 2a. L6384 - PCB and componentlayoutof the fig. 2.

94mm

AN994 APPLICATIONNOTE

50mm

Silk

Comp. Layer

Back Layer

3/17

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The L6385 (Internal diagram in fig. 3) is a high and low side configurable driver. In fact, it is possible to control two separate inputs, thus the outputs can be switched independently. This device is provided with undervoltagedetection in both low voltage side and high voltage bootstrapped supply. Delivered in 8pin packages, this driver has been especiallydesigned for power supplies and motion control application. Fig. 4 shows the schematicdiagram of the evaluationcircuitand the layoutof the relevantPCB.

L6385 PIN DESCRIPTION

N. Name Type Function

1 LIN (*) I Low Side Driver Logic Input: it is compatible to Vcc voltage. 2 HIN (*) I High Side Driver Logic Input: it is compatible to Vcc voltage. 3V

4 GND Ground 5 LVG O Low Side Driver Output: the output stage can deliver 400mA source and 650mAsink

6 Vout O Upper Driver Floating Reference: layout care has to be taken to avoid undervoltage 7 HVG O High Side Driver Output: the output stage can deliver 400mA source and 650mA sink

8 Vboot BootstrapSupply Voltage:it is the upper driver floating supply [with UVLO: typ. V

(*) The pull-down internal resistor is typically some hundreds Kohm.

Figure 3. L6385 Internal Block Diagram.

= 1.5V, V

il Max

= 1.5V, V

il Max

I Supply input voltage with UVLO ( Typ. V

ih Min

= 3.6V] = 3.6V]

ccth1

= 9.6V, V

ccth2

= 8.3V).

[Typ.Values]. Thecircuit guarantees 0.3V max on the pin (@I

= 10mA) with Vcc> 3V and lower

sink

thanthe turn on threshold. This allows to omit the bleeder resistor connected between thegate and the the source of the external mosfet normally used to hold the pin low.

spikes on this pin. [Typ.Values].

Thecircuit guarantees 0.3V max between this pin and V

out

(@ I

= 10mA) with Vcc>

sink

3Vand lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the the source of the external mosfet normallyused to hold the pin low.

= 9.5V, V

= 8.2V]. The bootstrapcapacitor connected between this pin and pin 6

BSth2

canbe fed by an internal structure named ”bootstrap driver” (a patented structure). Thisstructure can replace the external bootstrap diode.

BSth1

BOOTSTRAP DRIVER

HIN

LIN

DETECTION

LOGIC

DETECTION

LEVEL

SHIFTER

R R S

LVG

DRIVER

Figure 4. L6385 Schematicdiagramof the evaluationcircuit.

CN1

LIN

HIN

L6385

GNDC2C1

HVG

VBOOT

VOUT

LVG

D98IN830

HVG

DRIVER

D97IN514B

Vboot

Cboot

H.V.

HVG

OUT

LVG

GND

+HV

TO LOAD

CN3

CN2

CN4

4/17

Figure 5a. L6385 - PCB and componentlayoutof the fig. 5.

80mm

AN994 APPLICATIONNOTE

50mm

Silk

Comp. Layer

Back Layer

5/17

AN994 APPLICATIONNOTE

L6386 (Internal diagram in fig. 5). Configurable driver, the L6386 is based on the L6385 structure with

added functions.Thisdevice is availablein DIP14or SO14. The added Shutdown function (active low) and the Current Sense Comparator (0.5V threshold) with Diagnostic Output, make this device particularly suitable for motion control with cycle-by-cycle current feedback.DIAG and CIN pins can be used to stop the device (e.g. acting on SD pin). Fig. 6 shows the schematic diagramof theevaluationcircuit and the layout of therelevantPCB.

L6386 PIN DESCRIPTION

N. Name Type Function

1 LIN (*) I Lower Driver Logic Input: it is compatible to Vcc voltage. [V 2 SD (*) I Shut Down Logic Input: it is compatible to Vcc voltage. If it has to be pulled up the

suggested resistorvalue is 5-10Kohm. [V 3 HIN (*) I Low SideDriverLogic Input:it is compatibletoV 4V

I Low SideDriverLogic Input:it is compatibletoVccvoltage.[V

il Max

= 1.5V, V

voltage.[V

ih Min

5 DIAG O Diagnostic Output: Open Drain 6 CIN I Comparator Input 7 SGND Ground reference for logic signals 8 PGND Power Ground reference for the Low Voltage Gate Driver 9 LVG O Low Side Driver Output: Low side driver output: the outputstage can deliver 400mA

source and 650mA sink [Typ. Values].

The circuit guarantees 0.3V max on the pin(@ I

= 10mA) with VCC> 3V and lower

sink

than the turn on threshold.This allows to omit the bleeder resistor connected between

the gate and the the source of the external mosfet normallyused to hold the pin low;

the gate driver ensures low impedence also in SD conditions.

10, 11 N.C. NotConnected

il Max

= 3.6V]

il Max

ilMax

= 1.5V, V

= 1.5V,V

ihMin

ih Min

ihMin

= 3.6V]

12 V

out

O Upper Driver Floating Driver: layout care has to be taken to avoid undervoltage spikes

on this pin

13 HVG O High Side Driver Output: High side driver output:the output stage can deliver 400mA

ource and 650mA sink [Typ.

Values] The circuit guarantees 0.3V max between this pin and Vout (@ I

with V

> 3V and lower than the turnon threshold. This allows to omit the bleeder

sink

resistor connectedbetween the gate and the the source of the external mosfet

normally used to hold the pin low; the gate driver ensures low impedence also in SD

conditions.

14 Vboot Bootstrapped Supply Voltage: Bootstrap supply voltage: it is the upper driver floating

supply [with UVLO: Typ. V

= 11.9V, V

Bth1

Bth2

= 9.9V]. The bootstrap capacitor connected between thispin and pin 6 can be fed by an internal structure named ”bootstrap driver” (a patented structure). This structure can replace theexternal bootstrap diode.

(*) The pull-down internal resistor is typically some hundreds Kohm.

= 10mA)

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