SHARP JE400D3HC2N Specification

PREPARED BY: DATE

LIQUID CRYSTAL DISPLAY GROUP

Sakai Display Products Corporation

SPEC No. FILE No. ISSUE : Dec, 20, 2012 APPROVED BY: DATE PAGE :

LD-K24Z07

SPECIFICATION

 CUSTOMER'S APPROVAL

DATE

BY BY     

MODEL No.

DEVICE SPECIFICATION FOR

TFT-LCD Open Cell

JE400D3HC2N

PRESENTED

K.Kobayashi

Center General Manager Technology Center Liquid Crystal Display Business Group Sakai Display Products Corporation

Sakai Display Products Corporation

RECORDS OF REVISION



MODEL No. : JE400D3HC2N SPEC No. : LD-K24Z07

SPEC No. DATE

LD-K24Z07 2012/12/20

REVISED

No.

- - - 1st ISSUE

PAGE SUMMARY NOTE

LD-K24Z07-1

1 Application

This specification applies to the color 40.0” TFT-LCD Open Cell JE400D3HC2N.

With parts (S-Dr, G-Dr, S-PWB) to drive it.）

（

* This specification sheets are proprietary products of Sakai Display Products Corporation (“SDP”) and include

materials protected under copyright of SDP. Do not reproduce or cause any third party to reproduce them in any form or by any means, electronic or mechanical, for any purpose, in whole or in part, without the express written permission of SDP.

* In case of using the device for applications such as control and safety equipment for transportation (aircraft, trains,

automobiles, etc.), rescue and security equipment and various safety related equipment which require higher reliability and safety, take into consideration that appropriate measures such as fail-safe functions and redundant system design should be taken.

* Do not use the device for equipment that requires an extreme level of reliability, such as aerospace applications,

telecommunication equipment (trunk lines), nuclear power control equipment and medical or other equipment for life support.

* SDP assumes no responsibility for any damage resulting from the use of the device that does not comply with the

instructions and the precautions specified in these specification.

* Contact and consult with the SDP sales representative for any questions about this device.

2 Overview

This Open Cell (JE400D3HC2N) is a color active matrix LCD PANEL incorporating amorphous silicon TFT (Thin Film Transistor), Polarizers, Source-PWBs, Source-Drivers, Gate-Drivers and Control-PWB(C-PWB). The following content can be achieved in using C-PWB (JE0DZ1C0010) that SDP specifies.

Graphics and texts can be displayed on a 1920×RGB×1080 dots panel with one billion colors by using 10bit LVDS (Low Voltage Differential Signaling) to interface, +12V of DC supply voltages.

In order to improve the response time of LCD, This C-PWB applies the Over Shoot driving (O/S driving) technology for the control circuit. In the O/S driving technology, signals are being applied to the Liquid Crystal according to a pre-fixed process as an image signal of the present frame when a difference is found between image signal of the previous frame and that of the current frame after comparing them.

With combination of this technologies, motion blur can be reduced and clearer display performance can be realized. [Caution] You should design thermal conductive interface pad and C-PWB cover enough to radiate heat from T-CON IC in C-PWB.

TFT LCD Panel

(1920 x RGB x 1080)

Fig.1 Overview of Open-Cell: JE400D3HC2N and C-PWB

Open Cell

Open CellOpen Cell ((((JE400D3HC2N

JE400D3HC2N))))

JE400D3HC2NJE400D3HC2N

Gate Driver Source Driver

CN2

CN1

FFC (not attached)

CN3

CN1

1111

55551111

Control

Control----PW

ControlControl

PWB (JE0DZ1C0010)

PWPW

Source PWB (S-PWB)

B (JE0DZ1C0010)

B (JE0DZ1C0010)B (JE0DZ1C0010)

Pin No.

Symbol

Function

Remark

1

GND

2

Reserved

It is required to set non

-

connection(OPEN)

3

Reserved

It is required to set non

-

connection(OPEN)

4

Reserved

It is required to set non

-

connection(OPEN)

5

Reserved

It

is required to set non

-

connection(OPEN)

6

Reserved

It is required to set non

-

connection(OPEN)

7

SELLVDS

Select LVDS data order

[Note

1,2]

Pull

down

8

Reserved

It is required to set non

-

connection(OPEN)

9

Reserved

It is required to set non

-

connection

(OPEN)

10

Reserved

It is required to set non

-

connection(OPEN)

11 GND

12

AIN0

- Aport (

-

)LVDS CH0 differential data input

13

AIN0+

Aport (+)LVDS CH0 differential data input

14

AIN1

- Aport (

-

)LVDS CH1 differential data input

15

AIN1+

Aport (+)LV

DS CH1 differential data input

16

AIN2

- Aport (

-

)LVDS CH2 differential data input

17

AIN2+

Aport (+)LVDS CH2 differential data input

18

GND

19

ACK

- Aport LVDS Clock signal(

-)

20

ACK+

Aport LVDS Clock signal(+)

21

GND

22

AIN3

- Aport (

-

)LVDS

CH3 differential data input

23

AIN3+

Aport (+)LVDS CH3 differential data input

24

AIN4

- Aport (

-

)LVDS CH4 differential data input

25

AIN4+

Aport (+)LVDS CH4 differential data input

26

GND

27

GND

28

BIN0

- Bport (

-

)LVDS CH0 differential data in

put

29

BIN0+

Bport (+)LVDS CH0 differential data input

30

BIN1

- Bport (

-

)LVDS CH1 differential data input

3 Mechanical Specifications

Parameter Specifications Unit

Display size

Active area 885.60(H) x 498.15 (V) mm Pixel Format Pixel pitch 0.46125 (H) x 0.46125 (V) mm

Pixel configuration R, G, B vertical stripe Display mode Normally black Cell Outline Dimensions[Note1] 921.18 (H) x 541.25(V) x 1.66(D) mm Mass 1.72+0.3 kg

Surface treatment [Note2] Underside Surface

treatment [Note2] [Note1] Outline dimensions are shown in P20. Dimension "D" does not include the parts on S-PWB. [Note2] With the protection film removed.

101.61 （Diagonal）

40.00 （Diagonal）

1920(H) x 1080(V)

1pixel = R + G + B dot）

（

Anti Glare Hard coating : 2H and more

Hard coat less

4 Cell Driving Specifications

4.1 Driving interface of Control PWB SDP specifies

Parts code: JE0DZ1C0010 CN1 (Interface signals and +12V DC power supply) shown in Fig.1

Using connector : 91213-0510 (Aces Electronics Co., Ltd.) Matching connector : FI-RE51HL, FI-RE51CL (Japan Aviation Electronics Ind., Ltd.) or equivalent device Matching LVDS transmitter : THC63LVD1023 or equivalent device

LD-K24Z07-2

cm

inch

pixel

31

BIN1+

Bport (+)LVDS CH1 differential data input

32

BIN2

- Bport (

-

)LVDS CH2 differential data input

33

BIN2+

Bport (+)LVDS CH2 differentia

l data input

34

GND

35

BCK

- Bport LVDS Clock signal(

-)

36

BCK+

Bport LVDS Clock signal(+)

37

GND

38

BIN3

- Bport (

-

)LVDS CH3 differential data input

39

BIN3+

Bport (+)LVDS CH3 differential data input

40

BIN4

- Bport (

-

)LVDS CH4 differential d

ata input

41

BIN4+

Bport (+)LVDS CH4 differential data input

42

GND

43

GND

44

GND

45

GND

46

GND

47

VCC

+12V Power Supply

48

VCC

+12V Power Supply

49

VCC

+12V Power Supply

50

VCC

+12V Power Supply

51

VCC

+12V Power Supply

[Note] You should connect GND plane in Control PWB to module chassis.

[Note 1] The equivalent circuit figure of the terminal:

Terminal

LD-K24Z07-3

4.7KΩ

Control PWB

LD-K24Z07-4

[Note 2] LVDS Data order

SELLVDS

Data L(GND) or Open

[VESA] TA0 TA1 TA2 TA3 TA4 TA5 TA6

TB0 TB1 TB2 TB3 TB4 TB5 TB6 TC0 TC1 TC2 TC3 TC4 NA NA TC5 NA NA TC6 DE(*) DE(*) TD0 TD1 TD2 TD3 TD4 TD5 TD6

TE0 TE1 TE2 TE3 TE4 TE5 TE6

NA: Not Available (*)Since the display position is prescribed by the rise of DE(Display Enable)signal, please do not fix DE signal at ”High” during operation. And you should input DE signal in all LVDS port.

R0(LSB) R1 R2 R3 R4 R5 G0(LSB) G1 G2 G3 G4 G5 B0(LSB) B1 B2 B3 B4 B5

R6 R7 G6 G7 B6 B7

N/A

R8 R9(MSB) G8 G9(MSB) B8 B9(MSB)

N/A

H(3.3V)

[JEIDA] R4 R5 R6 R7 R8 R9(MSB) G4 G5 G6 G7 G8 G9(MSB) B4 B5 B6 B7 B8 B9(MSB)

R2 R3 G2 G3 B2 B3 N/A R0(LSB) R1 G0(LSB) G1 B0(LSB) B1 N/A

SELLVDS= Low (GND) or OPEN：：：：VESA

ACK+,BCK+

ACK– ,BCK

AIN0+,BIN0+

AIN0–,BIN0

AIN1+,BIN1+

AIN1–,BIN1

–

G0 R5 R4 R3 R2 R1 R0 R0 R1 G0

B1 B0 G5 G4 G3 G2 G1 G1 G2 B1

AIN2+,BIN2+

AIN2–,BIN2

AIN3+,BIN3+

AIN3–,BIN3

–

DE

AIN4+,BIN4+ AIN4–,BIN4

–

SELLVDS= High (3.3V)：：：：JEIDA

ACK+,BCK+

ACK– ,BCK

AIN0+,BIN0+

AIN0–,BIN0

AIN1+,BIN1+ AIN1–,BIN1

AIN2+,BIN2+ AIN2–,BIN2

AIN3+,BIN3+

AIN3–,BIN3

AIN4+,BIN4+ AIN4

–

,BIN4

–

G4 R9 R8 R7 R6 R5 R4 R4 R5 G4

B5 B4 G9 G8 G7 G6 G5 G5 G6 B5

DE

–

DE: Display Enable, NA: Not Available (Fixed Low)

NA NA

B7 B6 G7 G6 R7 R6 R6 R7 NA NA

B9 B8 G9 G8 R9 R8 R8 R9 NA NA

NA NA

B3 B2 G3 G2 R3 R2 R2 R3 NA NA

B1 B0 G1 G0 R1 R0 R0 R1 NA NA

1 cycle

B5 B4 B3 B2 B2 B3

1 cycle

B9 B8 B7 B6 B6 B7

LD-K24Z07-5

DE

INPUT SIGNALS

GATE DRIVER

SOURCE

DRIVER

CN4

SOURCE

PWB SOURCE

PWB

INPUT SIGNALS

I2C SCL

4.2

Interface block diagram

4.24.2

SELLVDS AIN0- AIN0+ AIN1- AIN1+ AIN2- AIN2+ AIN3- AIN3+ AIN4- AIN4+ ACK- ACK+ BIN0- BIN0+ BIN1- BIN1+ BIN2- BIN2+ BIN3- BIN3+ BIN4- BIN4+ BCK- BCK+

POWER SUPPLY

+12V DC

4.3

Display position of data

4.34.3

LCD PANEL

1920×3(RGB)×1080

GATE DRIVER

Signals &

Power Supply

Signals &

Power Supply

C-PWB

CN1

Fig.2 Interface block diagram

LD-K24Z07-6

I2C SDA

B1 G1 R1 B2 G2 R2

(1,1) (1,2)

1,1 1,2 1,3

2,1 2,2

3,1

B G R

1080,1

S-PWB S-PWB

1,1920

1080,1920

[Note] You should assemble Open-Cell for S-PWBs to be located at the downside of your TV set.