Sharp IR3Y48M Datasheet
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1
DESCRIPTION
The IR3Y48M is a CMOS single-chip signal
processing IC for CCD area sensors which includes
correlated double sampling circuit (CDS), clamp
circuit, automatic gain control amplifier (AGC),
reference voltage generator, black level detection
circuit, 20 MHz 10-bit analog-to-digital converter
(ADC), timing circuit for internally required pulses,
and serial interface for internal circuits.
FEATURES
• Low power consumption :
110 mW (TYP.) at 20 MHz mode
• Wide AGC range : 0 to 36 dB
(Gain step : 0.094 dB/step)
• High speed sample-and-hold circuits :
pulse width 10 ns (MIN.)
• Power save operation :
84 mW (TYP.) at 15 MHz mode
• Standby mode : less than 0.3 mW
• Built-in serial interface
• 10-bit ADC operating up to 20 MHz
– Non-linearity
DNL : 0.6 LSB (TYP.)
INL : 1.5 LSB (TYP.)
• Maximum input level of CCD signals : 1.1 Vp-p
• Accepts a direct signal input to ADC or AGC
(input level : 1 Vp-p (TYP.))
• Single +3 V power supply
• Package :
48-pin QFP (QFP048-P-0707) 0.5 mm pin-pitch
PIN CONNECTIONS
IR3Y48M
CCD Signal Process & Digital Interface IC
IR3Y48M
1
48 47 4645 44 434241 40 39 37
13 14 1516 17 1819 20 2122 23 24
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
NC
AV
DD4
NC
V
RN
VRP
AVDD2
AVDD2
AVSS2
AVSS2
VCOM
CCDIN
REFIN
OP
RESETN
AVDD3
AVSS3
STBYN
CSN
SDATA
SCK
OBP
CCDCLP
BLK
ADCLP
CLPCAP
ADIN
OBCAP
MONOUT
NC
AISET
AV
DD1
AVSS1
NC
ADCK
SHR
SHD
DO
9
DO8
DO7
DO6
DO5
DVDD
DVSS
DO4
DO3
DO2
DO1
DO0
38
48-PIN QFP
TOP VIEW
(QFP048-P-0707)
IR3Y48M
2
BLOCK DIAGRAM
13
12
CCD
ADIN
ADCLP
CCDCLP
6 dB/STEP
(0 to 12 dB)
S/H
OBCAP
AISET
ADCK
11
14
15
18
22
26 28 27 25 31 29 30 36 35
32
BLK OBP CCDCLP
TIMING
GENERATOR
SERIAL
REGISTER
REGISTER (7-BIT)
COMPARE
10-BIT
ADC
OBP
0.094 dB/STEP
(0 to 6 dB)
6 dB/STEP
(0 to 18 dB)
AGC
ROUGH
AGC
FINE
DAC
ADCLP CSN SCK SDATA OP RESETN STBYN
42
43
33
20
2
34
19
4
10
5
6,7
8,9
DVSS
DVDD
AVSS3
AVSS2
AVSS1
AVDD4
AVDD3
AVDD2
AVDD1
VRN
VCOM
BANDGAP
V
REF
VRP
DO0 to DO9
37 to 41, 44 to 48
MONOUT
16
SHD
24
SHR
CLPCAP
DC
REFIN
CCDIN
CLAMP
CLPCAP
23
CDS
+
IR3Y48M
3
PIN DESCRIPTION
1NC
–
No connection.
PIN NO.
SYMBOL I/O
EQUIVALENT CIRCUIT DESCRIPTION
Supply of 2.7 to 3.6 V analog power.
–AV
DD4
2
3
NC –
No connection.
VDD
GND
◊
ADC internal negative reference
voltage.
(Connect to AV
SS via 0.1 µF.)
OV
RN
4
Supply of 2.7 to 3.6 V analog power.
–AV
DD2
6
5
V
RP O
9
AV
SS2 –
An analog grounding pin.
8
AVSS2 –
An analog grounding pin.
7
AV
DD2 –
Supply of 2.7 to 3.6 V analog power.
ADC internal common reference
voltage.
(Connect to AV
SS via 0.1 µF.)
OV
COM
10
11
CCDIN I
CDS circuit data input.
IREFIN
12
ADC internal positive reference
voltage.
(Connect to AV
SS via 0.1 µF.)
CDS circuit reference input.
VDD
GND
◊
10
VDD
GND
◊
Clamp level output.
(Connect to AV
SS via 0.1 µF.)
OCLPCAP
13
14
15
16
◊ Internal gate
ADIN
OBCAP
MONOUT
I
O
O
ADIN signal input.
Black level integration voltage.
(Connect to AV
SS via 0.033 µF.)
Monitor output of CDS or AGC.
VDD
GND
◊
4
IR3Y48M
PIN NO.
SYMBOL I/O
EQUIVALENT CIRCUIT DESCRIPTION
–NC
17 No connection.
Internal analog circuit bias input.
(Connect to AV
SS via 4.7 k$.)
18
AISET I
No connection.21
NC –
An analog grounding pin.
33
AV
SS3 –
An analog grounding pin.20
AV
SS1 –
Supply of 2.7 to 3.6 V analog power.19
AVDD1 –
IADCK
22 ADC sampling clock input.
Reference sampling pulse input.
Data sampling pulse input.
Clamp and black calibration control
for ADIN signal.
Blanking pulse input.
Clamp control input.
Black level period pulse input.
Serial port clock input.
Serial port data input.
Serial port chip selection (active at low).
Standby control (standby at low).
23
24
25
26
27
28
29
30
31
32
SHR
SHD
ADCLP
BLK
CCDCLP
OBP
SCK
SDATA
CSN
STBYN
I
I
I
I
I
I
I
I
I
I
–AV
DD3
34 Supply of 2.7 to 3.6 V analog power.
VDD
GND
◊
18
VDD
GND
◊ Internal gate
Serial I/F operation code enable pin
(active at low).
36
OP I
Reset signal input (reset at low).
35
RESETN I
VDD
GND
IR3Y48M
5
PIN NO.
SYMBOL I/O
EQUIVALENT CIRCUIT DESCRIPTION
ODO
0
37
ADC digital output (LSB).
(Capable of High-Z)
VDD
GND
41
DO
4 O
ADC digital output.
(Capable of High-Z)
40
DO
3 O
ADC digital output.
(Capable of High-Z)
39
DO
2 O
ADC digital output.
(Capable of High-Z)
38
DO
1 O
ADC digital output.
(Capable of High-Z)
43
DV
DD –
Digital output driver power supply.
(2.7 to 3.6 V)
42
DV
SS –
Digital output driver GND. A digital
grounding pin.
ADC digital output (MSB).
(Capable of High-Z)
ODO
9
48
ADC digital output.
(Capable of High-Z)
ODO
8
47
ADC digital output.
(Capable of High-Z)
ODO
7
46
ADC digital output.
(Capable of High-Z)
ODO
6
45
ADC digital output.
(Capable of High-Z)
ODO
5
44
VDD
GND
NOTES :
• NC pins are recommended to be connected to AVSS on PCB even they are not connected electrically in the chip.
• High-Z at standby.
IR3Y48M
6
FUNCTIONAL DESCRIPTION
Outline
The configuration of IR3Y48M is described below.
SHR SHD
MONOUT
V
REF
Clamp
CDS
REFIN
CCDIN
ADIN
ADCK
BLK
OBP
CCDCLP ADCLP
CSN
SDATASCK
CCD
AGC
DO
0 toDO9
Black
Control
Serial
Register
Timing
Generator
IR3Y48M
+
10-bit
ADC
CCD
OB Effective Pixel (OB) Blanking
ADCK
BLK
OBP
CCDCLP
Data Output Black Code
DO
0-DO9
GENERAL TIMING
7
IR3Y48M
Reference Clock (SHR)
Data Clock (SHD)
REFIN
CCDINCCD
CDS
CDS Output
= V (CDS)
= V (DAT) – V (PREC)
Reset
Pulse
Reset
Pulse
V (PREC)
V (DAT)
MAX. Level
SHR
SHR
SHD
SHD
SIG
fSMAX = 20 MHz/tSMIN = 50 ns
SIG
V (CDS)
CDS Operation
CDS Circuit
CDS circuit holds CCD precharge (reference) level
at SHR pulse, then it samples CCD pixel data at
SHD pulse. Correlated (common) noise is removed
by subtraction of precharge level from pixel data
level.
CDS has the gain of maximum 12 dB (6 dB/step).
This gain is a part of total gain and it is controlled
by register value similar to gain in AGC circuit.
Connect signal from CCD sensor to CCDIN pin
through C-coupling. Place the same capacitor
between REFIN and AV
SS.
8
IR3Y48M
Clamp Circuit
DC CLAMP
DC level of the analog input is fixed by internal DC
clamp circuit. DC level of C-coupled CCD signal at
CDS input is set to CLPCAP by DC clamping.
Normally clamp switch is turned on at black level
calibration period. Place 0.1 µF external
capacitance between CLPCAP and AV
SS.
Timing Control
(Register Conditions)
REFIN
CCDIN
SHR SHD CCDCLP
Clamp
Source
CLPCAP
DC Clamp Function
(CCDCLP)
CLPCAP
CCDCLP
ADCK
CCD
CLPCAP Level
REFIN, CCDIN
Clamp Level
Clamp Timing
CLAMP OF ADIN SIGNAL
Clamp operation for ADIN path is also available.
Note that clamp voltage [CLPCAP] is different
between CCD input and ADIN.
ADCLP signal is used for both clamp and black
level control at ADIN input mode. It is also possible
to turn off clamp operation by register setting.
CLAMP CONTROL
Following items are selectable through register
setting.
a) Clamp current
Normal or fast clamp is selectable for charge
current. (Select normal clamp in general)
b) Clamp target
Input signal (REFIN and CCDIN) to be
clamped is selectable. It is also possible to turn
off the clamp function.
ADCLP
ADIN
To AGC
or
To ADC
Timing Control
CLPCAP
(ADCLP)
ADIN DC Clamp Function
9
IR3Y48M
CDS
REFIN
S/H
CCDIN
ADIN
(Path for ADIN)
ADCLP
ADCLPOBP
OBP
Compare
Register (7-bit)
OBCAP
Rough Fine
DO
0-DO9
AGC AGC
+
DAC
10-bit
ADC
Black Level Calibration
CCD
ADCK
OBP
OBCAP
Previous
Black Level
Blanking Blanking
Effective
Pixel Signal
Effective
Pixel Signal
Optical Black Period
Resulting Black
Calibration Level
(Hold)
Black Level Calibration Timing
Black Level Cancel Circuit
The purpose of black level cancel is to adjust the
AGC input level which can equalize the ADC output
code to black level code written in the register. The
black level cancelling is generally done during OB
(optical black period) pulsed by OBP pulse. The
register value ((1 to) 16 to 127 LSB : default 64
LSB) is written by serial interface.
Black level cancel loop is established while OBP is
low (when pulse is not inverted).
In this loop, ADC output code is compared with
register setting. During OB period, the OBP voltage
gradually terminates into certain voltage resulting
the output code equal to the register setting.
The OBP voltage is discharged under following
status :
q Set black level reset register to 1
w Set RESET pin low
e Power down (by STBYN or register control)
The period to reach the final value depends on the
status of chip. It may take more than one thousand
pixels at start-up or after reset. It may take only
several pixels when the status is not changed. DC
clamp [CCDCLP] is allowed during OBP low.
Black level cancelling for ADIN signal (broken line
in the chart) is controlled by ADCLP pulse (clamp
and OB control are done simultaneously) instead of
OBP.
10
IR3Y48M
Gain Control Circuit
The total gain for CCD input signal covers from 0 to
36 dB.
This range consists of CDS (0 to 12 dB (6 dB/
step)), AGC rough (0 to 18 dB (6 dB/step)), and
AGC fine (0 to 6 dB (0.094 dB/step)). Total gain is
controlled (as described below) by 9-bit gain control
register. The gain is fixed to maximum gain when
the code exceeds 382 (decimal).
The gain of ADIN (which bypassing CDS) is 0 to
24 dB.
0D
0 dB
35.91 dB
0.094 dB
1 step
383D
CDS
6 dB/step
(0 to 12 dB)
Rough
6 dB/step
(0 to 18 dB)
AGC Block
Fine
0.094 dB/step
(0 to 6 dB)
Total Gain = 0 to 35.91 dB
Gain Control
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