SGS Thomson Microelectronics STU2071FN, STU2071B1 Datasheet
4B3T TWO-WIRE U INTERFACE CIRCUIT
FOR LT AND NT APP LICA TION
120 kbaud LINE SYMBOL RATE (120 SYMBOLS PER F RAM E)
SCRAMBLER AND DESCRAMBLER ACCORDING TO CCITT REC V.29
BARKER CODE (11 SYMBOLS) SYNCHRONIZATION WORD
UNSCRAMBLED 1 KBIT/S HOUSEKEEPING
CHANNEL
ADAPTIVE ECHO CANCELLATION WITH
TRANSVERSAL FILTERING
ADAPTIVE DECISION FEEDBACK EQUALIZATION
AUTOMATIC GAIN CONTROL
PDM AD CONV ERT E R
AUTOMATIC ACTIVATION AND DEACTIVA-
TION WITH POLARITY ADAPTION
AUTOMA TIC C ODE VI OLAT I O N DETECT I O N
POWER F EE D UNIT CO NT RO L
ADVANCED CL3 1.5µm CMOS PROCESS
28 PIN DUAL-IN-LINE P LAS TIC PA CK AGE
V* DIGITAL INTERFACE
STU2071
4B3T U INTERFACE CIRCUIT
PRELIMINARY DATA
DIP28
ORDERING NUMBER: STU2071B1
PLCC28
ORDERING NUMBER: STU2071FN
SYSTEM OVERVIEW
STU2071 (UIC) provides two transparent 64 kbit/s
B channels, a transparent 16 kbit/s D channel, a
transparent 1 kbit/s service channel and a 1 kbit/s
maintenance channel for loop and error messages on subscriber lines.
UIC enables full duplex continuous data transmission via the standard twisted pair telephone cable. Adaptive Echo cancellation is used to restore
the received data. An equalizer, done with an
adaptive filter, restores the data which are distorted by the transmission line.
The coefficient of the equalizer and echo canceller are conserved during a power down. An all
digital PLL performs both bit and frame synchronization.
The analog front end consists of receive path RX
and transmit path TX, providing a full duplex analog interfacing to the twisted pair telephone cable.
Before data are converted to analog signals, they
September 1994
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
pass through a digital filter (TX-filter) to reduce
the high frequency components. After D/A conversion the signal is amplified and sent to the hybrid.
The received signal is converted back to digital
data and passed through the RX matching filter to
restore the line signal. The A/D convertor is a
second order sigma/delta modulator which operates with a clock of 15.36 MHz. After timing recovery, achieved by a digital PLL, the received
signal is equalized, in an adaptive digital filter, to
correct for the frequency and group delay distortion of the line.
Power supply status can be read via PFOFF. The
UIC can disable its power supply (DISS), and two
relay drivers outputs are provided (accessible via
B2*) to control the power feed unit (RD1,RD2).
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STU2071
PIN CON NECTION (Top view)
TEST
LT
CLS
XTAL2
XTAL1
DVSS
PFOFF
DIP28
Figure 1: UIC Schematic Block Diagram
DISS/COEF
RESETN
DIN
TSP
BURST
DOUT
1234
5
6
7
8
9
10
FR
11
CL
PLCC28
RD2
RD1
15141312 1816 17
S2
2628 27
25
LIN2
24
LIN1
LOUT2
23
AGND
22
AVDD
21
LOUT1
20
AVSS
19
S1
S0
D93TL041
DVDD
2/18
PIN DESCRIPTION
Pin Name Function
1 DVSS(input) Digital Ground.
2 PFOFF(input) Power feed off. PFOFF=HIGH is coded by the A-bit indication HI
accessible on DOUT. Active in LT mode only.
3 LT(input) LT/NT mode selection.
4 TEST(input) Test Mode.
5 DISS(output) A bit channel driven pin. Active in LT mode only.
6 RESETN(input) Hardware Reset.
7 DIN(input) Digital interface input.
8 TSP(input) Transmit single pulse. 1 KHz single pulse alternating positive and
negative polarity is transmitted.
9 BURST(input) Burst mode selection. Active in LT mode only.
10 FR(in/out) 8KHz Digital interface frame clock; input in LT and output in NT mode.
11 DOUT(output) Digital interface output.
12 CL(in/out) Digital interface bit clock; input in LT and output in NT mode.
13 RD1(output) Power feeder relay driver.
14 RD2(output) Power feeder relay driver.
15, 16, 17 S2,S1,S0 Time slot pin strap (. Active in LT mode only.
18 DVDD(input) 5V +/-5% positive digital power supply.
19 AVSS(input) Analog Ground.
20 LOUT1(output) Output to the line.
21 AVDD(input) 5V +/-5% positive analog power supply.
22 AGND(input) Analog Ground.
23 LOUT2(output) Output to the line.
24,25 LIN1,LIN2(input) Inputs from the line (UK0).
26, 27 XTAL1,XTAL2(inputs) System clock input;nominal frequency is 15.36MHz.
28 CLS(output) Clock output synchronous to the line receive clock at 7.68MHz.
STU2071
APPLICATION AND MODES
The UIC can be used in LT, LT-burst and in NT
mode.
Hereafter a list of the pin bias to set up the desired mode is given.
In LT mode:
Pins Value
LT
BURST
S0
S1
S2
1
0
0
0
0
In LT burst:
Pins Value
LT
BURST
S0
S1
S2
In NT:
time slot
time slot
time slot
Pins Value
LT
BURST
S0
S1
S2
Test pins should always be tied to GND
1
1
0
0
0
0
1
3/18
STU2071
MODE DEPENDENT FUNCTIONS
PIN
LT input
BURST input
S2, S1, S0 input
DIN
DOUT
CLS (MHz) output
CL (KHz) input
FR (KHz) input
input
output
output
output
RECOMMENDED APPLICATIONS
LT mode
Figure 2: LT Schematic Application Diagram
LT burst NT LT LTRP NTRP
10100
10000
static 1 0 0 0 0 0 0 0 1 0 1 0
2048
kbit/s
7.68 7.68 7.68 – 7.68
4096
–
8
–
256
kbit/s
–
512
–
8
MODE
256
kbit/s
512
–
8
–
256
kbit/s
512
–
8
–
256
kbit/s
–
512
–
8
4/18
DIN:
DOUT:
CL:
FR:
XTAL2:
CLS:
Data input, datarate = 256 kbit/s, continuous
Data output, datarate = 256 kbit/s, continuous
Data clock input, f = 512 KHz
Frame clock input, f = 8 KHz (1:1)
System clock input, f = 15.36 MHz (Tx clock synchronous to system clock)
Clock output, 7.68 MHz
NT mode
Figure 3: LT Schematic Application Diagram
STU2071
DIN:
DOUT:
CL:
FR:
XTAL1/2:
CLS:
Data input, datarate = 256 kbit/s, continuous
Data output, datarate = 256 kbit/s, continuous
Data clock input, f = 512 KHz
Frame clock input, f = 8 KHz (1:1)
15.36 MHz Xtal connection (Clock not synchronous to system clock)
Clock output, 7.68 MHz (used to synch S interface)
5/18
STU2071
LT burst mode
Figure 4: LT Burst Mode Schematic Application Diagram.
6/18
DIN:
DOUT:
CL:
FR:
XTAL2:
CLS:
Data input, datarate = 2048 kbit/s, continuous
Data output, datarate = 2048 kbit/s, continuous
Data clock input, f = 4096 KHz
Frame clock input, f = 8 KHz (1:1)
System clock input, f = 15.36 MHz (Tx clock synchronous to system clock)
Clock output, 7.68 MHz
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