Datasheet STLC3065QTR, STLC3065Q Datasheet (SGS Thomson Microelectronics)



WLL SUBSCRIBER LINE INTERFACE CIRCUIT

MONOCHIPSLIC OPTIMISEDFOR WLL AP­PLICATIONS

IMPLEMENT ALL KEY FEATURES OF THE
BORSHTFUNCTION

SINGLESUPPLY(5.5TO 15.8V)
BUILT IN DC/DC CONVERTER CONTROL-

LER.
SOFT BATTERY REVERSAL WITH PRO-

GRAMMABLE TRANSITIONTIME.
ON-HOOKTRANSMISSION.
PROGRAMMABLE OFF-HOOK DETECTOR

THRESHOLD
METERING PULSE GENERATION AND FIL-

TER
INTEGRATEDRINGING
INTEGRATEDRING TRIP
DUAL 2W PORT FOR DATA/VOICE OPERA-

TION
PARALLEL CONTROL INTERFACE (3.3V

LOGICLEVEL)
PROGRAMMABLE CONSTANT CURRENT

FEEDER
SURFACE MOUNTPACKAGE

BLOCKDIAGRAM

STLC3065

TQFP44

ORDERING NUMBERS:

INTEGRATEDTHERMAL PROTECTION

-40 TO +85°COPERATING RANGE

DESCRIPTION

The STLC3065 is a SLIC device specifically de­signed for WLL (Wireless Local Loop) application.
One of the distinctive characteristics of this de­vice is the ability to operate with a single supply
voltage (from +5.5V to +15.8V)and self generate
the negative battery by means of an on chip
DC/DCconvertercontrollerthatdrivesan external

STLC3065Q

STLC3065QTR

October 1999

TX

RX

ZAC1

ZAC

RS

ZB

CKTTX
CTTX1
CTTX2

FTTX

D0 D1 D2 P1 P2 DET DET1 DET2

INPUT LOGICAND DECODER

Status andfunctions

SUPERVISION

AC PROC

TTX PROC

RTTX CAC ILTF RD IREF RLIM RTH

REFERENCE

OUTPUT LOGIC

LINE

DRIVER

Vcc

Vss

Agnd

LINE

SWITCH

DC PROC

DC/DC

CONV.

VOLT.

REG.

AGND

Vbat

BGND

TIP1

TIP2
RING1

RING2

CREV
CSVR

CLK
RSENSE
GATE

VF

CVCC

VPOS

VBAT

1/27

STLC3065

DESCRIPTION

(continued)
MOSswitch.
The self generated battery voltage tracks the line

resistance. In this way the power dissipation in­side the device is low enough to allow the use of
smallSMD package(TQFP44).

Other useful characteristics for application in the
WLL environment are the integratedringing gen­erator and the dual two wire port that allows to
drive two different terminal equipment whether
the transmission is voice or data. When one port
is transmittingtheotherone is idle.

The control interface is a parallel type with open
drainoutput and 3.3V logiclevels.

The metering pulses are generated on chip start­ing from two logic signals (0, 3.3V) one defines
the metering pulse frequency and the other the

PIN CONNECTION

VBAT1

CREV

TIP2

TIP1

44 43 42 41 3940 38 37 36 35 34

1

D0

2

D1

3

D2

4

P1

5

P2

6

DET1

7

DET2

8

DET

9

CKTTX

CTTX1

10

CTTX2

12 13 14 15 16

metering pulse duration. An on chip circuit then
providesthepropershapingand filtering.

Meteringpulse amplitudeand shaping (rising and
decay time)can be programmedby externalcom­ponents. A dedicated cancellation circuit avoid
possible CODEC input saturationdue to Metering
pulse echo.

Constant current feed can be set from 20mA to
40mA.

Off-hook detection threshold is programmable
from5mA to 9mA.

The device, developed in BCD100II technology
(100V process), operates in the extended tem­perature range and integrates a thermal protec­tion that set the device in power down when Tj
exceeds140°C.

N.C.

N.C.

N.C.

RING1

RING2

VBAT

BGND

33

CSVR

32

ILTF

31

RD

30

RTH

29

IREF

28

RLIM

27

AGND

26

CVCC

25

VPOS

24

RSENSE

23

GATE

171118 19 20 21 22

RTTX

FTTX

ZB

RX

ZAC1

ZAC

RS

CAC

TX

D96TL273B

VF

CLK

ABSOLUTEMAXIMUM RATINGS

Symbol Parameter Value Unit

V

pos

A/BGND AGND to BGND -1 to +1 V

V

dig

T

j

(1)

V

btot

(1) Vbat is self generated bytheon chip DC/DC converter and can be programmed via RF1 and RF2.

RF1andRF2 shall beselectedinorder tofulfil the a.m limits (see External Components Table page 13)

2/27

Positive Supply Voltage -0.4 to +17 V

Pin D0, D1, D2, P1,P2, DET, DET1, DET2 CKTTX -0.4 to 5.5 V
Max. junction Temperature 150 °C
Vbtot=|Vpos|+|Vbat|. (Total voltage applied to the device

100 V

supply pins).

STLC3065

OPERATINGRANGE

Symbol Parameter Value Unit

V

pos

A/BGND AGND to BGND -100 to +100 V

V

dig

T

op

(1)

V

bat

(1) Vbat is self generated bytheon chip DC/DC converter and can be programmed via RF1 and RF2.

RF1andRF2 shall beselectedinorder tofulfil the a.m limits (see External Components Table page 10)

THERMALDATA

Symbol Parameter Value Unit

R

thj-amb

PIN DESCRIPTION

N. Name Function

25 VPOS Positive supply inputranging from 5.5V to 15.8V.
34 BGND Battery Ground, must be shorted with AGND.
27 AGND Analog Ground, must be shorted with BGND.
16 ZAC AC impedance synthesis.
15 ZAC1 RX bufferoutput, the AC impedance is connected from this node to ZAC.
17 RS Protection resistors image (the image resistor is connected from this node toZAC).
18 ZB Balance Network for 2 to 4 wire conversion (the balance impedance ZB is connected from this

20 TX 4 wire output port (TX output). The signal is referred to AGND. If connected to single supply

14 RX 4 wire input port (RX input); 300KΩinput impedance. This signal is referred to AGND. If

19 CAC AC feedback input, AC/DC split capacitor (CAC).
32 ILTF Transversal line current image output.
41 TIP1 2 wire port #1; TIP wire (Ia is the current sourced from this pin).
37 RING1 2 wire port #1; RING wire (Ib is thecurrent sunk into this pin).
42 TIP2 2 wire port #2; TIP wire (Ia is the current sourced from this pin)
36 RING2 2 wire port #2; RING wire (Ib is thecurrent sunk into this pin)
28 RLIM Constant current feed programming pin (via RLIM). RLIM should be connected close to this

30 RTH Off-hook threshold programming pin (via RTH). RTH should be connected close to this pin

29 IREF Internal bias current setting pin. RREF should be connected close to this pin and PCB layout

43 CREV Reverse polarity transition time control.One proper capacitor connected between this pin and

26 CVCC Internal positive voltage supply filter.

Positive Supply Voltage 5.5 to +15.8 V

Pin D0, D1, D2, DET, DET1, DET2, CKTTX, P1,P

2

-0.25 to 5.25 V
Ambient Operating Temperature Range -40 to +85 °C
Self Generated Battery Voltage -74 max. V

Thermal Resistance Junction to Ambient Typ. 60 °C/W

node to AGND. ZA impedance is connected from this node to ZAC1).

CODEC input it must be DC decoupled with proper capacitor.

connected to single supply CODEC output it must be DC decoupled with proper capacitor.

pin andPCB layout should avoid noise injection on this pin.

and PCB layout should avoid noise injection on this pin.

should avoid noise injection on this pin.

AGND is setting the reverse polarity transition time. This is the same transition time used to
shape the”trapezoidal ringing” during ringing injection.

3/27

STLC3065

PIN DESCRIPTION (continued)

N. Name Function

35 VBAT Regulated battery voltage self generated by the device via DC/DC converter. Must be shorted

23 GATE Driver for external Power MOS transistor.
21 VF Feedback input for DC/DC converter controller.
22 CLK Power Switch Controller Clock (typ. 125KHz). From version marked STLC3065 A5, this pin

24 RSENSE Voltage input for current sensing. RSENSE should be connected close to this pin and VPOS

1 D0 Control Interface: input bit 0.
2 D1 Control Interface: input bit 1.
3 D2 Control interface: input bit 2.
4 P1 Control Interface: port 1 selection bit
5 P2 Control Interface: port 2 selection bit
8 DET Logic interface output of the supervision detector (active low).
6 DET1 Logic interface output of thr linr port 1 detector (active low)

7 DET2 Logic interface output of thr linr port 2 detector (active low)
33 CSVR Battery supply filter capacitor.
12 RTTX Metering pulse cancellation buffer output. TTX filter network should be connected to this point.

13 FTTX Metering pulse buffer inputthis signal is sent to the line and used to perform TTX filtering.
10 CTTX1 Metering burst shaping external capacitor.
11 CTTX2 Metering burst shaping external capacitor.

9 CKTTX Metering pulse clock input (12 KHz or 16KHz square wave).
44 VBAT1 Frame connection. Must be shorted to VBAT.

38,39,

40

NC Not connected.

to VBAT1.

can also be connected to CVCC or AGND. When the CLK pin is connected to CVCC an
internal auto-oscillation is internally generated and it is used instead of the external clock.
When the CLK pin is connected to AGND, the GATE output is disabled.

pin. The PCB layout should minimize the extra resistance introduced by the copper tracks.

If notused should be left open.

FUNCTIONAL DESCRIPTION

The STLC3065 is a device specifically developed
for WLLapplication.

It is based on a SLIC core, on purpose optimised
for this application, with the addition of a DC/DC
convertercontrollerand a dual port in order to ful­fil the WLLrequirements.

The SLIC core performs the standard feeding,
signallingandtransmission functions.

It can be set in three different operating modes
via the D0, D1, D2 pins of the control logic inter­face (0 to 3.3V logic levels). The loop status is
carried out on the DET pin (active low).The DET
pin is an open drain outputto allow easy interfac­ing with both 3.3V and 5V logic levels.

The three possible SLIC core operating modes
are:

Power Down (PWD)

4/27

Active
Ringing

Table 1 shows how to set the different SLIC core
operatingmodes.

Table1. SLIC core operating modes.

D0 D1 D2 Operating Mode

0 0 X PowerDown
0 1 0 Active Normal Polarity
0 1 1 Active Reverse Polarity
1 1 0 Active TTX injection (N.P.)
1 1 1 Active TTX injection (R.P.)
1 0 0/1 Ring (D2 bit toggles @ fring)

FUNCTIONAL DIAGRAM

STLC3065

CONTROL
INTERFACE

Tip1

Ring1

Tip2

Ring2

SW4R

300µA

SW4T

SW6R

SW3T

SW5R

SW3R

300µA

The STLC3065 operating modes will be obtained
as combination of the SLIC core status and the
dual port configuration.

The DC/DC converter controller is driving an ex­ternal power MOS transistor(P-Channel)in order
to generate the negative battery voltage needed
for device operation.

The DC/DC converter controller is synchronised
withan externalCLK (125KHztyp.).
From version marked STLC3065 A5, it can be
synchronisedto an internalclockgeneratedwhen
the pin CLK is connected to CVCC. One sensing
resistor in series to Vpos supply allows to fix the
maximumallowedinput peak current.This feature
is implemented in order to avoid overload on
Vpos supply in case of line transient (ex. ring trip
detection).

The typical value is obtained for a sensing resis­tor equal to 110mΩthat will guarantee an aver­age current consumptionfromVpos < 700mA.

In on-hook condition the self generated battery
voltageis set to a predefinedvalue.

This value can be adjusted via one externalresis­tor (RF1) and it is typical -50V. When RING mode
is selectedthis value is increasedup to -70Vtyp.

Once the line goes in off-hook condition the
DC/DC converter automatically adjust the gener­ated battery voltage in order to feed the line with

SLIC core

SW1T

SW1T

SW2T

SW2R

DC/DC converter
controller

a fixed DC current(programmable via RLIM) opti­misingin this way the power dissipation.

The Dual Port allows to connectthe SLIC core to
one of the two possible 2W ports (TIP1/RING1,
TIP2/RING2).

Dual port concept

One switches array integrated in STLC3065 al­lows to connect the TIP and RING output of the
SLIC core to one of the two 2W ports
(TIP1/RING1 or TIP2/RING2). For special condi­tions it is also possible to connect both ports to
the SLIC core.The structure of the switches array
is shown in fig.1 and it is controlled via the two
logicinputsP1 and P2.

Depending on the switches configurations each
2W port (TIP1/RING1or TIP2/RING2)can be set
in four possible conditions:

Open
Connected to BGND and Battery via two inte-

grated1.5KΩresistors.
Connectedto the SLIC core
Connected to an internal 300µA (min.) current

source.

Depending on the SLIC core operating modes
(definedby D0,D1 and D2) only a subsetof these
conditionscan be programmed.

TX
RX

5/27

STLC3065

Figure1. Dual Port Concept.

BGND

Tip

Line

Driver

Ring

R1 = 1500ohm

Table2. Dual Portcontrol.

R1

Sw1T

Sw1R

Sw2T

Sw2R

Sw6R

Sw4R

300µA 300µA

R1 R1

R1

Sw4T Sw3T

Is2

VBAT

TIP1

RING1

TIP2

RING2

Sw5R

Sw3R

Is1

LINE1

LINE2

D0 D1 D2 P1 P2 OPER. MODE LINE 1 LINE 2 DET DET1 DET2

0 0 X 0 0 Power Down Open Open - - ­0 0 X 1 1 High Z feed. To P.S. via

Res.

0 0 X 0 1 Power Down/

Open To P.S. via

High Z feed.

0 0 X 1 0 High Z feed.

Power Down

To P.S. via

Res.

To P.S. via

Res.

off-hook
line 1+2

off-hook

Res.

Open off-hook

line 2

line 1

off-hook

line 1

- off-hook

off-hook

line 1

off-hook

X 1 X 0 0 ACTIVE 300µA bias 300µA bias - - ­X 1 X 1 1 ACTIVE To Buffer To Buffer off-hook

--

line 1+2

X 1 X 0 1 ACTIVE 300µA bias To Buffer off-hook

--

line 2

X 1 X 1 0 ACTIVE To Buffer 300µA bias off-hook

--

line 1
1 0 X 0 1 RING 300µA bias 300µA bias - - ­1 0 X 1 1 RING To Buffer To Buffer Ring-trip

--

line 1+2

1 0 X 0 1 RING 300µA bias To Buffer Ring-trip

--

line 2
1 0 X 1 0 RING To Buffer 300µA bias Ring-trip

--

line 1

6/27

line 2

line 2

-

STLC3065

Where:

”Open”: the line port termination is in high impedance.
”To P.S. via Res”: the TIP(n) wire is connected to BGND through a 1500Ωresistor , the RING(n) wire is

”To Buffer”: the TIP(n) wire and RING(n) wire are connected to the SLIC core line driver and the off-

”300µA bias”: the TIP(n) wire is connected to BGND through a 1500Ωresistor , the RING(n) wire is

Note: see also Appendix C

connected to VBAT by a 1500Ωresistor. The current flowing in the second resistor is used
to detect the off-hook .

hook detection is performed using the SLIC core supervision circuit that drives the DET
output.

biased by a 300µA current generator to negative battery (Vbat)

Table 2 shows all the possible combinations be­tween switches configurations and operating
modes.

A detailed description of each configuration can
be found in the ”OPERATING MODES” descrip­tionsection.

OPERATINGMODES
Power Down (PWD)

D0 D1 D2 P1 P2 DET DET1 DET2

0 0 X 0 0 disable disable disable

DC CHARACTERISTIC & SUPERVISION
When this mode is selected both 2W ports

(TIP1/RING1andTIP2/RING2) are in high imped­ance; all switches Sw1 to Sw6 are open (see
fig.1)

The SLIC core is switched off and the line detec­tors are disabled therefore the off-hook condition
cannotbe detected.

This mode can be selected in emergency condi­tion when it is necessary to cut any current deliv­eredto the line.

This mode is also forced by STLC3065in case of
thermaloverload(Tj > 140°C).

In this case the device goes back to the previous
status as soon as the junction temperature de­creaseunderthe hysteresisthreshold.

AC CHARACTERISTICS
Both the 2W ports (TIP1/RING1and TIP2/RING2)

are set in highimpedance,the TX outputbufferis
a low impedance output, no AC transmission is
possible.

High ImpedanceFeeding(HI-Z)

D0 D1 D2 P1 P2 DET DET1 DET2

0 0 X 1 1 off/hk

line 1+2

0 0 X 0 1 off/hk

line 2

0 0 X 1 0 off/hk

line 1

off/hk
line 1

disable off/hk

off/hk
line 1

off/hk
line 2

line 1

disable

DC CHARACTERISTIC & SUPERVISION
This operating mode is normally selected when

the telephone is in on-hook in orderto monitorthe
line status keeping the power consumption at the
minimum.

The SLIC core of STLC3065 is in PWD mode
(see fig.1 or FUNCTIONAL DIAGRAM); the two
line series switches (Sw1; Sw2) are open. De­pending on P1, P2 the 2W ports (TIP1/RING1
and TIP2/RING2) can be in high impedance or
connected to the built in feeding resistors
(2x1500Ω) via SW3T and SW5R or SW4T and
SW6R.

P1 controls TIP1/RING1 and P2 controls
TIP2/RING2(see Fig.1 and Table2).

When this mode is selectednormallyboth P1, P2
bitsshould be set to one.

The output voltage in on-hook condition is equal
tothe self generatedbatteryvoltage(-50Vtyp).

When off-hook occurs on 2W port 1 (2) the cur­rent flowing through the RING1(2) wire activates
the DET1 (2_) detector indicating the line status
change. When DET1 or DET2 are activated also
the DET become active (low logiclevel).

The off-hook threshold in HI-Z mode is the same
value programmedin ACTIVEmode.

The DC characteristic in HI-Z mode is just equal
to the self generated battery with 2x(1500W+Rp)

7/27

STLC3065

in series (see fig.2), where Rp is the external pro­tectionresistance.

It should be noted that in case of both ports in HI­Z mode and both of them in off-hookconditionthe
power dissipated inside the chip could drive the
device in thermal protection. This can be pre­vented via a proper software control that should
avoid to keep as a steady condition both lines in
off-hook and HI-Z mode. Typical operation is to
set the SLIC core in active mode as soon as off­hook is detected.

Figure2. DC characteristicin HI-Z mode.

IL

Vbat

2x(R1+Rp)

Slope: 2x(R1+Rp)

(R1=1500ohm)

VL

Vbat (-50V)

AC CHARACTERISTICS
The AC impedance shown at the 2W ports

(TIP1/RING1 and TIP2/RING2) is the same as
the DC one. Depending on the P1, P2 bits the
TIP1/RING1 and TIP2/RING2 AC impedance will
be 2x(1500Ω + Rp) or high impedance.

Active

D0 D1 D2 P1 P2

X 1 X 0 0 disable disable disable
X 1 X 1 1 off/hk

X 1 X 0 1 off/hk

X 1 X 1 0 off/hk

DET DET1 DET2

disable disable

line 1+2

disable disable

line 2

disable disable

line 1

DC CHARACTERISTICS & SUPERVISION
When this mode is selected it is because one

connected telephone goes off-hook and the
STLC3065 is providing both DC feeding and AC
transmission.

The SLIC core is in ACTIVE mode and normally
only one of the two portshould be connected to it:

P1,P2= (1,0) or (0,1). (see Fig.1 and Table 2).
The unselected port is anyway DC biased being

TIP wire connected to BGND via a 1600W resis­tor and the RING wire connected to a 300mA
(min.)currentsourceconnectedto Vbat.

It should be noted that since Vbat is self gener­ated by the STLC3065 and it is tracking the line
voltage depending on the loop resistance con­nected to the selected port its voltage can range
typically from -12V to -50V. The unselected port
status (on/off hook) cannot be detected. For spe­cial configurations it is also possible to set AC­TIVEmode with both port selected(P1,P2=1,1) or
bothunselected(P1,P2=0,0).

Considering now the selected port, this is con­nected to the SLIC core. The STLC3065 feeds
the line with a constant current fixed by RLIM
(20mA to 40mA range). The on-hook voltage is
typically 40V allowing on-hook transmission; the
selfgeneratedVbatis -52V typ.

If the loop resistance is very high and the line
current cannot reach the programmed constant
currentfeed value, the STLC3065 behaveslike a
40V voltage source with a series impedance
equalto the protection resistors2xRp(typ. 2x41Ω)
plus the line series switches (Sw1 or Sw2)on re­sistance2xRsw(typ.2x9Ω).

Fig.3 shows the typical DC characteristic in AC­TIVEmode.

Figure3. DC characteristicin ACTIVE mode

IL

Ilim

(20 to

40mA)

2Rp+2Rsw

(100ohm typ.)

10V

Vbat (-50V)

VL

The line status (on/off hook) is monitored by the
SLIC core Supervision circuit. The off-hook
threshold can be programmed via the external
resistorRTHin the range from 5mA to 9mA.

When the line goes in off-hook condition the built
in DC/DC converter controller set properly the
Vbatsupplyin order to keep the loop current fixed
tothe programmedvalue.

Independently on the programmed constant cur­rent value, the TIP and RING buffers have a cur­rentsourcecapabilitylimited to 70mA typ.

8/27

STLC3065

Moreover the power available at Vbat is control­led by the DC/DC converter that limits the peak
current drawn from the Vpos supply. The maxi­mum allowed current peak is set by the RSENSE
resistorandit istypically900mApk.

AC CHARACTERISTICS
The SLIC core provides the standard SLIC trans-

missionfunctions:

Input impedance synthesis: can be real or
complex and is set by a scaled (x50) external
ZACimpedance.

Transmit and receive:

The AC signal present
on the 2W port (TIP/RING)is transferredto the
TX output with a -6dB gain and from the RX in­put to the2W port with a 0dB gain.

2 to 4 wire conversion: The balance imped­ance can be real or complex, the proper can­cellation is obtained by means of two external
impedanceZAand ZB.

Once in Active mode (D1=1) the SLIC core can
operatein differentstatessetting properly D0 and
D2 control bits (see also Table3).

D0 D1 D2 Operating state

0 1 0 Active Normal Polarity
0 1 1 Active Reverse Polarity
1 1 0 Active TTX injection (N.P.)
1 1 1 Active TTX injection (R.P.)

POLARITYREVERSAL
The D2 bit controls the line polarity, the transition

betweenthe two polaritiesis performed in a ”soft”
way. This means that the TIP and RING wire ex­change their polarities following a ramp transition
(see fig.4). The transition time is controlled by an
external capacitor CREV. This capacitor is also
setting the shape of the ringing trapezoidal wave­form.

Figure4. TIP/RINGtypicaltransition from

Directto Reverse Polarity

GND

TIP

4V typ.

40V typ
ON-HOOK

dV/dT set
byCREV

RING

Whenthe control pins set battery reversalthe line
polarity is reversed with a proper transition time
setvia an external capacitor(CREV).

METERING PULSE INJECTION (TTX)
The metering pulses circuit consist of a burst

shaping generator that gives a square wave
shaped and a low pass filter to reduce the har­monic distortionof theoutput signal.

The metering pulse is obtained starting from two
logicsignals:

CKTTX: is a square wave at the TTX fre­quency (12 or 16KHz) and should be perma­nently applied to the CKTTX pin or at least for
all the duration of the TTX pulse (including ris­ing and decay phases).

D0: enable the TTX generation circuit and de­finethe TTX pulse duration.

This two signals are then processed by a dedi­cated circuitry integrated on chip that generate
the metering pulse as an amplitude modulated
shaped squarewave(SQTTX) (see fig.5).

Both the amplitude and the envelope of the
squarewave (SQTTX) can be programmed by
means of external components. In particular the
amplitudeis set by the two resistorsRLV and the
shapingbythe capacitorCS.

The waveform so generated is then filtered and
injectedon the line. The low pass filter can be ob­tained using the integratedbuffer OP1 connected
between pin FTTX (OP1 non inverting input) and
RTTX (OP1 output) (see fig.5) and implementing
a ”Sallen and Key” configuration.

Dependingon the externalcomponentscountit is
possible to build an optimised application de­pending on the distortion level required. In par­ticular harmonic distortion levels equal to 13%,
6% and 3% can be obtained respectively with
first,secondand third order filters (see fig.5).

The circuit shown in the ”Application diagram” is
relatedto the simple firstorderfilter.

Once the shaped and filtered signal is obtainedat
RTTX buffer output it is injected on the TIP/RING
pins with a +6dB gain.

It should be noted that this is the nominal condi­tion obtained in presence of ideal TTX echo can­cellation(obtainedvia proper settingof RTTX and
CTTX). In addition the effective level obtained on
the line will depend on the line impedance, the
protection resistor value and the series switch
(SW1or SW2) on resistance.

In the typical application (TTX line impedance
=200Ω, RP=41Ω, SW1,2 on resistance= 9Ωand
ideal TTX echo cancellation) the metering pulse
level on the line will be 1.33 times the level ap­pliedto the RTTXpin.

9/27

STLC3065

Figure5. Meteringpulse generationcircuit.

CTTX1

Low Pass Filter

C1

BURST

SHAPING

GENERATOR

D0

CKTTX

Square wave pulse metering

CS

CTTX2

RLV

SQTTX

RLV

As already mentioned the metering pulse echo
cancellationis obtained by means of two external
components(RTTXand CTTX) that should match
the line impedance at the TTX frequency. This
simple networkhas a doubleeffect:

Synthesise a low output impedance at the
TIP/RINGpins at the TTX frequency.

Cut the eventual TTX echo that will be trans­ferredfromthe line to theTX output.

Ringing

FTTX

­OP1

+

C2

Sinusoidal wave
pulse metering

R2

R1

CFL

Required external components vs. filter order.

Order CFL R1 C! R2 C2 THD

1 X 13%
2 XXXX6%
3XXXXX3%

RTTX

Figure6. TIP/RINGtypicalringingwaveform

GND

TIP

2.5V typ.

65V

typ.

dV/dT set
by CREV

D0 D1 D2 P1 P2 DET DET1 DET2

1 0 0/1

1 0 0/1

1 0 0/1

1 1 RTrip

@fr

0 1 RTrip

@fr

1 0 RTrip

@fr

line 1+2

disable disable

disable disable

line 2

disable disable

line 1

When this mode is selected STLC3065self gen­erate an higher negative battery (-70V typ.) in or­der to allow a balanced ringing signal of typically
62Vpeak.

The SLIC core is set in ring mode via the control
inputsD0 andD1 set respectively to 0 and 1.

In this condition both the DC and AC feedback
loop are disabled and the SLIC core line drivers
operateas voltage buffers.

Theringwaveformis obtained togglingthe D2 con­trolbit at the desired ring frequency.This bit in fact
controlsthelinepolarity(0=direct;1=reverse).

As in the ACTIVE mode the line voltage transition
is performed with a ramp transition, obtaining in

10/27

RING

VBAT

2.5V typ.

this way a trapezoidal balanced ring waveform
(seefig.6).

The shaping is defined by the CREV external
capacitor.

Selecting the proper capacitorvalue it is possible
to get different crest fattor values. The following
table shows the crest factor values obtained with
a 20Hz and 25Hz ring frequency and with 1REN.
This value are valid either with European or USA
specification:

CREV

22nF 1.2 1.26
27nF 1.25 1.32
33nF 1.33 Not significant (*)

(*)Distorsion already less than 10%.

CREST

FACTOR

@20Hz

CREST

FACTOR

@25Hz

STLC3065

Depending on the P1,P2 control bits the ring
waveform can be applied to both 2W ports
(TIP1/RING1 and TIP2/RING2) or to one of the
two(see also table2).

The ring trip detection is performed sensing the
variation of the AC line impedance from on hook
(relatively high) to off-hook (low). This particular
ring trip method allows to operate without DC off­set superimposedon the ring signal and therefore
obtaining the maximum possible ring level on the
load startingfrom a givennegativebattery.

It should be noted that such a method is opti­mised for operation on shortloop applicationsand
may not operateproperlyin presenceof long loop
applications(>500Ω).

Once ring trip is detected,the DET output is acti­vated (logic level low), at this point the card con­troller or a simple logic circuitshould stop the D2
toggling in order to effectively disconnect the ring
signal and then set the STLC3065 in the proper
operatingmode(NormallyACTIVE).

RING LEVEL IN PRESENCE OF MORE TELE­PHONEIN PARALLEL.

As already mentioned above the maximum cur­rent that can be drawn from the Vpos supply is
controlledandlimitedvia theexternalRSENSE.

This will limit also the power available at the self
generatednegative battery.

If for any reason the ringer load will be too high
the self generated battery will drop in order to
keep the power consumption to the fixed limit and
therefore also the ring voltage level will be re­duced.

In the typical application with RSENSE = 110mW
the peak current from Vpos is limited to about
900mA, which correspond to an average current
of 700mA max. In this condition the STLC3065
can drive up to 3REN with a ring frequency
fr=25Hz (1REN = 1800Ω+ 1.0µF, European
standard).

In order to drive up to 5REN (1REN= 6930Ω+
8mF, US standard) it is necessary to modify the
externalcomponentsas follows:

CREV= 15nF
RD = 2.2 K

Power On Requirements

In order to avoid damage to the device when
Vpos is first applied it is recommended to keep all
the logic inputs to a low logic level (0V) until Vpos
is > 5.5V.

Ω

In case this power up sequence cannot be guar­anteed,it’s recommendedto connect a shottkydi­ode (BAT46 or equivalent) between VBAT and
BGND(see figure 7).

Figure7. Shottkydiode connection

BGND

STLC3065

VBAT

LayoutRecommendation

A properly designed PCB layout is a basic issue
to guarantee a correct behaviourand good noise
performances.

Particularcare must be taken on the ground con­nection and in this case the star configuration al­lows surely to avoid possibleproblems(see Appli­cationDiagramFig. 8).

The ground of the power supply (VPOS) has to
be connected to the center of the star, let’s call
this point PGND. This point should show a resis­tance as low as possible, that means it should be
a ground plane.

Noise sources can be identified in not enough
good grounds, not enough low impedance sup­plies and parasitic coupling between PCB tracks
and high impedance pins of the device.

In particular, to avoid noise problems, layout
should prevent any coupling between the DC/DC
converter components and analog pins that are
referred to AGND (ex: RD, IREF, RTH, RLIM,
VF). As a first reccomendation the components
CV, L, D1, CVPOS, RSENSE should be kept as
close as possible to each other and isolated from
theother components.

Additionalimprovements can be obtained:
decoupling the center of the star from the analog

groundof STLC3065 using small chokes.
adding a capacitorin therange of 100nF between

VPOS and AGND in order to filter the switch fre­quencyon VPOS.

BAT46

11/27

STLC3065

ExternalComponents List

In order to properly define the external compo­nents value the following system parameters
have to be defined:

The AC input impedance shown by the SLIC at
the line terminals ”Zs” to which the return loss
measurement is referred. It can be real (typ.
600Ω) or complex.

The AC balance impedance, it is the equiva­lent impedance of the line ”Zl” used for evalu­ation of the trans-hybrid loss performances
(2/4 wire conversion). It is usually a complex
impedance.

The value of the two protection resistors Rp in
series with the line termination.

The line impedance at the TTX frequency
”Zlttx”.

The metering pulse level amplitude measured
at line termination ”V

”. In case of low or-

LOTTX

der filtering, V

represents the amplitude

LOTTX

(Vrms) of the fundamental frequency compo­nent.(typ12 or 16KHz).

Pulse metering envelope rise and decay time
constant”t”.

The slope of the ringing waveform”∆V

TR/∆T

”.

The value of the constant current limit current
”Ilim”.

The value of the off-hook current threshold
”I

”.

TH

The value of the ring trip rectified average
thresholdcurrent”I

RTH

”.

The value of the requiredself generated nega­tive battery ”V

” in ring mode (max value is

BATR

70V). This value can be obtained from the de­sired ringpeak level +5V.

The value of the maximum current peak sunk
fromVpos”IPK”.

12/27

EXTERNAL COMPONENTS

Name Function Formula Typ. Value

RREF Bias setting current RREF = 1.3/Ibias

Ibias = 50µA

CSVR Negative Battery Filter CSVR = 1/(2

π ⋅fp⋅

1.8MΩ)

fp = 50Hz

RD Ring Tripthreshold setting

resistor

RD = 100/I

RTH

2KΩ<RD<5K

Ω

CAC AC/DC split capacitance 22µF 20% 15VL

RP Line protection resistor Rp > 30
RS Protection and series switches

Ω

RS = 100⋅(Rp + 9Ω)5k

resistance image

ZAC Two wire AC impedance ZAC = 50⋅(Zs - 2Rp - 18Ω) 25kΩ1%

ZA (1) SLIC impedance balancing

ZA = 50⋅Zs 30kΩ1%

network

ZB (1) Line impedance balancing

ZB = 50⋅Zl 30kΩ1%

network

CCOMP AC feedback loop compensation CCOMP= 1/(2π⋅fo⋅100⋅(RP+9Ω))

fo = 250kHz

CH Trans-Hybrid Loss frequency

CH = CCOMP 120pF 10% 10VL

compensation

RLIM Current limiting programming RLIM = 1300/Ilim

RTH Off-hook threshold programming

(ACTIVE mode)

CREV Reverse polarity transition time

32.5kΩ< RLIM < 65k
RTH = 260/I

TH

27kΩ< RTH < 52k
CREV = (1/3750)

Ω

Ω

⋅ ∆T/∆

V

) 22nF 10% 10V

TR

programming

RTTX (3) Pulse metering cancellation

RTTX = 50Re[(Zlttx+2Rp+18Ω)] 15k

resistor

CTTX (3) Pulse metering cancellation

CTTX = 1/{50⋅2π⋅fttx[-lm(Zlttx)]} 100nF 10% 10V (2)

capacitor

RLV Pulse metering level resistor RLV = 63.3⋅10

= (|Zlttx + 2Rp + 18Ω|/|Zlttx|)

α

CS Pulse metering shaping

CS =τ/(2⋅RLV) 100nF 10% 10V

capacitor

3

V

⋅α⋅

LOTTX

@τ= 6ms, RLV = 27.1k

CFL Pulse metering filter capacitor CFL = 2/(2π⋅fttx⋅RLV) 1nF 10% 10V

RDD Pull up resistors 100k

CVCC Internally supply filter capacitor 100nF 20% 10V

CVpos Positive supply filter capacitor

with low impedance for switch
mode power supply

CV Battery supply filter capacitor

with low impedance for switch
mode power supply

CVB High frequency noise filter 470nF 20% 100VL

26kΩ1%

1.5nF 10%
100VL

4.12kΩ1%

@ IRTH = 24mA

@ RD = 4.12k

41Ω1%
@Rp=41

Ω

@ Zs = 600

@ Zs = 600

@ Zl = 600

120pF 10% 10VL

@Rp=41

52.3kΩ1%

@ Ilim = 25mA

28.7kΩ1%

@ITH= 9mA

@ 12V/ms

@Zlttx = 200Ωreal

@ Zlttx = 200Ωreal

27kΩ1%

@V

LOTTX

@fttx = 12kHz

RLV = 27k

100µF(4)

100µF 20% 100V (5)

STLC3065

Ω

Ω

Ω

Ω

Ω

Ω

Ω

= 275mVrms

Ω

Ω

Ω

13/27

STLC3065

EXTERNAL COMPONENTS

(continued)

Name Function Formula Typ. Value

CRD (6) High frequency noise filter 100nF 10% 15VL

Q1 DC/DC converter switch P ch.

MOS transistor

RDS(ON)≤1.2Ω,VDS = -100V
Total gate charge=20nC max.
with VGS=4.5V and VDS=1V

Possible choiches:
IRF9510 or IRF9520 or
IRF9120 or equivalent

ID>500mA

D1 DC/DC converter series diode Vr > 100V, t

50ns SMBYW01-200

≤

RR

or equivalent

RSENSE DC/DC converter peak current

limiting

RSENSE = 100mV/I

PK

@I

110m

= 900mA

PK

Ω

L (8) DC/DC converter inductor DC Resistance≤0.1Ω(9) L=125µH RFP1304PV

(Manuf.: All Inductive)

or SUMIDA CDRH125

or equivalent

CF1 DC/DC converter feedback loop

220pF to470pF (10)

stability

RF1 Negative battery programming

level

RF2 Negative battery programming

250KΩ<RF1<300KΩ(7) 300kW 1%

@V

BATR

= -70V

9.1kΩ1%

level

(1) In case Zs=Zl, ZA and ZB can bereplacedby two resistors of same value: RA=RB=|Zs|.
(2) In thiscase CTTX is justoperating as a DC decoupling capacitor (fp=100Hz).
(3) Defining ZTTX as the impedance ofRTTX inserieswithCTTX,RTTX and CTTX canalso becalculated from the following formula:

ZTTX=50*(Zlttx+2Rp+18Ω).
(4) CVpos should be defined dependingon the power supply current capability and maximum allowable ripple.
(5) For low ripple applicationuse 2x47µF inparallel.
(6) Can be saved if properPCBlayoutavoid noise coupling on RD pin (high impedance input).
(7) RF1 sets the selfgeneratedbattery voltage in RING andACTIVE(Il=0)mode as follows:

267k

Ω

V

BAT(ACTIVE)

V

BATR(RING)

VBATR should be defined consideringthe ring peak level required (Vringpeak=VBATR-6Vtyp.).
The above relation is valid provided that the Vpos power supply current capability and the RSENSE programming allow to source all the
current requested by the particularringerload configuration.
(8) Core: MICROMETALS T50-26C IRON POWDER, AL-VALUE61nH/N2

(9) For high efficiency in HI-Z mode coil resistance@125kHz must be <3ohm
(10) Functionof this capacitoristo introduceazeroat theresonancefrequency for loopstability. In case someparasitic resistance are already
present in the loop (Coil, CVBAT, PCB layout), the presence of this capacitor can degrade the device noise performances; in this case CF1
should be removed beingtheloop stabilityalready guaranteed by theparasitic resistance.

Current rating: 2A(50/60Hz)
Operating Temperature -25° to +60° Centigrades

Inductance:14µH +/-15% at 1KHz,1mA
DC resistance of winding: MAX.100mOhm
Code: RFY1303
Wire: UEW2, 0,60 mm
Turns: 50
Inductance (f=1KHz): >125µH

-46V -48V -49V -50V

-62V -65V -68V -70V

280k

Ω

294kW 300k

Ω

14/27

Figure8. Applicationdiagram.

STLC3065

CONTROL

INTERFACE

D0
D1
D2
P1
P2

TTX CLOCK

CCOMP

VDD

CFL

CH

RLV

RLV

RDD

RS

ZAC

CVPOS

VPOS

RSENSE

GATE

VBAT1

VBAT

CLK

TIP1

RING1

TIP2

RING2

CSVR
CREV

RTH

RLIM

IREF

RSENSE

CVB

CREV

CLK

RLIM

RP

RP

RP

RP

CF1

CSVR

RTH

RF1

RF2

TIP1

RING1

TIP2

RING2

Q1

D1

L

CVVF

TX

RX

TX

RX

RS
ZAC
ZAC1

ZA

ZB

CS

ZB

DETDET
DET1DET1
DET2DET2
D0
D1
D2
P1
P2

CKTTX

CTTX1

CTTX2
FTTX

RTTX

BGND CVCC

AGND VPOS

CAC

CVCC

STLC3065

RD

ILTF

SUPPLY GND

SUGGESTED GROUND LAY-OUT

BGND

AGND

PGND

RTTX

CTTX

CAC

RD

CRD

RREF

D96TL252E

15/27

STLC3065

ELECTRICAL CHARACTERISTICS

Testconditions:V
Externalcomponentsas listedinthe ”Typical Values” column of EXTERNAL COMPONENTSTable.
Note: Testing of all parameter is performed at 25°C. Characterisationas well as design rules used allow

correlationof tested performancesat other temperatures.All parameters listed here are met in the oper­ating range: -40 to +85°C.

DC CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

lohi

V

lohi

V

loa

V

loa

Ilim Lim. current programming range ACTIVE mode 20 40 mA

Ilima Lim. current accuracy ACTIVE mode.

Rfeed HI Feeding resistance HI-Z (High Impedance feeding) 2.4 3.6 k

Zrx RX port input impedance 280 k

AC CHARACTERISTICS

L/T Long. totransv.

T/L Transv. to long.

T/L Transv. to long.

2WRL 2W return loss 300 to 3400Hz,

THL Trans-hybrid loss 300 to 3400Hz,

Ovl 2W overload level at line terminals on ref.imped.

TXoff TX output offset ACTIVE N. P., R

G24 Transmit gain abs. 0dBm @ 1020Hz,

G42 Receive gain abs. 0dBm @ 1020Hz,

G24f TX gain variation vs. freq. rel. 1020Hz; 0dBm,

Line voltage Il = 0, HI-Z

Line voltage Il = 0, HI-Z

Line voltage Il = 0, ACTIVE

Line voltage Il = 0, ACTIVE

(see Appendix for test circuit)

(see Appendix for test circuit)

(see Appendix for test circuit)

= 6.0V,AGND = BGND,NormalPolarity,T

pos

(High impedance feeding)
T

= 0 to 85°C

amb

(High impedance feeding)
T

= -40 to 85°C

amb

T

= 0 to 85°C

amb

T

= -40 to 85°C

amb

Rel. to programmed value
20mA to 40mA

Rp = 41Ω, 1% tol.,
ACTIVE N. P., R
f = 300 to 3400Hz

Rp = 41Ω, 1% tol.,
ACTIVE N. P., R
f = 300 to 3400Hz

Rp = 41Ω, 1% tol.,
ACTIVE N. P., R
f = 1kHz

ACTIVE N. P., R

20Log|VRX/VTX|,
ACTIVE N. P., R

ACTIVE N. P., R

ACTIVE N. P., R

ACTIVE N. P., R

300 to 3400Hz,
ACTIVE N. P., R

=25°C.

amb

44 50 V

42 48 V

33 40 V

31 37 V

-10 10 mA

48 50 dB

= 600Ω(*)

L

40 45 dB

= 600Ω(*)

L

48 53 dB

= 600Ω(*)

L

22 26 dB

= 600Ω(*)

L

30 dB

= 600Ω(*)

L

10 dBm

= 600Ω(*)

L

= 600Ω(*) -150 150 mV

L

-6.4 -5.6 dB

= 600Ω(*)

L

-0.4 0.4 dB

= 600Ω(*)

L

-0.12 0.12 dB

= 600Ω(*)

L

Ω
Ω

16/27

STLC3065

ELECTRICAL CHARACTERISTICS

(continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

G42f RX gain variation vs. freq. rel. 1020Hz; 0dBm,

-0.12 0.12 dB
300 to 3400Hz,
ACTIVE N. P., R

V2Wp Idle channel noise at line psophometric filtered

ACTIVE N. P., R
T

= 0 to +85°C

amb

V2Wp Idle channel noise at line psophometric filtered

ACTIVE N. P., R
T

= -40 to +85°C

amb

V4Wp Idle channel noise at line psophometric filtered

ACTIVE N. P., R
T

= 0 to +85°C

amb

V4Wp Idle channel noise at line psophometric filtered

ACTIVE N. P., R
T

= -40 to +85°C

amb

Thd Total Harmonic Distortion ACTIVE N. P., R

VTTX Metering pulse level on line ACTITIVE - TTX

= 600Ω(*)

L

-73 -68 dBmp

= 600Ω(*)

L

-68 dBmp

= 600Ω(*)

L

-75 -70 dBmp

= 600Ω(*)

L

-75 dBmp

= 600Ω(*)

L

= 600Ω(*) -46 dB

L

200 250 mVrms

Zl = 200Ωfttx = 12kHz

CLKfreq CLK operating range -10% 125 10% kHz

AIS Insolation between 2-wire ports ACTIVE, odBm0

@ 1020Hz, R

(*) RL: Line Resistance

L

= 600

Ω

-20 dB

RING

Vring Line voltage RING D2 toggling @ fr = 25Hz

45 49 Vrms
Load = 3REN;
Crest Factor = 1.25
1REN = 1800Ω+ 1.0µF
T

= 0 to +85°C

amb

Vring Line voltage RING D2 toggling @ fr = 25Hz

44 48 Vrms
Load = 3REN;
Crest Factor = 1.25
1REN = 1800Ω+ 1.0µF
T

= -40 to +85°C

amb

LIS Insolation between 2-wire ports RING Mode on Port1 -50 dBmp

DETECTORS

IOFFTHA Off/hook current threshold ACT. mode, RTH = 28.7kΩ1%

10.5 mA

(Prog. ITH =9mA)

ROFTHA Off/hook loopresistance

threshold

IONTHA On/hook current threshold ACT. mode, RTH = 28.7kΩ1%

ACT. mode, RTH = 28.7kΩ1%
(Prog. ITH =9mA)

3.4 k

6mA

(Prog. ITH =9mA)

RONTHA On/hook loop resistance

threshold

IOFFTHI Off/hook current threshold Hi Z mode, RTH = 28.7kΩ1%

ACT. mode, RTH = 28.7kΩ1%
(Prog. ITH =9mA)

8k

10.5 mA

(Prog. ITH =9mA)

ROFFTHI Off/hook loop resistance

threshold

Hi Z mode, RTH = 28.7kΩ1%
(Prog. ITH =9mA)

800

Ω

Ω

Ω

17/27

STLC3065

ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit

IONTHI On/hook current threshold Hi Z mode, RTH = 28.7kΩ1%

RONTHI On/hook loop resistance

threshold

Irt Ring Trip detector threshold

range

Irta Ring Trip detector threshold

accuracy

Trtd Ring trip detectiontime RING TBD ms

Td Dialling distortion ACTIVE -1 1 ms

Rlrt (1) Loop resistance 500

ThAl Tj for th. alarm activation 160 °C

(1) Rlrt = Maximum loop resistance (incl. telephone)forcorrectring trip detection.

DIGITAL INTERFACE

INPUTS: D0, D1, D2, P1, P2,CLK
OUTPUTS: DET, DET1, DET2

Vih In put high voltage 2 V

Vil Input low voltage 0.8 V
Iih Input highcurrent -10 10

Iil Input low current -10 10

Vol Output low voltage Iol = 1mA 0.45 V

PSRR AND POWER CONSUMPTION

PSRRC Power supply rejection Vpos to

2W port

Ivpos Vpos supply current @ ii = 0 HI-Z On-Hook

Ipk Peak current limiting accuracy RING Off-Hook

(continued)

(Prog. ITH =9mA)
Hi Z mode, RTH = 28.7kΩ1%

(Prog. ITH =9mA)
RING 20 50 mA

RING -15 15 %

Vripple = 100mVrms
50 to 4000Hz

ACTIVE On-Hook,
RING (line open)

RSENSE = 110m

Ω

8k

26 36 dB

52
93

120

-20% 950 +20% mApk

6mA

60
115
140

Ω

Ω

A

µ

A

µ

mA
mA
mA

18/27

STLC3065

APPENDIX A

STLC3065TestCircuits

Referring to the application diagram shown in fig. 8 of the STLC3065 datasheet and using as external
components the Typ. Values specified in the ”External Components” Table (page 16) find below the
properconfigurationfor each measurement.

All measurements requiring DC current termination should be performedusing ”Wandel & Goltermann
DC Loop Holding CircuitGH-1”or equivalent.

FigureA1. 2W ReturnLoss

2WRL= 20Log(|Zref+ Zs|/|Zref-Zs|)=20Log(E/2Vs)

W&GGH1

Zref

TIP1/TIP2

600ohm

Vs

1Kohm

E

1Kohm

100µF

100mA
DC max

Zin = 100K
200 to 6kHz

100µF

STLC3065
application

circuit

TX

FigureA2. THL Trans Hybrid Loss

THL = 20Log|Vrx/Vtx|

W&G GH1

100µF

100mA

600ohm

DC max

Zin = 100K
200 to 6kHz

100µF

TIP1/TIP2

STLC3065
application

circuit

RING1/RING2

RING1/RING2

TX

RX

RX

Vtx

Vrx

19/27

STLC3065

FigureA3. G24 Transmit Gain

G24 = 20Log|2Vtx/E|

W&G GH1

600ohm

E

FigureA4. G42 Receive Gain

G42 = 20Log|Vl/Vrx|

Vl

600ohm

100µF

100mA
DC max

Zin =100K
200 to6kHz

100µF

W&G GH1

100µF

100mA
DC max

Zin = 100K
200 to 6kHz

100µF

TIP1/TIP2

STLC3065
application

circuit

RING1/RING2

TIP/1TIP2

STLC3065
application

RING1/RING2

TX

Vtx

RX

TX

circuit

RX

FigureA5. PSRRC Power supply rejectionVposto 2W port

PSSRC= 20Log|Vn/Vl|

W&G GH1

100µF

Vl

600ohm

20/27

100mA
DC max

Zin =100K
200 to 6kHz

100µF

TIP1/TIP2

STLC3065
application

circuit

RING1/RING2

VPOS

~

Vrx

TX

RX

Vn

FigureA6. L/T Longitudinalto Transversal Conversion

L/T = 20Log|Vcm/Vl|

STLC3065

W&G GH1

100µF

100mA
DC max

Zin =100K
200 to 6kHz

100µF

Vcm

300ohm

300ohm

100µF

Impedancematching
better than 0.1%

100µF

FigureA7. T/L Transversal to Longitudinal Conversion

T/L = 20Log|Vrx/Vcm|

W&G GH1

100µF

100mA
DC max

Zin= 100K
200to 6kHz

100µF

600ohm

Vcm

300ohm

100µF

Impedancematching
better than 0.1%

Vl

TIP1/TIP2

STLC3065
application

circuit

RING1/RING2

TIP1/TIP2

STLC3065
application

RING1/RING2 RX

TX

RX

TX

circuit

Vrx

300ohm

100µF

FigureA8. VTTX Metering Pulse level on line

Vlttx

200ohm

TIP1/TIP2

STLC3065
application

circuit

RING1/RING2 RX

CKTTX

fttx (12 or 16kHz)

TX

21/27

STLC3065

FigureA9. V2Wpand W4Wp:Idlechannelpsophometric noise at line and TX.

V2Wp= 20Log|Vl/0.774l|;V4Wp = 20Log|Vtx/0.774l|

W&G GH1

100µF

100mA

600ohm

Vl

psophometric

filtered

DC max

Zin = 100K
200 to6kHz

100µF

FigureA10. AIS Isolationbetween2 wire ports

AIS= 20Log|Vais/Vl|

W&G GH1

100µF

100mA

Vl

600ohm

DC max

Zin =100K
200 to6kHz

100µF

TIP1/TIP2

STLC3065

application

TIP1/TIP2

STLC3065
application

circuit

RING1\RING2

circuit

TX

Vtx

psophometric

filtered

RX

TX

22/27

Vais

100µF

600ohm

100µF

RING1/RING2

TIP2/TIP1

RING2/RING1

RX

Vrx

FigureA11. Vring,Vlis:RingVoltage and port isolation

STLC3065

Vring
(true rms
meter)

Vlis
(psophometric
meter)

1µF

1800ohm

100µF

600ohm

100µF

TIP1/TIP2

STLC3065
application

circuit

RING1/RING2

TIP2/TIP1

RING2/RING1

D2

TX

RX

fring (25Hz)

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STLC3065

APPENDIX B

STLC3065OVERVOLTAGE PROTECTION

FigureB1. Simplifiedconfiguration for indoor overvoltage protection

BGND

STLC3065

TIP1

RP1

RP2

TIP1

2x

SM4T39RX

RING1

TIP2

RING2

RP1

RP1

RP1

RP2

RP2

RP2

VBAT

FigureB2. Standard overloltageprotection configuration for k20 compliance

2x

SM4T39RX

BGND

TIP1

RING1

STLC3065

RP1

RP1 RP2

LCDP
1511

RP2

RING1

TIP2

RING2

RP2: Fuse or PTC

TIP1

RING1

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VBAT

TIP2

RING2

RP1

RP1 RP2

RP2: Fuse orPTC

RP2

TIP2

RING2

NOTE:RP2shouldguaranteeIpeak< 10A: otherwise two LCP1511maybe used

APPENDIX C

FigureC1. Typical state diagram for the STLC3065operation

STLC3065

Tj>Tth

Line 1 State,
Line 2 State

D0=D1=P1=P2=0

Power Down,
Power Down

P1=1
P2=0

HI-Z Feeding,
Power Down

RingBurst
Line1,
D2=0/1

P1=P2=1

Line1OnHook,

P1=1,P2=0

Line1Off Hook

HI-Z Feeding,
HI-Z Feeding

Line1,
Off Hook

P1=0,P2=1

Line2OnHook,

Act OffHook,
Ic Feeding

RingTrip
Detection
Line1

Ringing,
Ic Feeding

Power Down,
HI-Z Feeding

P1=0,P2=1

Line2Off Hook

Line2OnHook

Line1
On Hook,

P1=P2=1

P1=P2=1

Line1OffHook

Line1Off Hook

RingBurst

Line2Off Hook

Ic Feeding,
Act OffHook

Ring Burst
Line1and 2,
D2=0/1

RingBurst
Line2,
D2=0/1

Ring Trip
Detection
Line2

Line2Off Hook

Line2Off Hook

Ringing,
Ringing

Act On Hook,
Ic Feeding

Ic Feeding,
Ringing

SW
routine
(*)

RingTrip
Detection

RingBurst

RingBurst

RingPause

RingPause

Ic Feeding,

Act On Hook

Off Hook
Detection

Act On Hook,
Act On Hook

RingPause

Note: all statetransitionsareunder the microprocessor control.
(*) = When the ringingsignal is sent to both lines, theSTLC3065is not able to detectthe answering line. To detect the answeringline, aSW

routine is needed that disables firstthe line 1 (forcing P1=0) andthen the line2 ( forcing P2=0) so as to detect which line is inOff Hook

condition.
The On Hook condition is declared when itpersists forT>Tref.
Ic Feeding state is referred to aconstant feeding current appliedto the local loopandequalto 300µA.

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STLC3065

26/27

STLC3065

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subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
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