N - CHANNEL 500V - 0.48Ω - 10A - I2PAK/D2PAK
TYPE V
DSS
ST B10NC50-1 500 V < 0.52 Ω 10 A
■ TYPICALR
■ EXTREMELYHIGH dv/dt CAPABILITY
■ 100%AVALANCHETESTED
■ VERYLOW INTRINSIC CAPACITANCES
■ GATECHARGE MINIMIZED
DS(on)
= 0.48 Ω
DESCRIPTION
Using the latest high voltage MESH OVERLAY
process, STMicroelectronics has designed an
advanced family of power MOSFETs with
outstanding performances. The new patent
pending strip layout coupled with the Company’s
proprietary edge termination structure, gives the
lowest RDS(on) per area, exceptional avalanche
and dv/dt capabilities and unrivalled gate charge
and switching characteristics.
R
DS(on)
I
D
STB10NC50-1
PowerMESH MOSFET
PRELIMINARY DATA
3
2
1
I2PAK D2PAK
INTERNAL SCHEMATIC DIAGRAM
3
1
APPLICATIONS
■ HIGHCURRENT, HIGH SPEEDSWITCHING
■ SWITCHMODE POWER SUPPLIES(SMPS)
■ DC-AC CONVERTERS FOR WELDING
EQUIPMENTAND UNINTERRUPTIBLE
POWERSUPPLIESAND MOTORDRIVE
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
V
I
DM
P
dv/ dt(
T
(•) Pulse width limited by safe operating area (1)ISD≤ 10 A, di/dt ≤100 A/µs,VDD≤ V
Drain-sour ce Voltage (VGS=0) 500 V
DS
Drain- ga t e V oltage (RGS=20kΩ)
DGR
Gate-sourc e Voltage ± 30 V
GS
Drain C urrent (con tinuous) at Tc=25oC10A
I
D
Drain C urrent (con tinuous) at Tc= 100oC6.3A
I
D
500 V
(•) Drain C urrent (puls ed ) 40 A
Total Dissipation at Tc=25oC135W
tot
Derating Factor 1.08 W/
1) Peak Diod e Rec o very volt ag e slope 3 V/ns
Sto rage T e m pe r ature -65 to 1 50
stg
Max. O pe rating Junc t ion Temp eratur e 150
T
j
(BR)DSS
,Tj≤T
JMAX
o
C
o
C
o
C
December 1999
1/7
STB10NC50-1
THERMAL DATA
R
thj-case
R
thj-amb
R
thc-sink
T
AVALANCHE CHARACTERISTICS
Symbol Para meter Max Val ue Uni t
I
AR
E
Ther mal Resis t an ce Junc ti on-cas e Max 0.93
Ther mal Resis t an ce Junc ti on-ambien t Max
Thermal Resistance Case-sink Typ
Maximum Le ad Temper at u re F or Sold er ing P ur p os e
l
Avalanche Cu r rent, Repetitive or Not -R e petitive
(pulse width limite d by T
Single Pu lse Avalanche Energy
AS
(starting T
=25oC, ID=IAR,VDD=50V)
j
max)
j
62.5
0.5
300
10 A
550 mJ
o
C/W
o
C/W
o
C/W
o
C
ELECTRICAL CHARACTERISTICS (T
=25oC unless otherwisespecified)
case
OFF
Symbol Parameter Test Con ditions Min. Typ. M ax. Unit
V
(BR)DSS
Drain-sourc e
=250µAVGS=0
I
D
500 V
Break d own Voltage
I
DSS
I
GSS
Zero Gate Voltage
Drain Current (V
GS
Gat e- b ody Leakage
Current (V
DS
=0)
=0)
V
=MaxRating
DS
= Max Rating Tc=125oC
V
DS
= ± 30 V
V
GS
1
50
± 100 nA
ON(∗)
Symbol Parameter Test Con ditions Min. Typ. M ax. Unit
V
GS(th)
Gate Threshold
V
DS=VGSID
= 250 µA
234V
Voltage
R
DS(on)
Static Drain-source On
VGS=10V ID= 5 A 0.48 0.52 Ω
Resistanc e
I
D(on)
On State Drain Cu r rent VDS>I
D(on)xRDS(on)max
10 A
VGS=10V
DYNAMIC
Symbol Parameter Test Con ditions Min. Typ. M ax. Unit
g
(∗)Forward
fs
Tr ansconduc tance
C
C
C
Input Capacit ance
iss
Out put Ca pacita nce
oss
Reverse T ransfer
rss
Capacitance
VDS>I
D(on)xRDS(on)maxID
=5 A 10 S
VDS=25V f=1MHz VGS= 0 1480
210
25
µA
µ
pF
pF
pF
A
2/7
STB10NC50-1
ELECTRICAL CHARACTERISTICS
(continued)
SWITCHINGON
Symbol Parameter Test Con ditions Min. Typ. M ax. Unit
t
d(on)
Q
Q
Q
Turn-on Time
t
Rise Tim e
r
Total Gate Charge
g
Gat e- Source Charge
gs
Gate-Drain Charg e
gd
VDD= 250 V ID=5A
R
=4.7
G
Ω
VGS=10V
VDD= 160 V ID=10A VGS=10V 41
29
16
49 nC
12
19
SWITCHINGOFF
Symbol Parameter Test Con ditions Min. Typ. M ax. Unit
t
r(Voff)
t
t
Off -voltage Rise Time
Fall Time
f
Cross-ov er T ime
c
VDD= 160 V ID=10A
=4.7 ΩVGS=10V
R
G
16
18
29
SOURCEDRAINDIODE
Symbol Parameter Test Con ditions Min. Typ. M ax. Unit
I
SD
I
SDM
V
SD
t
Q
I
RRM
(∗) Pulsed:Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operatingarea
Source-drain C urrent
(•)
Source-drain C urrent
10.6
42.4
(pulsed)
(∗) Forwar d O n V oltage ISD=10 A VGS=0 1.6 V
Reverse Recover y
rr
Time
Reverse Recover y
rr
=10 A d i/ dt = 100 A/µs
I
SD
=50V Tj= 150oC
V
DD
560
4.9
Charge
Reverse Recover y
17.5
Current
ns
ns
nC
nC
ns
ns
ns
A
A
ns
nC
A
3/7
STB10NC50-1
Fig. 1:
UnclampedInductive Load TestCircuit
Fig. 3: SwitchingTimes Test CircuitsFor
ResistiveLoad
Fig. 2:
UnclampedInductive Waveform
Fig. 4: Gate Chargetest Circuit
Fig. 5:
Test CircuitFor InductiveLoad Switching
And Diode Recovery Times
4/7
TO-262 (I2PAK) MECHANICAL DATA
STB10NC50-1
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.3 4.6 0.169 0.181
A1 2.49 2.69 0.098 0.106
B 0.7 0.93 0.027 0.036
B1 1.2 1.38 0.047 0.054
B2 1.25 1.4 0.049 0.055
C 0.45 0.6 0.017 0.023
C2 1.21 1.36 0.047 0.053
D 8.95 9.35 0.352 0.368
e 2.44 2.64 0.096 0.104
E 10 10.28 0.393 0.404
L 13.2 13.5 0.519 0.531
L1 3.48 3.78 0.137 0.149
L2 1.27 1.4 0.050 0.055
mm inch
CA1
A
C2
B2
B
e
E
L1
L2
D
L
P011P5/C
5/7
STB10NC50-1
TO-263(D2PAK) MECHANICALDATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.3 4.6 0.169 0.181
A1 2.49 2.69 0.098 0.106
B 0.7 0.93 0.027 0.036
B2 1.25 1.4 0.049 0.055
C 0.45 0.6 0.017 0.023
C2 1.21 1.36 0.047 0.053
D 8.95 9.35 0.352 0.368
E 10 10.28 0.393 0.404
G 4.88 5.28 0.192 0.208
L 15 15.85 0.590 0.624
L2 1.27 1.4 0.050 0.055
L3 1.4 1.75 0.055 0.068
mm inch
E
A
C2
6/7
L2
D
L
L3
B2
B
A1
C
G
P011P6/C
STB10NC50-1
Information furnishedis believed tobeaccurateand reliable.However, STMicroelectronics assumesno responsibilityfor the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationmentioned in this publicationare
subjecttochange without notice. This publicationsupersedesandreplaces all information previouslysupplied. STMicroelectronicsproducts
are not authorized for use as critical components in life supportdevicesor systemswithout express written approval of STMicroelectronics.
The STlogo is a trademark of STMicroelectronics
1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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