SGS Thomson Microelectronics ST93C67, ST93C66 Datasheet

4K (256 x 16 or 512 x 8)SERIALMICROWIREEEPROM

1 MILLIONERASE/WRITE CYCLES, with
40 YEARS DATARETENTION

DUALORGANIZATION:256 x 16 or 512 x 8
BYTE/WORDand ENTIRE MEMORY

PROGRAMMING INSTRUCTIONS
SELF-TIMED PROGRAMMINGCYCLEwith

AUTO-ERASE
READY/BUSY SIGNAL DURING

PROGRAMMING
SINGLESUPPLY VOLTAGE:
– 4.5V to 5.5V for ST93C66version
– 3V to 5.5V for ST93C67 version
SEQUENTIAL READ OPERATION
5ms TYPICALPROGRAMMING TIME

ST93C66and ST93C67are replaced by the
M93C66

8

1

PSDIP8 (B)

0.4mm Frame

Figure 1. Logic Diagram

ST93C66
ST93C67

NOT FOR NEW DESIGN

8

1

SO8 (CM)

150mil Width

DESCRIPTION

This specification covers a range of 4K bit serial
EEPROMproducts, the ST93C66specified at 5V
± 10%and theST93C67 specifiedat 3V to 5.5V.In
the text, products are referred to asST93C66.

The ST93C66 is a 4K bit Electrically Erasable
ProgrammableMemory(EEPROM)fabricatedwith
SGS-THOMSON’sHighEnduranceSinglePolysili­con CMOS technology. The memory is accessed
through a serial input (D) and output (Q). The 4K
bit memory is divided into either 512 x 8 bit bytes
or 256 x 16 bit words. The organization may be
selectedby a signalappliedon the ORG input.

Table 1. Signal Names

S Chip Select Input
D Serial Data Input
Q Serial Data Output
C Serial Clock
ORG Organisation Select
V

CC

V

SS

Supply Voltage
Ground

ORG

V

CC

D

C
S

ST93C66
ST93C67

V

SS

Q

AI01252B

July 1997 1/13

This isinformation on a product still in production but not recommended for new designs.

ST93C66,ST93C67

Figure2A. DIPPin Connections

ST93C66
ST93C67

SV

1
2

D

3

Q

4

Warning: DU = Don’t Use Warning: DU = Don’t Use

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

T

STG

T

LEAD

V

V

CC

V

ESD

Notes: 1. Exceptfor the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”

Ambient Operating Temperature –40 to 125 °C

A

Storage Temperature –65 to 150 °C
Lead Temperature,Soldering (SO8 package)

Input or Output Voltages(Q = VOHor Hi-Z) –0.3 to VCC+0.5 V

IO

Supply Voltage –0.3 to 6.5 V
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

may cause permanent damage to the device. Theseare stress ratings only and operation of thedevice at these or any other
conditions abovethose indicated in the Operating sectionsof this specification is not implied. Exposure toAbsolute Maximum
Rating conditions for extended periods may affect device reliability.Refer also to the SGS-THOMSON SURE Programand other
relevant quality documents.

2. MIL-STD-883C, 3015.7(100pF, 1500 Ω).

3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).

8
7
6
5

AI01253B

CC

DUC
ORG
V

SS

(1)

(PSDIP8 package)

Figure2B. SO Pin Connections

ST93C66
ST93C67

1

SV

2

D

3

Q

4

40 sec
10 sec

(2)

(3)

8
7
6
5

AI01254C

215
260

7000 V
1000 V

CC

DUC
ORG
V

SS

°C

DESCRIPTION (cont’d)
The memory is accessed by a set of instructions

which includes Read a byte/word, Write a
byte/word,Erasea byte/word,Erase All and Write
All. ARead instructionloads theaddressof the first
byte/word to be read into an internal address
pointer.The data containedat this addressis then
clocked out serially. The address pointer is auto­maticallyincrementedafterthe data is output and,
if the Chip Select input (S) is held High, the
ST93C66 can output a sequential stream of data
bytes/words.In this way,the memorycan be read
as a data stream from 8 to 4096 bits long, or
continuouslyas the address counterautomatically
rolls over to ’00’ when the highest address is
reached.Programming is internallyself-timed(the
external clock signal on C input may be discon-

2/13

nectedorleftrunningafterthestart ofa Writecycle)
and does not require an erase cycle prior to the
Write instruction. The Write instruction writes 8 or
16 bits at one timeinto oneof the512 bytesor256
words. After the startof the programming cycle, a
Busy/Readysignal is available on the Data output
(Q)when Chip Select (S) is driven High.

The design of the ST93C66 and the High Endur­anceCMOStechnologyusedforitsfabricationgive
an Erase/Write cycle Endurance of 1,000,000 cy­clesand a data retention of 40 years.

TheDU (Don’tUse) pindoesnotaffectthefunction
of the memory and it is reserved for use by SGS­THOMSON duringtestsequences.The pinmaybe
left unconnectedor may be connected to V
V

. Direct connection of DU to VSSis recom-

SS

CC

or

mended for the lowest standby power consump­tion.

ST93C66, ST93C67

AC MEASUREMENT CONDITIONS

Figure 3. AC Testing Input Output Waveforms

Input Rise and Fall Times ≤ 20ns
Input Pulse Voltages 0.4V to 2.4V
Input TimingReference Voltages 1V to 2.0V
Output TimingReference Voltages 0.8V to 2.0V

Note that Output Hi-Z is defined as the point where data

2.4V

0.4V

2V
1V

INPUT OUTPUT

is no longer driven.

Table 3. Capacitance

(1)

(TA=25°C, f = 1 MHz )

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

Note: 1. Sampledonly, not 100% tested.

Input Capacitance VIN=0V 5 pF
Output Capacitance V

=0V 5 pF

OUT

Table 4. DC Characteristics

= 0 to70°C or –40 to 85°C; VCC= 4.5V to 5.5V or 3V to 5.5V)

(T

A

2.0V

0.8V

AI00815

Symbol Parameter TestCondition Min Max Unit

I

I

I

CC1

V

V

V

V

I

LI

LO

CC

IL

IH

OL

OH

Input Leakage Current 0V ≤ VIN≤ V

Output Leakage Current

0V ≤ V

≤ VCC,

OUT

Q inHi-Z

CC

±2.5 µA

±2.5 µA

Supply Current (TTL Inputs) S = VIH, f = 1 MHz 3 mA
Supply Current (CMOS Inputs) S = V

Supply Current (Standby)

Input Low Voltage (D, C, S)

Input High Voltage (D, C, S)

Output Low Voltage

Output High Voltage

, f = 1 MHz 2 mA

IH

,C=VSS,

S=V

SS

ORG = V

V

CC

3V ≤ V
V

CC

3V ≤ V

I

OL

I

I

OH

I

OH

or V

SS

CC

=5V±10% –0.3 0.8 V

≤ 4.5V –0.3 0.2V

CC

=5V±10% 2 VCC+1 V

≤ 4.5V 0.8 V

CC

CC

= 2.1mA 0.4 V

=10µA 0.2 V

OL

= –400µA 2.4 V

= –10µAV

–0.2 V

CC

50 µA

VCC+1 V

CC

V

3/13

ST93C66,ST93C67

Table 5. AC Characteristics

(T

= 0 to70°C or –40 to 85°C; VCC= 4.5V to 5.5V or 3V to 5.5V)

A

Symbol Alt Parameter Test Condition Min Max Unit

t

SHCH

t

CLSH

t

DVCH

t

CHDX

t
t

t

t

Chip Select High to Clock High 50 ns

CSS

Clock Low to Chip SelectHigh 100 ns

SKS

Input Valid to Clock High 100 ns

DIS

Temp.Range: grade 1 100 ns

Clock High to Input Transition

DIH

Temp.Range:

grades3, 6

200 ns

t

CHQL

t

CHQV

t

CLSL

t

SLCH

t

SLSH

t

SHQV

t

SLQZ

t

CHCL

t

CLCH

t

W

f

C

Notes: 1. Chip Selectmust bebrought low for a minimumof 250 ns(t

2. The Clock frequency specification calls for a minimum clock period of 1 µs, therefore the sum of the timings t

t
t
t

Clock High to Output Low 500 ns

PD0

Clock High to Output Valid 500 ns

PD1

Clock Low to Chip SelectLow 0 ns

CSH

Chip Select Low to Clock High 250 ns

t

Chip Select Low to Chip Select High Note 1 250 ns

CS

t

Chip Select High to Output Valid 500 ns

SV

t

Chip Select Low to Output Hi-Z 200 ns

DF

t
t

must be greater or equal to 1 µs. For example, ift

Clock High to Clock Low Note 2 250 ns

SKH

Clock Low to Clock High Note 2 250 ns

SKL

t

Erase/Write Cycle time 10 ms

WP

f

Clock Frequency 0 1 MHz

SK

is 250 ns, then t

CHCL

) between consecutive instruction cycles.

SLSH

must be at least 750 ns.

CLCH

Figure4. Synchronous Timing, Start and Op-CodeInput

CHCL+tCLCH

4/13

tCLSH tCHCL

C

tSHCH

S

tDVCH

D

OP CODE OP CODESTART

OP CODE INPUTSTART

tCLCH

tCHDX

AI01428