SGS Thomson Microelectronics ST92195B, ST92195 Datasheet
ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
■ Register File based 8/16 bit Core Architecture
with RUN, WFI, SLOW and HALT modes
■ 0°C to +70°C operating temperature range
■ Up to 24 MHz. operation @ 5V±10%
■ Min. instruction cycle time: 165nsat 24 MHz.
■ 32, 48, 56 or 64 Kbytes ROM
■ 256 bytesRAM of Register file (accumulators or
index registers)
■ 256 bytes of on-chip static RAM
■ 2, 6 or 8 Kbytes of TDSRAM (Teletext and
Display Storage RAM)
■ 28 fully programmable I/O pins
■ Serial Peripheral Interface
■ Flexible Clock controller for OSD, Data Slicer
and Core clocks running from a single low
frequency external crystal.
■ Enhanced display controller with 26 rows of
40/80 characters
– Serial and Parallel attributes
– 10x10 dot matrix, 512 ROM characters, defin-
able by user
– 4/3 and 16/9 supported in 50/60Hz and 100/
120 Hz mode
– Rounding, fringe,doublewidth, double height,
scrolling, cursor, full background color, halfintensity color, translucency and half-tone
modes
■ Teletext unit, including Data Slicer, Acquisition
Unit and up to 8 Kbytes RAM for data storage
■ VPS and Wide Screen Signalling slicer (on
some devices)
■ Integrated Sync Extractor and Sync Controller
■ 14-bit Voltage Synthesis for tuning reference
voltage
■ Up to 6 external interrupts plus one Non-
Maskable Interrupt
■ 8 x 8-bit programmable PWM outputs with 5V
open-drain or push-pull capability
■ 16-bit watchdog timer with 8-bit prescaler
■ One 16-bit standard timer with 8-bit prescaler
■ 4-channel A/D converter; 5-bit guaranteed
ST92195B
32-64K ROM HCMOS MCU WITH
DATA BRIEFING
PSDIP56
TQFP64
See end of document for ordering information
■ Rich instruction set and 14 addressing modes
■ Versatile development tools, including
Assembler, Linker, C-compiler, Archiver,
Source Level Debugger and hardware
emulators with Real-Time Operating System
available from third parties
■ Pin-compatible EPROM and OTP devices
available
Device Summary
Device
ST92195B1 32K ROM 2K Yes
ST92195B2 32K ROM 6K No
ST92195B3 32K ROM 6K Yes
ST92195B4 48K ROM 6K Yes
ST92195B5 48K ROM 8K Yes
ST92195B6 56K ROM 8K Yes
ST92195B7 64K ROM 8K Yes
ST92T195B7 64K OTP 8K Yes
ST92E195B7 64K EPROM 8K Yes
Program
Memory
TDS
RAM
VPS/
WSS
Package
PSDIP56/
TQFP64
CSDIP56
/CQFP64
Rev. 2.5
January 2000 1/22
1
ST92195B - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST92195B microcontroller is developedand
manufactured by STMicroelectronics using a proprietary n-well HCMOS process. Its performance
derives from the use of a flexible 256-register programming model for ultra-fast context switching
and real-time event response. The intelligent onchip peripherals offload the ST9 core from I/O and
data management processing tasks allowing critical application tasks to get the maximum use of
core resources.The ST92195B MCUsupports low
power consumption and low voltage operation for
power-efficient and low-cost embedded systems.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File and the
Interrupt controller.
The general-purpose registers can be used as accumulators, index registers, or address pointers.
Adjacent registerpairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory/register and memory/memory exchanges.
Two basic addressable spaces are available: the
Memory space and the Register File, which includes the control and status registers of the onchip peripherals.
1.1.2 Power Saving Modes
To optimize performance versus power consumption, a range of operating modes can be dynamically selected.
Run Mode. This is the full speed execution mode
with CPU and peripherals running at themaximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).
Wait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution until an interrupt request is acknowledged. During
WFI, the CPU clock is halted while the peripheral
and interrupt controller keep running at a frequen-
cy programmable via the CCU. In this mode, the
power consumption of the device can be reduced
by more than 95% (Low power WFI).
Halt Mode. When executing the HALT instruction,
and if the Watchdog is not enabled, the CPU and
its peripherals stop operating and the status of the
machine remains frozen (the clock is also
stopped). A reset is necessary to exit from Halt
mode.
1.1.3 I/O Ports
Up to 28 I/O lines are dedicated to digital Input/
Output. Theselines are grouped into up to five I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
timer and output,analog inputs,external interrupts
and serial or parallel I/O.
1.1.4 TV Peripherals
A set of on-chip peripherals form a complete system for TV set and VCR applications:
– Voltage Synthesis
– VPS/WSS Slicer
– Teletext Slicer
– Teletext Display RAM
– OSD
1.1.5 On Screen Display
The human interface is provided by the On Screen
Display module, this can produce up to 26 lines of
up to 80 characters from a ROM defined 512 character set. The character resolution is 10x10 dot.
Four character sizes are supported. Serial attributes allow the user to select foreground and
background colors, charactersizeand fringe background. Parallel attributes can be used to select
additional foreground and background colors and
underline on a character by character basis.
1.1.6 Teletext and Display Storage RAM
The internal Teletext and Display storage RAM
can be usedtostore Teletext pages aswell as Display parameters.
2/22
INTRODUCTION (Cont’d)
1.1.7 Teletext, VPS and WSS Data Slicers
The three on-board data slicers using a single external crystal are used to extract the Teletext, VPS
and WSS information from the video signal. Hardware Hamming decoding is provided.
1.1.8 Voltage Synthesis Tuning Control
14-bit Voltage Synthesis using the PWM (Pulse
Width Modulation)/BRM (Bit Rate Modulation)
technique canbeused togenerate tuning voltages
for TV set applications. The tuning voltage is output on one of two separate output pins.
1.1.9 PWM Output
Control of TV settings can be made with up to
eight 8-bitPWMoutputs,with a maximumfrequency of 23,437Hz at 8-bit resolution (INTCLK = 12
MHz). Low resolutions withhigher frequency operation can be programmed.
ST92195B - GENERAL DESCRIPTION
1.1.10 Serial Peripheral Interface (SPI)
The SPI bus is used to communicate with external
devices v ia the SPI, or I C bus communication
standards. The SPI uses a single data line for data
input and output. A se cond l ine is used for a synchronous c lock signal.
1.1.11 Standard Timer (STIM)
The ST92195B has one Standard Timer (STIM0)
that includes a programmable 16-bit down counter
and an associated 8-bit prescaler with Single and
Continuous counting modes.
1.1.12 Analog/Digital Converter (ADC)
In addition there is a 4-channel Analog to Digital
Converter with integral s ample and hold, fast
5.75µs conversion time and6-bit guaranteed resolution.
3/22
ST92195B - GENERAL DESCRIPTION
INTRODUCTION (Cont’d)
Figure 1. ST92195B Block Diagram
NMI
INT[7:4]
INT2
INT0
OSCIN
OSCOUT
RESET
RESETO
SDO/SDI
SCK
MCFM
STOUT
VSO[2:1]
Up to 64
Kbytes ROM
256 bytes
RAM
Up to 8
Kbytes
TDSRAM
256 bytes
Register File
Management
ST9+ CORE
WATCHDOG
TIMING AND
CLOCK CTRL
STANDARD
VOLTAGE
SYNTHESIS
TRI
8/16-bit
CPU
MMU
Interrupt
RCCU
16-BIT
TIMER/
SPI
TIMER
MEMORY BUS
REGISTER BUS
I/O
PORT 0
I/O
PORT 2
I/O
PORT 3
I/O
PORT 4
I/O
PORT 5
DATA
SLICER
& ACQUI-
SITION
UNIT
SYNC.
EXTRAC-
TION
VPS/WSS
DATA
SLICER
ADC
SYNC
CONTROL
ON
SCREEN
DISPLAY
PWM
D/A CON-
VERTER
8
6
4
8
2
FREQ.
MULTIP.
P0[7:0]
P2[5:0]
P3[7:4]
P4[7:0]
P5[1:0]
TXCF
CVBS1
WSCR
WSCF
CVBS2
AIN[4:1]
EXTRG
VSYNC
HSYNC/CSYNC
CSO
PXFM
R/G/B/FB
TSLU
HT
PWM[7:0]
4/22
All alternate functions
(Italic characters)
are mapped on Ports 0,2, 3, 4 and 5
1.2 PIN DESCRIPTION
Figure 2. 64-Pin Package Pin-Out
ST92195B - GENERAL DESCRIPTION
GND
AIN4/P0.2
P0.1
P0.0
CSO/RESET0/P3.7
P3.6
P3.5
P3.4
FB
SDO/SDI/P5.1
INT2/SCK/P5.0
V
DD
JTDO
VDDP0.3
P0.4
P0.5
P0.6
P0.7
RESET
P2.0/INT7
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
64
1
B
G
R
16
16
N.C.
N.C.
WSCF
/WSCR
PP
V
AVDD3
MCFM
TEST0
JTCK
TXCF
AVDD2
CVBSO
JTMS
CVBS2
OSCIN
OSCOUT
32
AGND
CVBS1
DD
V
48
V
SS
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSLU/HT
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC/CSYNC
AVDD1
PXFM
JTRST0
GND
N.C.
N.C.
N.C. = Not connected
5/22
ST92195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
RESET
tialised by the Reset signal. With the deactivation
of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.
R/G/B
outputs.
FB
VDDMain power supply voltage (5V±10%, digital)
WSCF, WSCR Analog pins for the VPS/WSS slic-
er . These pins must be tied to ground or not connected.
VPP: On EPROM/OTP devices, the WSCR pin is
replaced by VPPwhich istheprogramming voltage
pin. VPPshould be tied to GND in user mode.
MCFM Analog pin for the display pixel frequency
multiplier.
OSCIN, OSCOUT
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the
input of the oscillator inverter and internal clock
generator; OSCOUT is the output of the oscillator
inverter.
Reset
(input, active low). The ST9+ is ini-
Red/Green/Blue
Fast Blanking
. Video color analog DAC
. Video analog DAC output.
Oscillator
(input and output).
VSYNC
Vertical Sync
. Vertical video synchronisa-
tion input to OSD. Positive or negative polarity.
HSYNC/CSYNC
Horizontal/Composite sync
. Horizontal or composite video synchronisation input to
OSD. Positive or negative polarity.
PXFM Analog pin for the Display Pixel Frequency
Multiplier
AVDD3
Analog VDDof PLL.
This pin must be tied
to VDDexternally.
GND Digital circuit ground.
AGND Analog circuit ground (must be tied exter-
nally to digital GND).
CVBS1 Composite video input signal for the Tele-
text slicer and sync extraction.
CVBS2 Composite video input signal for the VPS/
WSS slicer. Pin AC coupled.
AVDD1, AVDD2 Analog power supplies (must be
tied externally to AVDD3).
TXCF Analog pin for the Teletext slicer line PLL.
CVBSO, JTDO, JTCK Test pins: leave floating.
TEST0 Test pins: must betied to AVDD2.
JTRST0 Test pin:must be tied to GND.
Figure 3. 56-Pin Package Pin-Out
INT7/P2.0
AIN4/P0.2
CSO/RESET0/P3.7
SDI/SDO/P5.1
SCK/INT2/P5.0
V
PP
RESET
P0.7
P0.6
P0.5
P0.4
P0.3
P0.1
P0.0
P3.6
P3.5
P3.4
FB
V
DD
JTDO
WSCF
/WSCR
AVDD3
TEST0
MCFM
JTCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
B
16
G
17
R
18
19
20
21
22
23
24
25
26
27
28
P2.1/INT5/AIN1
56
P2.2/INT0/AIN2
55
54
P2.3/INT6/VS01
53
P2.4/NMI
52
P2.5/AIN3/INT4/VS02
51
OSCIN
50
OSCOUT
49
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
48
P4.5/PWM5
47
46
P4.4/PWM4
45
P4.3/PWM3/TSLU/HT
44
P4.2/PWM2
43
P4.1/PWM1
42
P4.0/PWM0
41
VSYNC
40
HSYNC/CSYNC
39
AVDD1
38
PXFM
37
JTRSTO
36
GND
35
AGND
34
CVBS1
33
CVBS2
32
JTMS
31
AVDD2
30
CVBSO
29
TXCF
6/22
ST92195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
Figure 4. ST92195B Required External components (56-pin package)
+5V
1µF
C2
S1
RST
C4
C6
C11
4.7nF
C13
10µF
100nF
22pF
R3
10k
R1
D1
1N4148
L2
10uH
B
G
R
FB
100nF
C9
5.6k
U1
P20
1 56
P2.0/INT7 P2.1/INT5/AIN1
2
P07
P06
P05
P04
P03
P02
P01
P00
P37
P36
P35
P34
P51
P50
RESETN
3
P0.7
4
P0.6
5
P0.5
6
P0.4
7
P0.3
8
P0.2/AIN4
9
P0.1
10
P0.0
11
P3.7/RESET0/CSO
12
P3.6
13
P3.5
14
P3.4
15
B
16
G
17
R
18
FB
19
P5.1/SDI/SDO
20
P5.0/SCK/INT2
21
VDD
22
JTDO
23
WSCF
24
WSCR
25
AVDD3
26
TEST0
27
MCFM
28
JTCK
SDIP56
ST92195B
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.5/AIN3/INT4/VS02
P4.7/PWM7/EXTRG/STOUT
P4.3/PWM3/TSLU/HT
HSYNC/CSYNC
P2.4/NMI
OSCIN
OSCOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
AVDD1
PXFM
JTRST0
GND
AGND
CVBS1
CVBS2
JTMS
AVDD2
CVBSO
TXCF
82pF
VSYNC
HSYNC
C1
Y1
4Mhz
C3
C12
C14
C15
82pF
R2
470nF
82pF
100nF
R4
C8
5.6k
15k
+5V
L1
10uH
C5
100nF
10µF
C7
22pF
4.7nF
C10
CVBS
2.2nF
C16
P21
P22
55
P23
54
P24
53
P25
52
51
50
P47
49
P46
48
P45
47
P44
46
P43
45
P42
44
P41
43
P40
42
41
40
39
38
37
36
35
34
33
32
31
30
29
7/22
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