SGS Thomson Microelectronics ST7FLITE29F2M6, ST7FLITE29F2B6, ST7FLITE29, ST7FLITE25F2M6, ST7FLITE25F2B6 Datasheet

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August 2003 1/131

Rev. 2.0

ST7LITE2

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,

DATA EEPROM, ADC, TIMERS, SPI

■ Memories

– 8 Kbytes single voltag e Flas h Pro gram mem-

ory with read-out protection, In-Circuit Programming and In-Application programming (ICP and IAP). 10K write/erase cycles guar-

anteed, data retention: 20 years at 55°C. – 384 bytes RAM – 256 bytes data EEPROM with read-out pro-

tection. 300K write/erase cycles guarant eed,

data retention: 20 years at 55°C.

■ Clock , Res et and Supp ly Managem e n t

– Enhanced reset system – Enhanced low voltage supervisor (LVD) for

main supply and an auxiliary voltage detector

(AVD) with interrupt capability for implement-

ing safe power-down procedures – Clock sources: Internal 1% RC oscillator,

crystal/ceramic resonator or external clock – Internal 32-MHz input clock for Auto-reload

timer – Optional x4 or x8 PLL for 4 or 8 MHz internal

clock – Five Power Saving Modes: Halt, Active-Halt,

Wait and Slow, Auto Wake Up From Halt

■ I/O Ports

– Up to 15 multifunctional bidirectional I/O lines –7 high sink outputs

■ 4 Timers

– Configurable Watchdog Timer – Two 8-bit Lite Timers with prescaler,

1 realtime base and 1 input capture – One 12-bit Auto-reload Timer with 4 PWM

outputs, input capture and output compare functions

■ 1 Communication Interface

– SPI synchronous serial interface

■ Interrupt M ana g em e n t

– 10 inter r u pt vecto r s plu s TRAP an d RESET – 15 external interrupt lines (on 4 vectors)

■ A/D Converter

– 7 input channels – Fixed gain Op-amp – 13-bit resolution for 0 to 430 mV (@ 5V V

)

– 10-bit resolution for 430 mV to 5V (@ 5V V

)

■ Instruction Set

– 8-bit data manipulation – 63 basic instruct ions – 17 main addressing modes – 8 x 8 unsigned multiply instructions

■ Development Tools

– Full hardware/software development package – DM (Debug Module)

Device Summary

DIP20

SO20

300”

Features ST7LITE20 ST7LITE25 ST7LITE29

Program memory - bytes 8K RAM (stack) - byte s 384 (128) Data EEPROM - bytes - - 256

Peripherals

Lite Timer with Watchdog,

Autoreload Timer, SPI,

10-bit ADC with Op-Amp

Lite Timer with Watchdog,

Autoreload Timer with 32-MHz input clock,

SPI, 10-bit ADC with Op-Amp

Operat ing Supply 2.4V to 5.5V CPU Frequency

Up to 8Mhz

(w/ ext OS C up to 16 MHz)

Up to 8Mhz (w/ ext OSC up to 16MHz

and int 1MHz RC 1% PLLx 8/4MHz)

Operat i ng T em perature -40°C to +85°C

Packages SO20 300”, DIP20

Table of Cont ents

131

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1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.4 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.5 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.6 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table of Cont ents

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10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

11.2 12-BIT AUTORELOAD TIMER 2 (AT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.3 LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

11.5 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 114

13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

14.2 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 123

15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

15.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

16.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

16.2 ADC CONVERSION SPURIOUS RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

16.3 A/ D CONVERTER ACCURACY FOR FIRST CONVERSION . . . . . . . . . . . . . . . . . . . 129

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17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet

Please also pay special attention to the Section “IMPORTANT NOTES” on page 129.

ST7LITE2

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1 INTRODUCTION

The ST7LITE2 is a member of the ST7 m icrocontroller family. All ST7 devices are based on a common industry-standard 8-bit core, feat uring an enhanced instruction set.

The ST7LITE2 features FLASH memory with byte-by-byte In-Circuit Programming (ICP) and InApplication Programming (IAP) capability.

Under software control, the ST 7LITE2 device can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to

software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

For easy reference, all parametric data are located in section 13 on page 91.

The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD). F or a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.

Figure 1. General B lock Diag ram

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSC1 OSC2

RESET

PORT A

Internal CLOCK

CONTROL

RAM

(384 Bytes)

PA7:0

(8 bits)

POWER

SUPPLY

PROGRAM

(8K Bytes)

LVD

MEMORY

PLL x 8

Ext.

1MHz

PLL

Int.

1MHz

8-Bit

LITE TIMER 2

PORT B

SPI

PB6:0

(7 bits)

DATA EEPROM

(256 Bytes)

1% RC

OSC

16MHz

ADC

+ OpAmp

12-Bit

Auto-Reload

TIM E R 2

CLKIN

/ 2

or PLL X4

8MHz -> 32MHz

WATCHDOG

Debug Modul e

ST7LITE2

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2 PIN DESCRIPTION

Figure 2. 20-Pin SO Package Pinout

Figure 3. 20-Pin DIP Package Pinout

20 19 18 17 16 15 14 13

1 2 3 4 5 6 7 8

AIN5/PB5

CLKIN/AIN4/PB4

MOSI/AIN3/PB3

MISO/AIN2/PB2

SCK/AIN1/PB1

/AIN0/PB0

OSC1/CLKIN

OSC2

PA5

(HS)/ATPWM3/ICCDATA

PA4

(HS)/ATPWM2

PA3

(HS)/ATPWM1

PA2

(HS)/ATPWM0

PA1

(HS)/ATIC

PA0

(HS)/LTIC

(HS) 20mA high sink capability eix associated external interrupt vector

12 11

9 10

AIN6/PB6

PA7(HS)

PA6/MCO/ICCCLK/BREAK

RESET

ei3

ei2

ei0

ei1

20 19 18 17 16 15 14 13

1 2 3 4 5 6 7 8

MISO/AIN2/PB2 MOSI/AIN3/PB3

ATPWM2/PA4(HS)

ATPWM3/ICCDATA/PA5(HS)

MCO/ICCCLK/BREAK/PA6

PA7(HS)

AIN6/PB6

AIN5/PB5

SCK/AIN1/PB1 SS

/AIN0/PB0

PA0(HS)/LTIC

OSC2

OSC1/CLKIN

RESET

(HS) 20mA high sink capability eix associated external interrupt vector

12 11

9 10

ATPWM1/PA3(HS)

PA2(HS)/ATPWM0

PA1(HS)/ATIC

CLKIN/AIN4/PB4

ei3

ei2

ei1

ei0

ST7LITE2

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PIN DESCRIPTION (Cont’d)

Legend / Abbreviations for Table 1 :

Type: I = input, O = output, S = supply In/Output le v el: C

= CMOS 0.3VDD/0.7VDD with input trigger

Output level: HS = 20mA high sink (on N-buffer only)

Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog – Output : OD = open drain, PP = push-pull

The RESET co nf igurati on of eac h pin i s shown in b old whic h is va lid as l ong as the d evice is i n rese t sta te .

Table 1. Device Pin Description

Pin No.

Pin Name

Type

Level Port / Control

Main

Function

(after reset)

Alternate Function

SO20

DIP20

Input

Output

Input Output

float

wpu

int

ana

116V

S Ground

217V

S Main power supply

3 18 RESET

I/O C

Top priority non maskable interrupt (active low)

4 19 PB0/AIN0/SS

I/O C

ei3

XXXPort B0

ADC Analog Input 0 or SPI Slave Select (active low)

5 20 PB1/AIN1/SCK I/O C

X XXXPort B1

ADC Analog Input 1 or SPI Serial Clock

6 1 PB2/AIN2/MISO I/O C

X XXXPort B2

ADC Analog Input 2 or SPI Master In/ Slave Out Data

7 2 PB3/AIN3/MOSI I/O C

ei2

XXXPort B3

ADC Analog Input 3 or SPI Master Out / Slave In Data

8 3 PB4/AIN4/CLKIN I/O C

X XXXPort B4

ADC Analog Input 4 or External clock input

9 4 PB5/AIN5 I/O C

X XXXPort B5 ADC Analog Input 5

10 5 PB6/AIN6 I/O C

X XXXPort B6 ADC Analog Input 6

11 6 PA7 I/O C

HS X ei1 X X Port A7

12 7

PA6 /MCO/ ICCCLK/BREAK

I/O C

X ei1 XXPort A6

Main Clock Output or In Circuit Communication Clock or External BREAK

Caution: During reset, this pin must be held at high level to avoid entering ICC mode unexpectedly (this is guaranteed by the internal pull-up if the application leaves the pin floating).

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13 8

PA5 /ATPWM3/ ICCDATA

I/O CTHS X

ei1

XXPort A5

Auto-Reload Timer PWM3 or In Circuit Communication Data

14 9 PA4/ATPWM2 I/O C

HS X XXPort A4 Auto-Reload Timer PWM2

15 10 PA3/ATPWM1 I/O C

HS X

ei0

XXPort A3 Auto-Reload Timer PWM1

16 11 PA2/ATPWM0 I/O C

HS X XXPort A2 Auto-Reload Timer PWM0

17 12 PA1/ATIC I/O C

HS X XXPort A1

Auto-Reload Timer Input Capture

18 13 PA0/LTIC I/O C

HS X XXPort A0 Lite Timer Input Capture

19 14 OSC2 O Resonator oscillator inverter output 20 15 OSC1/CLKIN I

Resonator oscillator inverter input or External clock input

Pin No.

Pin Name

Type

Level Port / Control

Main

Function

(after reset)

Alternate Function

SO20

DIP20

Input

Output

Input Output

float

wpu

int

ana

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3 REGISTER & MEMORY MAP

As sho wn i n Figure 4, the MCU is capable of ad- dressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, 384 bytes of RAM, 256 bytes of data EEPROM and 8 Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 180h to 1FFh.

The highest address b ytes contain the user res et and interrupt vectors.

The Flash mem ory contains two sectors (see Fig -

ure 4) mapped in the upper part of the ST7 ad-

dressing space so the res et and interrupt vectors are located in Sector 0 (F000h-FFFFh).

The size of Flash Sector 0 and other device options are configurable by Option byte (refer to sec-

tion 15.1 on page 123).

IMPORTANT: Memory locations marked as “Reserved” must ne ver be accessed. Ac cessing a reseved area can have u npredict able effects on t he device.l

Figure 4. Me m ory M a p

0000h

RAM

Flash Memory

(8K)

Interrupt & Reset Vectors

HW Registers

0080h

007Fh

0FFFh

(see Table 2)

1000h

10FFh

FFE0h

FFFFh

(see Table 5)

0200h

Reserved

01FFh

Short Addressing RAM (zero page)

128 Bytes Stack

0180h

01FFh

0080h

00FFh

(384 Bytes)

Data EEPROM

(256 Bytes)

E000h

1100h

DFFFh

Reserved

FFDFh

16-bit Addressing

RAM

0100h

017Fh

1 Kbyte

7 Kbytes

SECTOR 1

SECTOR 0

8K FLASH

FFFFh

FC00h

FBFFh

E000h

PROGRAM MEMORY

1000h

1001h

RCCR0 RCCR1

see section 7.1 on page 23

FFDEh

FFDFh

RCCR0 RCCR1

see section 7.1 on page 23

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Table 2. Hardware Register M ap

Address Block Register Label Register Name Reset Status Remarks

0000h 0001h 0002h

Port A

PADR PADDR PAOR

Port A Data Register Port A Data Direction Register Port A Option Register

FFh

00h 40h

R/W R/W R/W

0003h 0004h 0005h

Port B

PBDR PBDDR PBOR

Port B Data Register Port B Data Direction Register Port B Option Register

FFh

00h 00h

R/W R/W R/W

0006h 0007h

Reserved Area (2 bytes)

0008h 0009h 000Ah 000Bh 000Ch

LITE

TIMER 2

LTCSR2 LTARR LTCNTR LTCSR1 LTICR

Lite Timer Control/Status Register 2 Lite Timer Auto-reload Register Lite Timer Counter Register Lite Timer Control/Status Register 1 Lite Timer Input Capture Register

0Fh

00h 00h

0X00 0000h

xxh

R/W R/W Read Only R/W Read Only

000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h

AUTO-

RELOAD

TIMER 2

ATCSR CNTRH CNTRL ATRH ATRL PWMCR PWM0CSR PWM1CSR PWM2CSR PWM3CSR DCR0H DCR0L DCR1H DCR1L DCR2H DCR2L DCR3H DCR3L ATICRH ATICRL TRANCR BREAKCR

Timer Control/Status Register Counter Register High Counter Register Low Auto-Reload Register High Auto-Reload Register Low PWM Output Control Register PWM 0 Control/Status Register PWM 1 Control/Status Register PWM 2 Control/Status Register PWM 3 Control/Status Register PWM 0 Duty Cycle Register High PWM 0 Duty Cycle Register Low PWM 1 Duty Cycle Register High PWM 1 Duty Cycle Register Low PWM 2 Duty Cycle Register High PWM 2 Duty Cycle Register Low PWM 3 Duty Cycle Register High PWM 3 Duty Cycle Register Low Input Capture Register High Input Capture Register Low Transfer Control Register Break Control Register

0X00 0000h

00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 01h 00h

R/W Read Only Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only Read Only R/W R/W

0023h to

002Dh

Reserved area (11 bytes)

002Eh WDG WD GCR Watchdog Control Register 7Fh R/W

0002Fh FLASH FCSR Flash Control/Status Register 00h R/W 00030h EEPROM EECSR Data EEPROM Control/Status Register 00h R/W

0031h 0032h 0033h

SPI

SPIDR SPICR SPICSR

SPI Data I/O Register SPI Control Register SPI Control Status Register

xxh 0xh 00h

R/W R/W R/W

0034h 0035h 0036h

ADC

ADCCSR ADCDRH ADCDRL

A/D Control Status Register A/D Data Register High A/D Amplifier Control/Data Low Register

00h xxh 0xh

R/W Read Only R/W

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Legend: x=undefined, R/W=read/write Notes:

1. The contents of the I/O port DR regist ers are readable only in out put c onfigurat ion. I n i nput c onfiguration, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

3. For a description of the Debug Module registers, see ICC reference manual.

0037h ITC EICR External Interrupt Control Register 00h R/W 0038h MCC MCCSR Main Clock Control/Status Register 00h R/W 0039h

003Ah

Clock and

Reset

RCCR SICSR

RC oscillator Control Register System Integrity Control/Status Register

FFh

0000 0XX0h

R/W

R/W 003Bh Reserved area (1 byte) 003Ch ITC EISR External Interrupt Selection Register 0Ch R/W

003Dh to

0048h

Reserved area (12 bytes)

0049h 004Ah

AWU

AWUPR AWUCSR

AWU Prescaler Register AWU Control/Status Register

FFh

00h

R/W

R/W 004Bh

004Ch 004Dh 004Eh 004Fh 0050h

DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L

DM Control Register DM Status Register DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low

00h 00h 00h 00h 00h 00h

R/W

0051h to

007Fh

Reserved area (47 bytes)

Address Block Register Label Register Name Reset Status Remarks

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4 FLASH PROGRAM MEMORY

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.

The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming.

The array matrix organ isation allows each sector to be erased and reprogramm ed without affecting other sectors.

4.2 Main Features

■ ICP (In-Circuit Programming)

■ IAP (In-Application Programming)

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Sector 0 size configurable by option byte

■ Read-out and write protection against piracy

4.3 PROGRAMMING MODES

The ST7 can be programmed in three different ways:

– Insertion in a programming tool. In this m ode,

FLASH sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased.

– In-Circuit Programming. In this mode, FLA SH

sectors 0 and 1, option byte row and data EEPROM (if present) can be programme d or erased without removing the device from the application board.

– In-Application Programming. In this mode,

sector 1 and data EEPROM (if present) can be programmed or erased without removing

the device from the application board and while the application is running.

4.3.1 In-Circuit Programming (ICP)

ICP us es a pr otoco l c al l e d IC C ( I n- Ci r c ui t C om mu nication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:

Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface.

– Download ICP Driver c ode in RAM from the

ICCDATA pin

– Execute ICP Driver code in RAM to program

the FLASH memory

Depending on the IC P Driver c ode downl oaded in RAM, FLASH m emory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In Application Programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol us ed to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except Sector 0, which is write/erase prot ected to allow recovery in case errors occur during the programming operation.

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FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC interface

ICP needs a minimum of 4 and u p to 6 pins to be connected to the programming tool. These pins are:

– RESET

: device reset

–V

: device power supply ground – ICCCLK: ICC output serial clock pin – ICCDATA: ICC input serial data pin – OSC1: main clock input for external source

(not required on devices without OSC1/OSC2 pins)

–V

: application board power supply (option-

al, see Note 3)

Notes:

1. If the ICCCLK or ICCDATA pins are only u sed as outputs in t he ap plication, n o s ign al iso lation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2. During the ICP session, the programming tool must control the RESET

pin. This can lead to con-

flicts between the programming tool and the appli-

cation reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be u sed to isolat e the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain ou tput and pu ll-up resistor>1K, no additional com ponents are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3. The use of Pin 7 of the ICC con nector de pends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4. Pin 9 has to be connected t o the OSC1 pin of the ST7 when the clock is n ot available in the application or if the selected clock option is no t programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.

5. During reset, this pin must be held at high level to avoid entering ICC mode unexpec tedly (this is guaranteed by the internal pull-up if the application leaves the pin floating).

Figure 5. Typical ICC Interface

ICC CONNECTOR

ICCDATA

ICCCLK

RESET

VDD

HE10 CONNECTORTYPE

APPLICATION POWER SUPPLY

1 246810

975 3

PROGRAMMING TOOL

ICC CONNECTOR

APPLICAT ION BOARD

ICC C a ble

OPTIONAL (See No te 3)

ST7

OSC1

OSC2

OPTIONAL

See Note 1

See Notes 1 and 5

See Note 2

APPLICATION RESET SOURCE

APPLICATION

I/O

(See No te 4)

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FLASH PROGRAM MEMORY (Cont’d)

4.5 Memory Protection

There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually.

4.5.1 Read out Protection

Read out protection, when select ed, makes it impossible to extract the memory content from the microcontroller, thus preventing piracy. Both program and data E

memory are protected.

In flash devices, this protection is removed by reprogramming the option. In this case, both program and data E

memory are automatically

erased and the device can be reprogrammed . Read-out protection selection depends on the de-

vice type: – In Flash dev ices it is enabled and remo ved

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

4.5.2 Flash Write/Erase Protection

Write/erase protection, when set, makes it impossible to both overwrite and erase program mem ory. It does not apply to E

data. Its purpose is to provide advanced security to applications and prevent any change bei ng made to the m emory content.

Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable.

Write/erase protection is enabled through the FMP_W bit in the option byte.

4.6 Related Documentation

For details on Flash program ming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Re ference Manual

4.7 Register Description FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh)

Note: This register is reserved for programming using ICP, IAP or oth er programming methods. It controls the XFlash programming and eras ing operations.

When an EPB or another programming tool is used (in socket or ICP m ode), the RASS key s are sent automatically.

00000OPTLATPGM

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5 DATA EEPROM

5.1 INTRODUCTION

The Electrically Erasable Programmable Read Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter.

5.2 MAIN FEATURES

■ Up to 32 Bytes programmed in the same cycle

■ EEPROM mono-voltage (charge pump)

■ Chained er ase and progr ammi ng cycle s

■ Intern a l c ont rol of the global programming cycl e

duration

■ WAIT mode management

■ Readout protection against piracy

Figure 6. EEP ROM Block D ia gram

EECSR

HIGH VOLTAGE

PUMP

0 E2LAT00 0 0 0 E2PGM

EEPRO M

MEMORY MA TRIX

(1 ROW = 32 x 8 BITS)

ADDR ESS DECODER

DATA

MULTIPLEXER

32 x 8 BITS

DATA LATCHES

ROW

DECODE R

DATA BUS

128128

ADDRESS BU S

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DATA EEPROM (Cont’d)

5.3 MEMORY ACCESS

The Data EEPROM memory read/write access modes are co ntr olle d by th e E2LAT b it of t he EEPROM Control/Status register (EECSR). The flowchart in Figure 7 describes these different memory access modes.

Read Operation (E2L AT=0 )

The EEPROM can be read as a normal ROM location when the E2LAT bit of the EEC SR register is cleared. In a read cycle, the byte to be accessed is put on the data bus in less t han 1 CPU clock cycl e. This means that reading data from EEPROM takes the same time as reading data from EPROM, but this memory canno t be used to execute machine code.

Write Operation (E2LAT=1)

To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains cleared). When a write access to the EEPROM area occurs,

the value is latched inside the 32 dat a latches according to its address.

When PGM bit is set by the software, all the previous bytes written in the data latches (up to 32) are programmed in the EEP ROM cells. The effective high address (row) is determined by the last E EPROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the five Least Significant Bits of the address can change.

At the end of the programming cycle, the PGM and LAT bits are cleared simultaneously.

Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two w rite ac cess d ata result) because the data latches are on ly cleared at t he end of the programming cycle and by the fall ing edge of the E2LAT bit. It is not possible to read the latched data. This note is ilustrated by the Figure 9.

Figure 7. Dat a EEP R OM Program m i ng Fl owchart

READ MODE

E2LAT=0

E2PGM=0

WRITE M ODE

E2LAT=1

E2PGM = 0

REA D BYTES

IN EEPROM AREA

WRITEUPTO32BYTES

IN EEPROM AREA

(with the same 11 MSB of the address)

START PROGR AMM I NG CY CL E

E2LAT=1

E2PGM=1 (set by software)

E2LAT

CLEARED BY HARDWARE

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DATA EEPROM (Cont’d) Figure 8. Dat a E

PROM Write Operation

Note: If a programming cycle is interrupted (by software or a reset action), the integrity of the data in mem-

ory is not guaranteed.

Byte 1 Byte 2 Byte 32

PHASE 1

Programming cycle

Read operation impossible

PHASE 2

Read operation possible

E2LAT bit

E2PGM bit

Writing data latches Waiting E2PGM and E2LAT to fall

Set by USER applicatio n

Cleared by hardware

⇓

Row / Byte

⇒

0 1 2 3 ... 30 31 Physical Address

00h...1Fh

20h...3Fh

...

Nx20h...Nx20h+1Fh

ROW

DEFINITION

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DATA EEPROM (Cont’d)

5.4 POWER SAVI N G MO DES Wait mode

The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the m icrocontroller or when the microcontroller enters Active-HALT mode.The DATA EEPROM will immediately enter this mode if there is no programming i n progress, otherwise the DATA EEPROM will finish the c ycle and then enter WAIT mode.

Active-Halt mode

Refer to Wait mode.

Halt mode

The DATA EEPROM immediately enters HALT mode if the microcontroller ex ecutes the HALT i nstruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted.

5.5 ACCESS ERROR HANDLING

If a read access occurs while E2LAT=1, then the data bus will not be driven.

If a write access occurs while E2LAT=0, t hen the data on the b us w ill n ot b e latc hed.

If a programming cycl e is interrupted (by software/ RESET action), the memory data will not be guaranteed.

5.6 Data EEPROM Read-out Protection

The read-out protection is enabled through an option bit (see section 15.1 on page 123).

When this option is selected, the programs and data stored in the EEPROM memory are protected against read-out piracy (including a re-write protection). In Flash devices, when this protection is removed by reprogram ming t he Option Byte, the entire Program memeory a nd EEPROM is fi rst automatically erased.

Note: Both Pr ogram Me mory and da ta EEPROM are protected using the same option bit.

Figure 9. Dat a EEP R OM Program m i ng C yc l e

LAT

ERASE CYCLE WRITE CYCLE

PGM

PROG

READ OPERATION NOT POSSIBLE

WRITEOF

DATA LATCHES

READ OPERATION POSSIBLE

INTERNAL PROGRAMMING VOLTAGE

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DATA EEPROM (Cont’d)

5.7 REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EEC-

SR)

Read/Write Reset Value: 0000 0000 (00h)

Bits 7:2 = Reserved, forced by hardware to 0.

Bit 1 = E2LAT

Latch Access Transfe r

This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if the E2PGM bit is cleared. 0: Read mode 1: Write mode

Bit 0 = E2PGM

Programming control and status

This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware. 0: Programming finished or not yet started 1: Programming cycle is in progress

Note: if the E2PGM bit is cleared during the programming cycle, the m emory data is not guaranteed

Table 3. DATA EEPROM Register M ap and Reset Values

000000E2LATE2PGM

Address

(Hex.)

Label

76543210

0030h

EECSR

Reset Value

000000

E2LAT0E2PGM

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6 CENTRAL PRO CESSING UNIT

6.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

6.2 MAIN FEATURES

■ 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low po wer modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

6.3 CPU REGISTERS

The 6 CPU registers shown in Figure 10 are not present in the memory mapping and are accessed by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the res ults of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

Figure 10. CPU Registers

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

1C11HI NZ

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

15 8

PCH

PCL

RESET VALUE = STACK HIGHER ADDRESS

RESET VALUE =

1X11X1XX

RESET VALUE = XXh

X = Undefined Value

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CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC)

Read/Write Reset Value: 111x1xxx

The 8-bit Condition Code regist er contains the i nterrupt mask and four flags repres entative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Bit 4 = H

Half carry

This bit is set by hardware when a carry occurs between bits 3 and 4 of t he ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutine s .

Bit 3 = I

Interrupt mask

This bit is set by hardware when entering in interrupt or by software to disable all inte rrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JR NM instructions.

Note: Interrupts requested while I is set are latched and can be process ed when I is cleared. By default an interrupt routine is not in terruptable

because the I bi t is set by h ardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.

Bit 2 = N

Negative

This bit is set and cleared by hardware. It is representative of the result sign of the last arithm etic, logical or data manipulation. It is a copy of the 7

bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z

Zero

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from

zero.

1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test

instructions.

Bit 0 = C

Carry/borrow.

This bit is set and cleared b y hardware and software. It indicates an overflow or an un derflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It i s also affected by the “bit test and branch”, shift and rotate instructions.

111HINZC

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CPU REGISTERS (Cont’d) STACK POINTER (SP)

Read/Write Reset Value: 01FFh

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 11).

Since the stack is 128 bytes deep, the 9 most significant bits are forced by hard ware. Following a n MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address.

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then o verwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to sav e the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location po inted t o by t he SP. Th en t he other registers are stored in the next locations as shown in Figure 11.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locat ion s i n the stack ar ea.

Figure 11. Stack Manipulation Examp le

15 8

00000001

1 SP6 SP5 SP4 SP3 SP2 S P1 SP0

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCH PCL

PCL

PCH

PCH PCL

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 01FFh

@ 0180h

Stack Higher Address = 01FFh Stack Lower Address =

0180h

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7 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components.

Main features

■ Clock Management

– 1 MHz internal RC oscillator (enabled by op-

tion byte, available on ST7LITE25 and ST7LITE29 devices only)

– 1 to 16 MHz or 32kHz External crystal/ceramic

resonator (selected by option byte)

– External Clock Input (enabled by option byte) – PLL for multiplying the frequency by 8 or 4

(enabled by option byte)

– For clock ART counter on ly: PLL32 for multi-

plying the 8 MHz f requency by 4 (enabled by option byte). The 8 MHz input frequency is mandatory and can be obtained in the following ways:

–1 MHz RC + PLLx8 –16 MHz external clock (internally divided

by 2)

–2 MHz. external clock (internally divided by

2) + PLLx8

–Crystal oscillator with 16 MHz output fre-

quency (internally divided by 2)

■ Reset Sequence Manager (RSM)

■ System Integrity Management (SI)

– Main supply Low voltage detection (LVD) with

reset generation (enabled by option byte)

– Auxiliary Voltage detector (AVD) with interrupt

capability for monitoring the main suppl y (enabled by option byte)

7.1 INTERNAL RC OSCILLATOR ADJUSTMENT

The device contains an internal RC oscillator with an accuracy of 1% for a given device, temperature and voltage range (4.5V-5.5V). It must be calibrated to obtain the frequency required in the appl ication. This is done by software writing a calibration value in the RCCR (RC Control Register).

Whenever the microcontroller i s reset, the RCCR returns to its def ault value (F F h), i.e. each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in EEPROM for 3 and 5V V

supply volt-

ages at 25°C, as shown in the following table.

Note: – See “ELECTRICAL CHARACTERISTICS” on

page 91. for more information on the frequency and accuracy of the RC oscillator.

– To improve clock stability, it is recommended to

place a decoupling capacitor between the V

and V

pins.

– These two byte s are syst ematicall y programmed

by ST, including on FASTROM devices. Consequently, customers intending to use FASTROM service must not use these two bytes.

– RCCR0 and RCCR1 calibration values will be

erased if the read-out protection bit is reset after it has been set. See “Read out Protection” on page 14.

Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated.

Refer to application note AN1324 f or information on how to calibrate the RC frequency using an external reference signal.

7.2 PHASE LOCKED LOOP

The PLL can be used to multiply a 1MHz frequency from the RC oscillator or the external clock by 4 or 8 to obtain f

OSC

of 4 or 8 MHz. The PLL is enabled and the multiplication factor of 4 or 8 is selected by 2 option bits.

– The x4 PLL is intended for operation with V

the 2.4V to 3.3V range

– The x8 PLL is intended for operation with V

the 3.3V to 5.5V range

Refer to Section 15.1 for the option byte descrip- tion.

If the PLL is disabled and the RC oscillator is enabled, then f

OSC =

1MHz.

If both the RC oscillator and the PLL are disabled, f

OSC

is driven by the external clock.

RCCR Conditions

ST7LITE29

Address

ST7LITE25

Address

RCCR0

=5V

=25°C

=1MHz

1000h and FFDEh

FFDEh

RCCR1

=3V

=25°C

=700KHz

1001h and FFDFh

FFDFh

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PHASE LOCKED LOOP (Cont’d) Figure 12. PLL Output Frequency Timing

Diagram

When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs the clock after a delay of t

STARTUP

When the PLL output signal reaches the operating frequency, the LOCKED bit in the SICSCR register is set. Full PLL accuracy (ACC

PLL

) is reached after

a stabilization time of t

STAB

(see Figure 12 and

13.3.4 Internal RC Oscillator and PLL)

Refe r to section 7.6.4 on page 33 for a description of the LOCKED bit in the SICSR register.

7.3 REGISTER DESCRIPTION MAIN CLOCK CONTROL/STATUS REGISTER

(MCCSR)

Read / Write Reset Value: 0000 0000 (00h)

Bits 7:2 = Reserved, must be kept cleared.

Bit 1 = MCO

Main Clock Out enable

This bit is read /write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock. 0: MCO clock disabled, I/O port free for general

purpose I/O.

1: MCO clock enabled.

Bit 0 = SMS

Slow Mode select

This bit is read /write by software and cleared by hardware after a reset. This bit selects the input clock f

OSC

or f

OSC

/32.

0: Normal mode (f

CPU = fOSC

1: Slow mode (f

CPU = fOSC

/32)

RC CONTROL REGISTER (RCCR)

Read / Write Reset Value: 1111 1111 (FFh)

Bits 7:0 = CR[7:0]

RC Oscillator Frequency Ad-

justment Bits

These bits must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. The applica tion can store the correct value for each voltage range in EEPROM and write it to this register at start-up. 00h = maximum available frequency FFh = lowest available frequency

Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h.

4/8 x freq.

LOCKED bit set

STAB

LOCK

input

Output freq.

STARTUP

000000

MCO SMS

CR70 CR60 CR50 CR40 CR30 CR20 CR10

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Figure 13. Clock Management Block Diagram

CR4CR7 CR0CR1CR2CR3CR6 CR5 RCCR

OSC

MCCSR

SMS

MCO

CPU

TO CPU AND PERIPHERALS

(1ms timebase @ 8 MHz f

OSC

)

/32 DIVIDER

OSC

/32

OSC

LTIMER

LITE TIMER 2 COUNTER

8-BIT

AT TIMER 2

12-BIT

PLL

8MHz -> 32MHz

CPU

CLKIN

OSC2

CLKIN

Tunable

Oscillator1% RC

PLL 1MHz -> 8MHz PLL 1MHz -> 4MHz

RC OSC

PLLx4x8

DIVIDER

Option bits

OSC,PLLOFF,

OSCRANGE[2:0]

OSC

1-16 MHZ or 32kHz

CLKIN CLKIN

/OSC1

OSC

DIVIDER

OSC/2

CLKIN/2

Option bits

OSC,PLLOFF,

OSCRANGE[2:0]

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7.4 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by four different source types coming from the multioscillator block (1 to 16MHz or 32kHz):

■ an external source

■ 5 crystal or ceramic resonator oscillators

■ an internal high frequency RC oscillator

Each oscillator is optimized for a given freq uency range in terms of consumption and is selectable through the option byte. The assoc iated hardware configurations are shown in Table 4. Refer to the electrical characteristics section for more details.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Note: when the Multi-Oscillator is not used, PB4 is selected by default as external clock.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The s election within a list of 4 os cillators with different frequency ran ges has to be done by option byte in order to redu ce consumption (refer to section 15.1 on page 123 for more details on the frequency ranges). In this mode of the multi-oscillator, the resonator and the load c apacitors have to be placed as close as possible to t he oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected osci lla tor .

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Internal RC Oscillator

In this mode, the tunable 1%RC oscilla tor is use d as main clock source. The two oscillator pins have to be tied to ground.

Table 4. ST7 Clock Sources

Hardware Configuration

External ClockCrystal/Ceramic ResonatorsInternal RC Oscillator

OSC1 OSC2

EXTERNAL

ST7

SOURCE

OSC1 OSC2

LOAD

CAPACITORS

ST7

OSC1 OSC2

ST7

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7.5 RESET SEQUENCE MANAGER (RSM)

7.5.1 Introd uc tion

The reset sequence manager in cludes three RESET sources as shown in Figure 15:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase. The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map. The basic RE SET sequence consists of 3 phases

as shown in Figure 14:

■ Active Phase depending on the RESET source

■ 256 or 40 96 CPU clock cy cle delay (see table

below)

■ RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from t he Reset st ate. T he short er or longer clock cycle delay is automatically selected dependi ng on the clock source chosen by option byte:

The RESET vector fetch phase duration is 2 clock cycles.

If the PLL is en abled by opt ion by te, it ou tpu ts the clock after an additional delay of t

STARTUP

(see

Figure 12).

Figure 14. RESET Sequence Phases

7.5.2 Async hr onous External RESET

The RESET

pin is both an input and an open-drain

output with integrated R

weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

in order to be recognized (see Figure 16). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

Figure 15. Reset Block Diagram

Clock Source

CPU clock

cycle delay

Internal RC Oscillator 256 External clock (connected to CLKIN pin) 256 External Crystal/Ceramic Oscillator

(connected to OSC1/OSC2 pins)

4096

RESET

Active Phase

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

RESET

WATCHDOG RESET LVD RESET

INTERNAL RESET

PULSE

GENERATOR

Filter

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RESET SEQUENCE MANAGER (Cont’d) The RESET

pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the elect rical characteristics section.

7.5.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V

is over the minimum

level specified for the selected f

OSC

frequency.

A proper reset signal for a slow rising V

supply can generally be provide d by a n external R C network connected to the RESET

pin.

7.5.4 Internal Low Voltage Detector (LVD) RESET

Two differe nt RESET sequences caused by the internal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET

pin acts as an output that is

pulled low when V

DD<VIT+

(rising edge) or

DD<VIT-

(falling edge) as shown in Figure 16.

The LVD filters spikes on V

larger than t

g(VDD)

avoid parasitic resets.

7.5.5 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 16.

Starting from the Watchdog counter underflow, the device RESET

pin acts as an output that is pulled

low during at least t

w(RSTL)out

Figure 16. RESET Sequences

RUN

RESET PIN

EXTERNAL

WATCHDOG

ACTIVE PHASE

IT+(LVD)

IT-(LVD)

h(RSTL)in

RUN

WATCHDOG UNDERFLOW

w(RSTL)out

RUN RUN

RESET

RESET SOURCE

EXTERNAL

RESET

LVD

RESET

WATCHD O G

RESET

INTERNAL RESET (256 or 4096 T

CPU

)

VECTOR FETCH

ACTIVE

PHASE

ACTIVE PHASE

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7.6 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Mana gement block co ntains the Low voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.

7.6.1 Low Voltage Detector (LVD)

The Low Voltage Dete ctor function (LVD ) generates a static reset when the V

supply voltage is

below a V

IT-(LVD)

reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.

The V

IT-(LVD)

reference value for a voltage drop is

lower than the V

IT+(LVD)

reference value for poweron in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generat es a reset when V

is below:

–V

IT+(LVD)

when VDD is rising

–V

IT-(LVD)

when VDD is falling

The LVD func t io n is illustrat ed in F igure 17.

The voltage threshold can be configured by option byte to be low, medium or high.

Provided the minimum V

value (guaranteed for

the oscillator frequency) is above V

IT-(LVD)

, the

MCU can only be in two modes:

– under full software control – in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus p ermitting the MCU to reset other devices.

Notes: The LVD allows the device to be used without any

external RESET circuitry. The LVD is an optional func tion which can be se-

lected by option byte.

Figure 17. Low Voltage Detector vs Reset

IT+

(LVD)

RESET

IT-

(LVD)

hys

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Figure 18. Reset and Supply Management Block Diagram

LOW VOLTA G E

DETECTOR

(LVD)

AUXILIARY VOLTAGE

DETECTOR

(AVD)

RESET

RESET SEQUENCE

MANAGER

(RSM)

AVD Interrupt Reque st

SYSTEM INTEGRITY MANAGEMENT

WATCHDOG

SICSR

TIMER (WDG)

AVDIEAVDF

STATUS FLAG

00 LVDRFLOCKEDWDGRF0

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.6.2 Auxiliary Voltage Detector (AVD)

The Voltage Detector function (AVD) is based on an analog comparison between a V

IT-(AVD)

and

IT+(AVD)

reference value and the VDD main sup-

ply voltage (V

AVD

). The V

IT-(AVD)

reference value

for falling voltage is lower than the V

IT+(AVD)

reference value for rising voltage in order to avoid parasitic detection (hysteresis).

The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in t he S ICS R regi ster. This bit is read only.

Caution: The AVD functions only if the LVD is en-

abled through the option byte.

7.6.2.1 Monitoring the V

Main Supply

The AVD vol tage thres hold value is relative to t he selected LVD threshold configured by option b yte (see section 15.1 on page 123).

If the AVD interrupt is enabled, an interrupt is generated when the vol tage crosses the V

IT+(LVD)

IT-(AVD)

threshold (AVDF bit is set).

In the case of a drop i n v oltage, t he A V D i nterrupt acts as an early warning, allowing software to shut down safely before the LV D resets the microcontroller. See Figure 19.

Figure 19. Using the AVD to Monitor V

IT+(AVD)

IT-(AVD)

AVDF bit

RESET

IF AVDIE bit = 1

hyst

AVD INTERRUPT REQUEST

INTERRUPT C leared by

IT+(LVD)

IT-(LVD)

LVD RESET

Early Warning Interrupt

(Power has dropped, MCU not not yet in reset)

hardware

INTERRUPT Cleared by

reset

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.6.3 Low Power Modes

7.6.3.1 Interrupts

The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is

set and the interrupt mask in the CC register is reset (RIM instruction).

Mode Description

WAIT

No effect on SI. AVD interrupts cause the device to exit from Wait mode.

HALT

The CRSR register is frozen. The AVD remains active.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit from Wait

Exit

from

Halt

AVD event AVDF AVDIE Yes No

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.6.4 Register Description SYSTEM INTE GRITY (SI) CONTROL/STAT U S REGISTER (SICSR)

Read/Write Reset Value: 0000 0xx0 (0xh)

Bit 7:5 = Reserved, must be kept cleared.

Bit 4 = WDGRF

Watchdog reset flag

This bit indicates that the last Reset was generated by the Watchd og peripheral. It is set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.

Bit 3 = L OCKED

PLL Locked Flag

This bit is set and cleared by hardware. It is set automatically when the PLL reaches its operating frequency. 0: PLL not locked 1: PLL locked

Bit 2 = LVDRF

LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined.

Bit 1 = AVDF

Voltage Detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt reques t is generated when the AV DF bit is set. Refer to Figure

19 and to Section 7.6.2.1 for additional details.

0: V

over AVD threshold

1: V

under AVD threshold

Bit 0 = AVDIE

Voltage Detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag is set. The pending interrupt information is automatically cleared when sof tware ent ers t he A V D in terrup t rout ine. 0: AVD interrupt disabled 1: AVD interrupt enabled

Applicatio n notes

The LVDRF flag i s not cleared when another RE SET type occurs (external or watchdog), the LVDRF flag remains set to ke ep trace of the original failure. In this case, a watchdog res et can be detected by software while an external reset can not.

000

WDG

LOCKED LVDRF AVDF AVDIE

RESET Sources LVDRF WDGRF

External RESE T

pin 0 0

Watchdog 0 1

LVD 1 X

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8 INTERRUP T S

The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 20. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection).

Note: After reset, all interrupts are disabled. When an interrupt has to be serviced:

– Normal processing is susp ended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– The I bit of the CC register is set to prevent addi-

tional interrupts.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses).

The interrupt service routine should finish with the IRET instruction w hich causes the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I bit will be cl eared and the main p rogram will resume.

Priority Management

By default, a servicing interrupt cannot be interrupted because the I bi t is set by hardware ent ering in interrupt routine.

In the case when several int e rrupts a re simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table).

Interrupts and Low Power Mode

All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the proces sor to leave the HALT low power mode (refer to the “Exit from HALT“ column in th e Interrupt Mapping Table).

8.1 NON MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit.

It will be serviced according to the flowchart on

Figure 20.

8.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the PC register if the corresponding ex ternal interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode.

The external interru pt polarity is selected thro ugh the miscellaneous register or interrupt register (if available).

An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.

If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically NANDed before entering the edge/level detection block.

Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity.

8.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both:

– The I bit of the CC register is cleared. – The corresponding enable bit is set in the control

If any of these two conditions is false, the interrupt is latched and thus remains pending.

Clearing an interrupt request is done by: – Writing “0” to the corresponding bit in the status

– Access to the status register while t he flag is set

followed by a read or write of an associated register.

Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed.

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INTERRUPTS (Cont’d) Figure 20. Int errupt Processing Flowchart

Table 5. I nte rrupt Mapping

Note 1: This interrupt exits the MCU from “Auto Wake-up from Halt” mode only.

N°

Source

Block

Description

Label

Priority

Order

Exit from

HALT or

AWUFH

Exit

from

ACTIVE

-HALT

Address

Vector

RESET Reset

N/A

Highest

Priority

Lowest Priority

yes yes FFFEh-FFFFh

TRAP Software Interrupt no

FFFCh-FFFDh

0 AWU Auto Wake Up Interrupt AWUCSR yes

FFFAh-FFFBh

1 ei0 External Interrupt 0

N/A

yes

FFF8h-FFF9h 2 ei1 External Interrupt 1 FFF6h-FFF7h 3 ei2 External Interrupt 2 FFF4h-FFF5h 4 ei3 External Interrupt 3 FFF2h-FFF3h 5 LITE TIMER LITE TIMER RTC2 interrupt LTCSR2 no FFF0h-FFF1h 6 Not used FFEEh-FFEFh 7 SI AVD interrupt SICSR

FFECh-FFEDh

AT TIMER

AT TIMER Output Compare Interrupt or Input Capture Interrupt

PWMxCSR

or ATCSR

FFEAh-FFEBh

9 AT TIMER Overflow Interrupt ATCSR yes FFE8h-FFE9h

LITE TIMER

LITE TIMER Input Capture Interrup t LTCSR no FFE 6h-FF E7h 11 LITE TIMER RTC1 Interrupt LTCSR yes FFE4h-FFE5h 12 SPI SPI Peripheral Interrupts SPICSR yes no FFE2h-FFE3h 13 Not usedNot used FFE0h-FFE1h

I BIT SET?

IRET?

FROM RESET

LOAD PC FROM INTERRUPT VECTOR

STACK PC, X, A, CC

SET I BIT

FETCH NEXT INSTRUCTION

EXECUTE INSTRUCTION

THIS CLEARS I BIT BY DEFAULT

RESTORE PC, X, A, CC FROM STACK

INTERRUPT

PENDING?

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INTERRUPTS (Cont’d) EXTERNAL INTERRUPT CONTROL REGISTER

(EICR)

Read/Write Reset Value: 0000 0000 (00h)

Bit 7:6 = IS3[1:0]

ei3 sensitivity

These bits define the interrupt sensitivity for ei3 (Port B0) according to Table 6.

Bit 5:4 = IS2[1:0]

ei2 sensitivity

These bits define the interrupt sensitivity for ei2 (Port B3) according to Table 6.

Bit 3:2 = IS1[1:0]

ei1 sensitivity

These bits define the interrupt sensitivity for ei1 (Port A7) according to Table 6.

Bit 1:0 = IS0[1:0]

ei0 sensitivity

These bits define the interrupt sensitivity for ei0 (Port A0) according to Table 6.

Note: These 8 bits can be written only when the I bit in the CC register is set.

Table 6. I nte rrupt Sensitivity Bi t s

EXTERNAL INTERRUPT SELECTION REGISTER (EISR)

Read/Write Reset Value: 0000 1100 (0Ch)

Bit 7:6 = ei3[1:0]

ei3 pin selection

These bits are written by software. They select the Port B I/O pin used for the ei3 external interrupt according to the table below.

External Interrupt I/O pin selecti on

* Reset State

Bit 5:4 = ei2[1:0]

ei2 pin selection

These bits are written by software. They select the Port B I/O pin used for the ei2 external interrupt according to the table below.

External Interrupt I/O pin selecti on

* Reset State

IS31 IS30 IS21 IS20 IS11 IS 10 IS01 IS00

ISx1 ISx 0 External Interr upt Sensit ivity

0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge

ei31 ei30 ei21 ei20 ei11 ei10 ei01 ei00

ei31 ei30 I/O Pin

0 0 PB0 * 01 PB1 10 PB2

ei21 ei20 I/O Pin

0 0 PB3 * 01 PB4 10 PB5 11 PB6

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INTERRUPTS (Cont’d) Bit 3:2 = ei1[1:0]

ei1 pin selection

These bits are written by software. They s elect t he Port A I/O pin used for the ei1 external interrupt according to the table below.

Ext ernal Interrupt I/O pin se lection

* Reset State

Bit 1:0 = ei0[1:0]

ei0 pin selection

These bits are written by software. They s elect t he

Port A I/O pin used for the ei0 external interrupt according to the table below.

External Interrupt I/O pin selecti on

* Reset State

Bits 1:0 = Reserved.

ei11 ei10 I/O Pin

0 0 PA4 0 1 PA5 1 0 PA6 11 PA7*

ei01 ei00 I/O Pin

0 0 PA0 * 01 PA1 10 PA2 11 PA3

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9 POWER SAVING MO DES

9.1 INTRODUCTION

To give a large measure of flexibility to the application in terms of power consumption, five main power saving modes are implemented in the ST7 (see

Figure 21):

■ Slow

■ Wait (and Slow-Wait)

■ Active Halt

■ Auto Wake up From Halt (AWUFH)

■ Halt

After a RESET the normal operating mode is s elected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2 (f

OSC2

From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

Figure 21. P ower Sav in g Mo de Tr a nsi t io ns

9.2 SLOW MODE

This mode has two targets:

– To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (f

CPU

) to

the available supply voltage.

SLOW mode is controlled by the SMS bit in the MCCSR register which enables or disables Slow mode.

In this mode, the oscillator frequency is divided by

32. The CPU and peripherals are clocked at this lower frequency. Note: SLOW-WAIT mode is activated when enter-

ing WAIT mode while the device is already in SLOW mode.

Figure 22. SLOW Mode Clock Transition

POWER CONSUMPTION

WAIT

SLOW

RUN

ACTIVE HALT

High

Low

SLOW WAIT

AUTO WAKE UP FROM HALT

HALT

SMS

CPU

NORMAL RUN MODE

REQUEST

OSC

/32 f

OSC

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POWER SAVING MODES (Cont’d)

9.3 WAIT MODE

WAIT mode places the MCU in a low power c onsumption mode by stopping the CPU. This pow e r s a v ing mo de is selected by callin g the ‘WFI’ inst ru c ti on . All peripherals remain active. During WAIT mode, the I bit of the CC register is cleared, to enabl e all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU w ill re mai n in W AIT mo de unt il a Res et or an Interrupt occurs, causing it to wake up.

Refer to Figure 23.

Figure 23. WAIT Mode Flow-chart

Note:

1. Before servicing an interrupt, the CC register is

pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

WFI INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I BIT

ON ON

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I BIT

OFF

CPU

OSCILLATOR PERIPHERALS

IBIT

ON ON

CYCLE DELAY

256 OR 4096 CPU CLOCK

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POWER SAVING MODES (Cont’d)

9.4 HALT MODE

The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when ACTIVE-HALT is disabled (see section 9.5 on page 41 for more details) and when the AWUEN bit in the AWUCSR register is cleared.

The MCU can e xit HAL T mode on reception of either a specific interrupt (see Table 5, “Interrupt Mapping,” on page 35 ) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by s ervicing the i nterrupt o r by fetching the reset vector which woke it up (see Fig-

ure 25).

When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator).

The compatibility of Watchdog operation with HALT mode is configured by t he “WDGHALT” option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see sec-

tion 15.1 on page 123 for more details).

Figure 24. HALT Timing Overview

Figure 25. HALT Mode Flow- c hart

Notes:

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only some sp ecific interrupt s can exit the MCU from HALT mode (such as ext ernal inte rrupt). Refer to Table 5 Interrupt Mapping for more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared whenthe CC register is popped.

5. If the PLL is enabled by option byte, it outputs the clock after a delay of t

STARTUP

(see Figure 12).

HALTRUN RUN

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

[Active Halt disabled]

RESET

INTERRUPT

CPU

OSCILLATOR PERIPHERALS

IBIT

OFF OFF

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR PERIPHERALS

IBIT

OFF

CPU

OSCILLATOR PERIPHERALS

IBIT

ON ON

256 OR 4096 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT

WATCHDOG

RESET

CYCLE

HALT INSTRUCTION

(Active Halt disabled)

(AWUCSR.AWUEN=0)

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POWER SAVING MODES (Cont’d)

9.4.1 Halt Mode Recommendations

– M ake s ure that an external event is available to

wake up the microcontroller from Halt mode.

– When using an external interrupt to wake up the

microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.

– For the same reason, reinitialize the level sensi-

tiveness of each external interrupt as a precautionary measure.

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in program memory with the value 0x8E.

– As the HALT instruction clears the interrupt mask

in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).

9.5 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power consumption mode of the M CU with a real time c lock available. It is entered by ex ecut ing the ‘HALT’ instruction. The decision to enter either in ACTIVEHALT or HALT mode is given by the LTCSR/ATCSR register status as shown in the following table:

The MCU can exit ACTIVE-HALT mode on reception of a specific interrupt (see Table 5, “Interrupt Mapping,” on page 35) or a RESET.

– When exiting ACTIVE-HALT mode by means of

a RESET, a 256 or 4096 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by fetching the reset vector which woke it up (see Figure 27).

– When exiting ACTIVE-HALT mode by means of

an interrupt, the CPU immediately resumes operation by servicing the interrupt vector which woke it up (see Figure 27).

When entering ACTIVE-HALT mode, the I bit in the CC register is cleared to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately (see Note 3).

In ACTIVE-HALT mode, only the main oscillator and the selected timer counter (LT/AT) are running to keep a wake-up time base. All other peripherals are not clocked except those whic h get their clock supply from another clock g enerator (such as external or auxiliary oscillator).

Note: As soon as ACTIVE-HALT is enabled, executing a HALT instruction while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode.

LTCSR1

TB1IE bit

ATCSR

OVFIE

bit

ATCSR CK1 bit

ATCSR CK0 bit

Meaning

0xx0

ACTIVE-HALT mode disabled

00xx 1 xxx

ACTIVE-HALT mode enabled

x 101

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POWER SAVING MODES (Cont’d) Figure 26. ACTIVE-HALT Timing Overview

Figure 27. ACTIV E - H ALT Mode Flow-chart

Notes:

1. This delay occurs only if the MCU exits ACTIVE-

HALT mode by means of a RESET.

2. Peripherals clocked with an external clock source can still be active.

3. Only the RTC1 interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode. Refer to Table 5, “Interrupt Mapping,” on page 3 5 for more details.

4. Before s ervicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

9.6 AUTO WAKE UP FROM HALT MODE

Auto Wake Up From Halt (AWUFH) mode is similar to Halt mode with the addition of a specific internal RC oscillator for wake-up (Auto Wake Up from Halt Osc illator ). Com pare d to ACT IVE -HAL T mode, AWUFH has lower power consumption (the main clock is not kept running , but there is no accurate realtime clock available.

It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set.

Figure 28. AWUFH Mode Block Diagram

As soon as HALT mode is entered, and if the AWUEN bit has been set in the AWUCSR register, the AWU RC oscillator provides a clock signal (f

AWU_RC

). Its frequency is divided by a fixed divider and a programmable prescaler controlled by the AWUPR register. The output of this prescaler provides the delay time. When the delay has elapsed the AWUF flag is set by hardware and an interrupt wakes-up the MCU from Halt mode. At the same time the main oscillator is imme diately turn ed on and a 256 or 4096 cycle delay is used to stabilize it. After this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU flag and its associated interrupt are cleared by software reading the AWUCSR register.

To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated by measuring the clock frequency f

AWU_RC

and then calculating the right prescaler value. Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run mode. This connects f

AWU_RC

to the input capture of the 12-bit Auto-Re-

load timer, allowing the f

AWU_RC

to be measured using the main oscillator clock as a reference timebase.

HALTRUN RUN

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

ACTIVE

[Active Halt Enabled]

HALT INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I BIT

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR PERIPHERALS

I BIT

OFF

CPU

OSCILLATOR PERIPHERALS

I BIT

ON ON

256 OR 4096 CPU CLOCK

DELAY

(Active Halt enabled)

(AWUCSR.AWUEN=0)

CYCLE

AWU RC

AWUFH

AWU_RC

AWUFH

(ei0 source)

oscillator

prescaler/1 .. 255

interrupt

/64

divider

to Timer input capture

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POWER SAVING MODES (Cont’d) Similarities with Halt mode

The following AWUFH mode behaviour is the same as normal Halt mode:

– The MCU can exit AWUFH mode by means of

any interrupt with exit from Halt capability or a reset (see Section 9.4 HALT MODE).

– When entering AWUFH mode, the I bit in the CC

– In AWUFH mode, the main oscillator is turned off

causing all internal processing to be stopped, including the operation of the on-chip peripherals. None of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the AWU osc illator).

– The compatibility of Watchdog operation with

AWUFH mode is configured by the WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction when executed while the Watchdog system is enabled, can generate a Watch d og R ESET .

Figure 29. AWUF Halt Timing Diagram

AWUFH interrupt

CPU

RUN MODE HALT MODE 256 OR 4096 t

CPU

RUN MODE

AWU_RC

Clear by software

AWU

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POWER SAVING MODES (Cont’d) Figure 30. AWUFH Mode Flow-chart Notes:

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from HALT mode (s uch as external interrupt). Refer t o Table 5, “Interrupt Mapping,” on page 35 for more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

5. If the PLL is enabled by option byte, it outputs the clock after an additional delay of t

STARTUP

(see

Figure 12).

RESET

INTERRUPT

CPU

MAIN OSC PERIPHERALS

I[1:0] BITS

OFF OFF

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

MAIN OSC PERIPHERALS

I[1:0] BITS

OFF XX

CPU

MAIN OSC PERIPHERALS

I[1:0] BITS

ON ON

256 OR 4096 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT

WATCHDOG

RESET

CYCLE

AWU RC OSC ON

AWU RC OSC OFF

HALT INSTRUCTION

(Active-Halt disabled)

(AWUCSR.AWUEN=1)

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POWER SAVING MODES (Cont’d)

9.6.0.1 Register Description AWUFH CONTROL/STATUS REGISTER

(AWUCSR)

Read/Write Reset Value: 0000 0000 (00h)

Bits 7:3 = Reserved.

Bit 1= AWUF

Auto Wake Up Flag

This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. Writing to this bit does not change its value. 0: No AWU interrupt occurred 1: AWU interrupt occurred

Bit 1= AWUM

Auto Wake Up Measurement

This bit enables t he AWU RC oscillat or and connects its output to the inputcapture of the 12-bit Auto-Reload timer. This allows the timer to be used to measure the AWU RC oscillator dispersion and then compens ate this d ispersion by providing the right value in the AWUPRE register. 0: Measurement disabled 1: Measurement enabled

Bit 0 = AWUEN

Auto Wake Up From Halt Enabled

This bit enables the Auto Wake Up From Halt feature: once HALT mode is entered, the AWUFH wakes up the microcontroller after a time delay dependent on the AWU prescaler value. It is set and cleared by software. 0: AWUFH (Auto Wake Up From Halt) mode disa-

bled

1: AWUFH (Auto Wake Up From Halt) mode ena-

bled

AWUFH PRESCALER REGISTER (AWUPR)

Read/Write

Bits 7:0= AWUPR[7:0]

Auto Wake Up Prescaler

These 8 bits define the AWUPR Dividing factor (as explained below:

In AWU mode, the p eriod that the MCU stays in Halt Mode (t

AWU

in Figure 29 o n page 43) is de-

fined by

This prescaler register can be programmed to modify the time that the MCU s tays in Halt mode before waking up automatically.

Note: If 00h is written to AWUPR, depending on the product, an interrupt is generat ed imm ediately after a HALT instruction, or the AWUPR remains inchanged.

Table 7. AWU Register Map and Reset Values

00000

AWUFAWUMAWU

AWU

PR7

AWU

PR6

AWU

PR5

AWU

PR4

AWU

PR3

AWU

PR2

AWU

PR1

AWU

PR0

AWUPR[7:0

] Dividing factor

00h Forbidden 01h 1

... ...

FEh 254 FFh 255

AWU

64 AWUPR

AWURC

--------------------------t

RCSTRT

Address

(Hex.)

Label

76543210

0049h

AWUPR

Reset Value

AWUPR71AWUPR61AWUPR51AWUPR41AWUPR31AWUPR21AWUPR11AWUPR0

004Ah

AWUCSR

Reset Value

00000AWUFAWUMAWUEN

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10 I/O P ORTS

10.1 INTRODUCTION

The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may have several other functions. These functions can include external interrupt, alternate signal input/output for onchip peripherals or analog input.

10.2 FUNCTIONAL DESCRIPTION

A Data Register (DR) and a Data Direction Register (DDR) are always associated with each port. The Option Register (OR), which allows input/output options, may or may not be imple men ted. The following description takes into account the OR register. Refer to the Port Configuration table for device specific information.

An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: bit x corresponding to pin x of the port.

Figure 31 shows the generic I/O block diagram.

10.2.1 Input Modes

Clearing the DDRx bit selects input mode. In this mode, reading its DR b it returns the digital value from that I/O pin.

If an OR bit is available, different input modes can be configured by software: floating or pull-up. Refer to I/O Port Implementation section f or configuration.

Notes:

1. Writing to the DR modifies the latch val ue but does not change the state of the input pin.

2. Do not use read/modify/write instructions (BSET/BRES) to modify the DR register.

Ext ernal Interrupt Function

Depending on the device, setting the ORx bit while in input mode can configure an I/O as an input with interrupt. In this configuration, a signal edge or level input on the I/O gene rates an interrupt request via the corresponding interrupt vector (eix).

Falling or rising edge sensitivity is programmed independently for each interrupt vector. The External Interrupt Control Register (EICR) or the Miscellaneous Register controls this sensitivity, depending on the device.

A device may have up to 7 external interrupts. Several pins may be tied to on e external interrupt vector. Refer to Pin Description to see which ports have external interrupts.

If several I/O interrupt pins on the same interrupt vector are selected simultaneously, they are l ogically combined. For t his reason if one of the in terrupt pins is tied low, it may mask the othe rs.

External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Modifying the sensitivity bits will clear any pending interrupts.

10.2.2 Output Modes

Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the I/O through the latch. Reading the DR bits returns the previously stored value.

If an OR bit is available, different output modes can be selected by software: push-pull or opendrain. Refer to I/O Port Implementation section for configuration.

DR Value and Output Pin Status

10.2.3 Alternate Functions

Many ST7s I/Os hav e one or more alternate functions. These m ay include output signals from, or input signals to, on-c hip peripherals. The Device Pin Description table describes which peripheral signals can be input/output to which ports.

A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the on-chip peripheral as an output (enable bit in the peripher-

al’s control register). The peripheral configures the I/O as an output and takes priority over standard I/ O programming. The I/O’s state is readable by addressing the corresponding I/O data register.

Configuring an I/O as floating enables alternate function input. It is not recommended to configure an I/O as pull-up as this will increase current consumption. Before us ing an I/O as an alternate input, configure it without interrupt. Otherwise spurious interrupts can occur.

Configure an I/O as input floating for an on-chip peripheral signal which can be input and output.

Caution: I/Os which can b e configured as both an analog and digital alternate function need special attention. The user must control the peripherals s o that the signals do not arrive at the same time on the same pin. If an external clock is used, only the clock alternate function should be employed on that I/O pin and not the other alternate function.

DR Push-Pull Open-Drain

1VOHFloating

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I/O PORTS (Cont’d) Figure 31. I /O Por t Ge nera l Blo c k D iag ram

Table 8. I/O Port Mode Options

Legend : NI - not implemented

Off - implemented not activated On - implemented and activated

Note: The diode to V

is not imp lement ed i n t he true open drain pads. A local protection between the pad and V

is implemented to protect the de-

vice against positive stress.

Configuration Mode Pull-Up P-Buffer

Diodes

to V

Input

Floating with/without Interrupt Off

Off

Pull-up with/withou t Interrupt On

Output

Push-pull

Off

On Open Drain (logic level) Off True Open Drain NI NI NI (see note)

DDR

DATA BUS

PAD

ALTERNATE ENABLE

ALTERNATE OUTPUT

OR SEL

DDR SEL

DR SEL

PULL-UP CONDITION

P-BUFFER (see table below)

N-BUFFER

PULL-UP (see table below)

ANALOG

INPUT

If implemented

ALTERNATE

INPUT

DIODES (see table below)

FROM OTHER BITS

EXTERNAL

REQUEST (eix)

INTERRUP T

SENSITIVITY SELECTION

CMOS SCHMITT TRIGGER

BIT

From on- chip peripheral

To on-chip peri pheral

Note : Refer to the Port C o nfiguratio n table for device specific information.

Combinational

Logic

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I/O PORTS (Cont’d) Table 9. I /O C onfi gurations

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.

3. For true open drain, these elements are not implemented.

Hardware Configuration

INPUT

OPEN-DRAIN OUTPUT

PUSH-PULL O UTPUT

NOTE 3

CONDITION

PAD

EXTERNAL INTERRUPT

POLARITY

DATABUS

PULL-UP

INTERRUPT

DR REGISTER ACCESS

FROM

OTHER

PINS

SOURCE (ei

)

SELECTION

CONDITION

ALTERNATE INPUT

ANALOG INPUT

To on-chip peripheral

COMBINATIONAL

LOGIC

NOTE 3

PAD

DATA BUS

DR REGISTER ACCESS

R/W

PAD

DATA BUS

DR REGISTER ACCESS

R/W

ALTERNATEALTERNATE

ENABLE OUTPUT

BIT From on-chi p peripheral

NOTE 3

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I/O PORTS (Cont’d) Analog alternate function

Configure the I/O as floating input to use an ADC input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail, connected to the ADC input.

Analog Recommendations

Do not change the voltage level or loading on any I/O while conversion is in progress. Do not have clocking pins located close to a selected analog pin.

WARNING: The analog input voltage level must be within the limits stated in the absolute maximum r a tings.

10.3 I/ O PORT IMPL EMENTATION

The hardware implementation on each I/O port depends on the settings in t he DDR and OR registers and specific I/O port features such as ADC input or open drain.

Switching these I/O ports from one state t o another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions ar e illu strat ed in Figure 32. Ot her transitions are potentially risky and shou ld be av oided, since they may present unwanted side-effects such as spurious interrupt generation.

Figure 32. Interrupt I/O Port State Transitions

10.4 UNUSED I/O PINS

Unused I/O pins m ust be connected to f ixed voltage levels. Refer to Section 13.8.

10.5 LOW POWER MODES

10.6 INTERRUPTS

The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM instruction).

Mode Description

WAIT

No effect on I/O ports. External interrupts cause the device to exit from WAIT mode.

HALT

No effect on I/O ports. External interrupts cause the device to exit from HALT mode.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

External interrupt on selected external event

DDRx

ORx

Yes Yes

floating/pull-up

interrupt

INPUT

floating

(reset state)

INPUT

open-drain

OUTPUT

push-pull

OUTPUT

= DDR, OR

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I/O PORTS (Cont’d)

10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION

The I/O port register configurations are summarised as follows.

Stan da rd Po rt s PA7:0, PB6:0

Interrupt P ort s Ports where the ex ternal i nterrupt capability is

selected using the EISR register

Table 10. P o rt Conf i gu ra tio n ( S ta ndard ports)

Note: On p orts w h er e t he e xter nal int errupt c apability is se lected us ing the EISR r egist er, the c onfigur a-

tion will be as follows:

Table 11. I/O Port Register Map and Reset Values

MODE DDR OR

floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1

MODE DDR OR

floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1

Port Pin name

Input Output

OR = 0 OR = 1 OR = 0 OR = 1

Port A PA7: 0 floating

pull-up

open drain push-pull

Port B PB6:0 floating pull-up open drain push-pull

Port Pin name

Input Output

OR = 0 OR = 1 OR = 0 OR = 1

Port A PA7:0 floating pull-up interr upt open drain push-pull Port B PB6:0 floating pull-up interr upt open drain push-pull

Address

(Hex.)

Label

76543210

0000h

PADR

Reset Value

MSB

1111111

LSB

0001h

PADDR

Reset Value

MSB

0000000

LSB

0002h

PAOR

Reset Value

MSB

0100000

LSB

0003h

PBDR

Reset Value

MSB

1111111

LSB

0004h

PBDDR

Reset Value

MSB

0000000

LSB

0005h

PBOR

Reset Value

MSB

0000000

LSB

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11 ON-CHIP PERIPHERALS

11.1 WATCHDOG TIMER (WDG)

11.1.1 Introduction

The Watchdog t imer is used to d etect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal seque nce. The W atchdog circuit generates an MCU reset on ex piry of a programmed time period, unless the program refresh-

es the counter’s contents before the T6 bit becomes cleared.

11.1.2 Main Features

■ Programmable free-running downcounter (64

increments of 16000 CPU cycles)

■ Programmable reset

■ Reset (if watchdog activated) when the T6 bit

reaches zero

■ Optional reset on HALT instruction

(configurable by option byte)

■ Hardware Watchdog selectable by option byte

11.1.3 Functional Description

The counter value stored in the CR register (bits T[6:0]), is decremented every 16000 m achine cycles, and the length of the timeou t period can be programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becom es cleared ), it initiates a reset cycle pulling low the reset pin for typically 36µs.

Figure 33. Watc hdog Block Diagram

RESET

WDGA

7-BIT DOWNCOU NTE R

CPU

T6 T0

CLOCK DIVIDER

WATCHDOG CONTROL REGISTER (CR)

16000

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WATCH DOG TI MER (Cont’d) The application program must write in the CR reg-

ister at regular intervals during normal operation to prevent an MCU res et. This d owncounter is f reerunning: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 12

.Watchdog Timing):

– The WDGA bit is set (watchdog enabled) – The T6 bit is set to prevent generating an imme-

diate reset

– The T[5:0] bits contain the number of increments

which represents the time delay before the watchdog produces a reset.

Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset.

The T6 bit can be used t o generate a s of tw are reset (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction will generate a Reset.

Table 12.Watchdo g Timing

Notes:

1. The timing variation shown in Table 12 is due to the unknown status o f the prescaler when writing to the CR register.

2. The number of CPU cloc k cycl es a p plie d during the RESET phase (256 or 4096) must be taken into account in addition to these timings.

11.1.4 Hardware Watchdo g Option

If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used.

Refer to the Option Byte description in section 15

on page 123.

11.1.4.1 Using Halt Mode with the WDG (WDGHALT option)

If Halt mode with Watchdog is en abled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. Same behavior in active-halt mode.

CPU

= 8MHz

WDG

Counter

Code

min

[ms]

max [ms]

C0h 1 2 FFh 127 128

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WATCH DOG TI MER (Cont’d)

11.1.5 Interrupts

None.

11.1.6 Register Description

CONTROL REGISTER (CR)

Read/Write Reset Value: 0111 1111 (7Fh)

Bit 7 = WDGA

Activation bit

. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled

Note: This bit is not us ed if the hardware watchdog option is enabled by option byte.

Bit 6:0 = T[6:0]

7-bit timer (MSB to LSB).

These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).

WDGA T6 T5 T4 T3 T2 T1 T0

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WATCH DOG TI MER (Cont’d) Table 13. Watchdog Time r Register Map and Rese t Values

Address

(Hex.)

Label

76543210

002Eh

WDGCR

Reset Value

WDGA

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11.2 12-BIT AUTORELOAD TIMER 2 (AT2)

11.2.1 Introduction

The 12-bit Autoreload T imer c an be used for general-purpose timing functions. It is based on a freerunning 12-bit upcounter with an input capture register and four PWM output channels. There are 6 external pins:

– F our PW M output s – A T IC pin for the Input Capture function – BREAK pin for forcing a break condition on the

PWM outputs

11.2.2 Main Features

■ 12-bit upcounter with 12-bit autorelo ad register

(ATR)

■ Maskable overflow interrupt

■ Generation of four independent PWMx signals

■ Frequency 2KHz-4MHz (@ 8 MHz f

CPU

)

– Programmable duty-cycles – Polarity control – Programmable output modes – Maskable Compare interrupt

■ Input Capture

– 12-bit input capture register (ATICR) – Triggered by rising and falling edges – Maskable IC interrupt

Figure 34. Block Diagram

ATCSR

CMPIEOVFIEOVFCK0CK1ICIEICF0

12-BIT AUTORELOAD REGISTER

12-BIT UPCOUNTER

CMPF2

CMPF1 CMPF3

CMPF0

CMP REQUEST

OVF INTERRUPT REQUEST

CPU

ATIC

12-BIT INPUT CAPTURE REGISTER

IC INTERRUPT

REQUEST

ATR

ATICR

COUNTER

CNTR

32 MHz

(1 ms

LTIMER

@ 8MHz)

CMPFx bit

PWM GENERATION

POLARITY

OPx bit

PWMx

COMP-

PARE

PWM

OUTPUT CONTROL

OEx bit

4 PWM Channels

INTERRUPT

timebase

DCR0H

DCR0L

Preload

on OVF Event

12-BIT DUTY CYCLE VALUE (shadow)

IF TRAN=1

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12-BIT AUTORELOAD TIMER (Cont’d)

11.2.3 Functional Description PWM M ode

This mode allows up to four Pulse W idth Mo dulated signals to be generated on the PWMx output pins. The PWMx output signals can be enabled or disabled using the OEx b its in the PWMCR register.

PWM Frequency and Duty Cycle

The four PWM signals have the sam e frequency (f

PWM

) which is controlled by the counter period

and the ATR register value.

PWM

= f

COUNTER

/ (4096 - ATR) Following the above formula, – If f

COUNTER

is 32 MHz, the maximum value of

PWM

is 8 MHz (ATR register value = 4092), the

minimum value is 8 KHz (ATR register value = 0)

– I f f

COUNTER

is 4 Mhz, the max imum val ue of f

PWM

is 2 MHz (ATR register value = 4094),the minimum value is 1 KHz (ATR register value = 0).

Note: The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case.

At reset, the counter starts counting from 0. When a upcounter o verflow oc curs (OV F event),

the preloaded Duty cycle values are transferred to the Duty Cycle registers and the PWMx signals are set to a high level. When the upcounter matches the DCRx value the PWMx signals are set to a low level. To obtain a signal on a PWMx pin, the

contents of the corresponding DCRx register must be greater than the contents of the ATR register.

The polarity bits can be used to invert any of the four output signals. The inversion is synchronized with the counter overflow if the TRAN bit in the TRANCR register is set (reset value). See Figure

35.

Figure 35. PWM Inversion Diagram

The maximum av ailable resolution for the PW Mx duty cycle is:

Resolution = 1 / (4096 - ATR)

Note: To get the maximum resolution (1/4096), the ATR register must be 0. With this maximum resolution, 0% and 100% can be obtained by changing the polarity.

Figure 36. PWM Func t ion

PWMx

PWMx PIN

counter

overflow

OPx

PWMxCSR Register

inverter

DFF

TRAN

TRANCR Register

DUTY CYCLE

AUTO-RELOAD

PWMx OUTPUT

4095

000

WITH OE=1 AND OPx=0

(ATR)

(DCRx)

WITH OE=1 AND OPx=1

COUNTER

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12-BIT AUTORELOAD TIMER (Cont’d) Figure 37. PWM Signal from 0% to 100% Duty Cycle

Output Compare Mode

This mode is always available. To use this function, load a 12-bit value in the

DCRxH and DCRxL registers. When the 12-bit upcounter (CNTR) reaches the

value stored in the DCRxH and DCRxL registers, the CMPF bit in the PWMxCSR register is set and an interrupt request i s generated i f the CM PIE bit is set.

Note: The output compare function is only available for DCRx values other than 0 (reset value).

Break Function

The break function is used to perform an emergency shutdown of the power converter.

The break function is activated by the external BREAK pin (active low). In order to use the BREAK pin it must be previously enabled by software setting the BPEN bit in the BREAKCR register.

When a low level is detected on the BREAK pin, the BA bit is s et an d the break function i s activated.

Software can set the BA bit to activate the break function without using the BREAK pin.

When the break function is activated (BA bit =1): – The break pattern (PWM[3:0] bits in the BREAK-

CR) is forced directly on the PWMx output pins

(after the inverter). – The 12-bit PWM counter is set to its rese t va l u e . – The ARR, DCRx and the corresponding shadow

registers are set to their reset values. – The PWM CR register is reset. When the break function is deactivated after ap-

plying the break (BA bit goes from 1 to 0 by sof tware):

– The control of PWM outputs is transferred to the

port registers.

COUNTER

PWMx OUTPUTtWITH MOD00=1

AND OPx=0

FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh

DCRx=000h

DCRx=FFDh

DCRx=FFEh

DCRx=000h

ATR= FFDh

COUNTER

PWMx OUTPUT

WITH MOD00=1

AND OPx=1

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Figure 38. Block Diagram of Break Function

11.2.3.1 Input Capture

The 12-bit ATICR register is used to latch t he va lue of the 12-bit free running upcounter after a rising or falling edge is detected on the ATIC pin. When an input captu re oc curs, the I CF bit is set and the ATICR register contains the value of the

free running upcounter. An IC interrupt is generated if the ICIE bit is set. The ICF bit is reset by reading the ATICR register when the ICF bit is set. The ATICR is a read only register and always contains the free running upcounter value which corresponds to the most recent input capture. Any further input capture is inhibited while the ICF bit is set.

Figure 39. Input Capture Timing Diagram

PWM0

PWM1

PWM2

PWM3

PWM0

PWM1

PWM2

PWM3

BREAKCR Register

BREAK pin

PWM counter -> Reset value ARR & DCRx -> Reset value PWM Mode -> Reset value

When BA is set:

(Active Low)

(Inverters)

Note: The BREAK pin value is latched by the BA bit.

PWM0PWM1PWM2PWM3BPENBA

COUNTER

01h

COUNTER

xxh

02h 03h 04h 05h 06h 07h

04h

ATIC PIN

ICF FLAG

ICR REGISTER

INTERRUPT

08h 09h 0Ah

INTERRUPT

ATICR READ

09h

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12-BIT AUTORELOAD TIMER (Cont’d)

11.2.4 Low Power Mo des

11.2.5 Interrupts

Note 1: The CMP and IC events are connected to

the same interrupt vector.

The OVF event is mapped on a separate vector (see Interrupts chapter). They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset (RIM instruction) .

Note 2: Only if CK0=1 and CK1=0

Mode Description

SLOW

The input frequency is divided by 32

WAIT No effect on AT timer ACTIVE-HALT

AT timer halted except if CK0=1, CK1=0 and OVFIE=1

HALT AT timer halted

Interrupt

Event

Flag

Enable

Control

Bit

Exit from Wait

Exit

from

Halt

Exit

from

Active-

Halt

Overflow Event

OVF OVIE Yes No Yes

IC Event ICF ICIE Yes No No CMP Event CMPF0 CMPIE Yes No No

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12-BIT AUTORELOAD TIMER (Cont’d)

11.2.6 Register Description TIMER CONTROL STATUS REGISTER

(ATCSR)

Read / Write Reset Value: 0x00 0000 (x0h)

Bit 7 = Reserved.

Bit 6 = ICF

Input Capture Flag.

This bit is set by hardware and cleared by soft ware by reading the ATICR register (a read ac cess to ATICRH or ATICRL will clear this flag). Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred

Bit 5 = ICIE

IC Interrupt Enable.

This bit is set and cleared by software. 0: Input capture interrupt disabled 1: Input capture interrupt enabled

Bits 4:3 = CK[1:0]

Counter Clock Selection.

These bits are set and cleared by software and cleared by hardware after a reset. They select the clock frequency of the counter. The change becomes effective after an overflow.

Note 1: PWM mode is not available at this frequency.

Note 2: ATICR counter may return inaccurate results when read. It is therefore not recommended to use Input Capture mode at this frequency.

Bit 2 = OVF

Overflow Flag.

This bit is set by hardware and cleared by software by reading the TCSR register. It indicates the transition of the counter from FFh to ATR value. 0: No counter overflow occurred 1: Counter overflow occurred

Bit 1 = OVFIE

Overflow Interrupt Enable.

This bit is read /write by software and cleared by hardware after a reset. 0: OVF interrupt disabled. 1: OVF interrupt enabled.

Bit 0 = CMPIE

Compare Interrupt Enable

. This bit is read /write by software and cleared by hardware after a reset. It can be used to mask the interrupt generated when the CMPF bit is set. 0: CMPF interrupt disabled. 1: CMPF interrupt enabled.

COUNTER REGISTER HIGH (CNTRH)

Read only Reset Value: 0000 0000 (000h)

COUNTER REGISTER LOW (CNTRL)

Read only Reset Value: 0000 0000 (000h)

Bits 15:12 = Reserved. Bits 11:0 = CNTR[11:0]

Counter Value

. This 12-bit register is read by software and cleared by hardware after a reset. The counter is incremented continuou sly as soon as a count er clok is selected. To obtain the 12-bit value, software should read the co unter value in two cons ecutive read operations, LSB first. When a counter overflow occurs, the counter restarts from the value specified in the ATR register.

76 0

0 ICF ICIE CK1 CK0 OVF OVFIE CMPIE

Counter Clock Selection CK1 CK0

OFF 0 0

LTIMER

(1 ms timebase @ 8 MHz)

CPU

32 MHz

15 8

0000

CNTR11CNTR

CNTR9 CNTR8

CNTR7 CNTR6 CNTR5 CNTR4 CNTR3 CNTR2 CNTR1 CNTR0

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12-BIT AUTORELOAD TIMER (Cont’d) AUTORELOAD REGISTER (ATRH)

Read / Write Reset Value: 0000 0000 (00h)

AUTORELOAD REGISTER (ATRL)

Read / Write Reset Value: 0000 0000 (00h)

Bits 11:0 = ATR[11:0]

Autoreload Register.

This is a 12-bit register which is written by software. The ATR register value is automatically loaded into the upcounter when an overflow occurs. The register value is used to set the PWM frequency.

PWM OUTPUT CONTROL REGISTER (PWMCR)

Read/Write Reset Value: 0000 0000 (00h)

Bits 7:0 = OE[3:0]

PWMx output enable

. These bits are set and cleared by software and cleared by hardware after a reset. 0: PWM mode disabled. PWMx Output Alternate

Function disabled (I/O pin free for general purpose I/O)

1: PWM mode enabled

PWMx CONTROL STATUS REGISTER (PWMxCSR)

Read / Write Reset Value: 0000 0000 (00h)

Bits 7:2= Reserved, must be kept cleared.

Bit 1 = OPx

PWMx Output Polarity.

This bit is read /write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM signal. 0: The PWM signal is not inverted. 1: The PWM signal is inverted.

Bit 0 = CMPFx PW Mx

Compare Flag.

This bit is set by hardware and cleared by software by reading the PWMxCSR register. It indicates that the upcounter value matches the DCRx register value. 0: Upcounter value does not match DCR value. 1: Upcounter value matches DCR value.

BREAK CONTROL REGISTER (BREAKCR)

Read/Write Reset Value: 0000 0000 (00h)

Bits 7:6 = Reserved. Forced by hardware to 0.

Bit 5 = BA

Break Active.

This bit is read/write by software, cleared by hardware after reset and set by hardware when the BREAK pin is low. It activates/deactivates the Break function. 0: Break not active 1: Break active

15 8

0 0 0 0 ATR11 ATR10 ATR9 ATR8

ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0

0OE30OE20OE10OE0

76 0

000000OPxCMPFx

0 0 BA BPEN PWM3 PWM2 PWM1 PWM0

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12-BIT AUTORELOAD TIMER (Cont’d) Bit 4 = BPEN

Break Pin Enable.

This bit is read/write by software and cleared by hardware after Reset. 0: Break pin disabled 1: Break pin enabled

Bit 3:0 = PWM[3:0]

Break Pattern.

These bits are read/ write by sof tware and cleared by hardware after a reset . They are used to forc e the four PWMx output signals into a stable state when the Break function is active.

PWMx DUTY CYCLE REGISTER HIGH (DCRxH) Read / Write Reset Value: 0000 0000 (00h)

PWMx DUTY CYCLE REGISTER LOW (DCRxL) Read / Write Reset Value: 0000 0000 (00h)

Bits 15:12 = Reserved. Bits 11:0 = DCR[11:0]

PWMx Duty Cycle Valu e

This 12-bit value is written by software. It definesthe duty cycle of th e correspondin g PWM output signal (see Figure 36).

In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWMx output signal (see Figure 36). In Output Compare mode, they define the value to be com pared with the 12-bit upcounter value.

INPUT CAPTURE REGISTER HIGH (ATICRH)

Read only Reset Value: 0000 0000 (00h)

INPUT CAPTURE REGISTER LOW (ATICRL)

Read only Reset Value: 0000 0000 (00h)

Bits 15:12 = Reserved. Bits 11:0 = ICR[11:0]

Input Capture Data

. This is a 12-bit register which is read able by s oftware and cleared by hardware after a reset. The ATICR register contains captured the value of the 12-bit CNTR register when a rising or falling e dge occurs on the ATIC p in. Capture will only be performed when the ICF flag is cleared.

TRANSFER CONTROL REGISTER (TRANCR)

Read/Write Reset Value: 0000 0001 (01h)

Bits 7:1 Reserved. Forced by hardware to 0.

Bit 0 = TRAN

Transfer enable

This bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset.

It allows the value of the DCRx registers to be transferred to the DCRx shadow registers after the next overflow event.

The OPx bits are t ransferred to the shadow OPx bits in the same way.

15 8

0 0 0 0 DCR11 DCR10 DCR9 DCR8

DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0

15 8

0000ICR11ICR10ICR9ICR8

ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0

0000000TRAN

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12-BIT AUTORELOAD TIMER (Cont’d) Table 14. Register Map and Reset Values

Address

(Hex.)

Label

76543210

ATCSR

Reset Value

ICF

ICIE

CK1

CK0

OVF

OVFIE0CMPIE

CNTRH

Reset Value

0000

CNTR110CNTR100CNTR90CNTR8

CNTRL

Reset Value

CNTR70CNTR80CNTR70CNTR60CNTR30CNTR20CNTR10CNTR0

ATRH

Reset Value

0000

ATR110ATR10

ATR9

ATR8

ATRL

Reset Value

ATR7

ATR6

ATR5

ATR4

ATR3

ATR2

ATR1

ATR0

PWMCR

Reset Value

OE3

OE2

OE1

OE0

PWM0CSR

Reset Value

000000

OP0

CMPF0

PWM1CSR

Reset Value

000000

OP1

CMPF1

PWM2CSR

Reset Value

000000

OP2

CMPF2

PWM3CSR

Reset Value

000000

OP3

CMPF3

DCR0H

Reset Value

0000

DCR110DCR10

DCR9

DCR8

DCR0L

Reset Value

DCR7

DCR6

DCR5

DCR4

DCR3

DCR2

DCR1

DCR0

DCR1H

Reset Value

0000

DCR110DCR100DCR9

DCR8

DCR1L

Reset Value

DCR7

DCR6

DCR5

DCR4

DCR3

DCR2

DCR1

DCR0

DCR2H

Reset Value

0000

DCR110DCR100DCR9

DCR8

DCR2L

Reset Value

DCR7

DCR6

DCR5

DCR4

DCR3

DCR2

DCR1

DCR0

DCR3H

Reset Value

0000

DCR110DCR100DCR9

DCR8

DCR3L

Reset Value

DCR7

DCR6

DCR5

DCR4

DCR3

DCR2

DCR1

DCR0

ATICRH

Reset Value

0000

ICR11

ICR10

ICR9

ICR8

ATICRL

Reset Value

ICR7

ICR6

ICR5

ICR4

ICR3

ICR2

ICR1

ICR0

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TRANCR

Reset Value

0000000

TRAN

BREAKCR

Reset Value

BPEN

PWM30PWM2

PWM1

PWM0

Address

(Hex.)

Label

76543210

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11.3 LITE TIMER 2 (LT2)

11.3.1 Introduction

The Lite Timer can be used for general-purpose timing functions. It is based on two free-running 8bit upcounters, an 8-bit input capture register.

11.3.2 Main Features

■ Realtime Clock

– One 8-bit upcounter 1 ms o r 2 m s timebase

period (@ 8 MHz f

OSC

)

– One 8-bit upcounter with auto reload and pro-

grammable timebase period from 4µs to

1.024ms in 4µs increments (@ 8 MHz f

OSC

)

– 2 Maskable timebase interrupts

■ Input Capture

– 8-bit input capture register (LTICR) – Maskable interrupt with wakeup from Halt

Mode capability

Figure 40. Lite Timer 2 Block Diagram

LTCSR1

8-bit TIMEBASE

8-bit

LTIMER

LTIC

OSC

/32

TB1F TB1IETBICFICIE

LTTB1 INTERRUPT REQUEST

LTIC INTERRUPT REQUEST

LTICR

INPUT CAPTURE

1 or 2 ms

Timebase (@ 8MHz

OSC

)

To 12-bit AT TImer

LTIMER

LTCSR2

TB2F

TB2IE

LTTB2

8-bit TIMEBASE

8-bit AUTORELOAD

LTCNTR

LTARR

COUNTER 2

COUNTER 1

Interrupt request

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LITE TIMER (Cont’d)

11.3.3 Functional Description

11.3.3.1 Timebase Counter 1

The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from 0 at a frequency of f

OSC

/32. An overflow event occurs when the c ounter roll s ov er from F9h to 00h. If f

OSC

= 8 MHz, then the time period between two counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the LTCSR1 register.

When Counter 1 overflows, the TB1F bit is set by hardware and an interrupt reques t is generated if the TB1IE bit is set. The TB1F bit is cleared by software reading the LTCSR1 register.

11.3.3.2 Timebase Counter 2

Counter 2 is an 8-bit aut oreload upcoun ter. It can be read by accessing the LTCNTR register. After an MCU reset, it increments at a frequency of f

OSC

/32 starting from the value stored in the LTARR register. A counter overflow event occurs when the counter rolls over from FFh to the

LTARR reload value. Software can write a new value at anytime in the LTARR register, this value will be automatically loaded in the counter when the next overflow occurs.

When Counter 2 overflows, the TB2F bit in the LTCSR2 register is set by hardware and an interrupt request is generated if the TB2IE bit is set. The TB2F bit is cleared by software reading the LTCSR2 register.

11.3.3.3 Input Capture

The 8-bit input capture register is used to latch the free-running upcounter (Counter 1) 1 after a rising or falling edge is detected on the ICAP1 pin. When an input capture occurs, the ICF bit is set and the LTICR1 register con tains the MSB of Counter 1. An interrupt is generated if the I CIE bit is set. T he ICF bit is cleared by reading the LTICR register.

The LTICR is a read-only register and always contains the data from the last input capture. Input capture is inhibited if the ICF bit is set.

Figure 41. Input Capture Timing Diagram.

04h

8-bit COUNTER 1

01h

OSC

/32

xxh

02h 03h 05h 06h 07h

04h

LTIC PIN

ICF FLAG

LTICRREGISTER

CLEARED

4µs

(@ 8MHz f

OSC

)

CPU

BY S/W

07h

READING

LTIC REGISTER

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LITE TIMER (Cont’d) – The opcode for the HALT instruction is 0x8E. To

– As the HALT instruction clears the I bit in the CC

register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).

11.3.4 Low Power Modes

11.3.5 Interrupts

Note: The TBxF and ICF interrupt events are con-

nected to separate interrupt vectors (see Interrupts chapter).

They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR 2 register and the interrupt mask in the CC register is reset (RIM instruction).

11.3.6 Register Description LITE TIMER CONTROL/STATUS REGISTER 2

(LTCSR2)

Read / Write Reset Value: 0x00 0000 (x0h)

Bits 7:2 = Reserved, must be kept cleared.

Bit 1 = TB2IE

Timebase 2 Interrupt enable

. This bit is set and cleared by software. 0: Timebase (TB2) interrupt disabled 1: Timebase (TB2) interrupt enabled

Bit 0 = TB2F

Timebase 2 Interrupt Flag

. This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No Counter 2 overflow 1: A Counter 2 overflow has occurred

LITE TIMER AUTORELOAD REGISTER (LTARR)

Read / Write Reset Value: 0000 0000 (00h)

Bits 7:0 = AR[7:0]

Counter 2 Reload Value.

These bits regist er is read/write by s oftware. The LTARR value is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs.

Mode Description

SLOW

No effect on Lite timer (this peripheral is driven directly by f

OSC

/32) WAIT No effect on Lite timer ACTIVE-HALT No effect on Lite timer HALT Lite timer stops counting

Interrupt

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Active

Halt

Exit

from

Halt

Timebase 1 Event

TB1F TB1IE Yes Yes No

Timebase 2 Event

TB2F TB2IE Yes No No

IC Event ICF ICIE Yes No No

000000TB2IETB2F

AR7 AR7 AR7 AR7 AR3 AR2 AR1 AR0

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LITE TIMER (Cont’d) LITE TIMER COUNTER 2 (LTCNTR)

Read only Reset Value: 0000 0000 (00h)

Bits 7:0 = CNT[7:0]

Counter 2 Reload Value.

This register is read by software. The LTARR value is automatically loaded into Co unter 2 (LTCNTR) when an overflow occurs.

LITE TIMER CONTROL/STATUS REGISTER (LTCSR1)

Read / Write Reset Value: 0x00 0000 (x0h)

Bit 7 = ICIE

Interrupt Enable.

This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled

Bit 6 = ICF

Input Capture Flag.

This bit is set by hardware and cleared by soft ware by reading the LTICR register. Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred

Note: After an MCU reset, software must initialise the ICF bit by reading the LTICR register

Bit 5 = TB

Timebase period selection.

This bit is set and cleared by software. 0: Timebase period = t

OSC

* 8000 (1ms @ 8 MHz)

1: Timebase period = t

OSC

* 16000 (2ms @ 8

MHz)

Bit 4 = TB1IE

Timebase Interrupt enable

. This bit is set and cleared by software. 0: Timebase (TB1) interrupt disabled 1: Timebase (TB1) interrupt enabled

Bit 3 = TB1F

Timebase Interrupt Flag

. This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No counter overflow 1: A counter overflow has occurred

Bits 2:0 = Reserved

LITE TIMER INPUT CAPTURE REGISTER (LTICR)

Read only Reset Value: 0000 0000 (00h)

Bits 7:0 = ICR[7:0]

Input Capture Value

These bits are read by software and cleared by hardware after a reset. If the ICF bit in the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or fa lling edge occurs on the LTIC pin.

CNT7 CNT7 CNT7 CNT7 CNT3 CNT2 CNT1 CNT0

ICIE ICF TB TB1IE TB1F - - -

ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0

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LITE TIMER (Cont’d) Table 15. Lite Timer Register Map and Reset Values

Address

(Hex.)

Label

76543210

LTCSR2

Reset Value

000000

TB2IE

TB2F

LTARR

Reset Value

AR7

AR6

AR5

AR4

AR3

AR2

AR1

AR0

LTCNTR

Reset Value

CNT7

CNT6

CNT5

CNT4

CNT3

CNT2

CNT1

CNT0

LTCSR1

Reset Value

ICIE

ICF

TB1IE

TB1F

000

LTICR

Reset Value

ICR7

ICR6

ICR5

ICR4

ICR3

ICR2

ICR1

ICR0

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11.4 SERI AL PER IPHERAL INTERFACE (SPI )

11.4.1 Introduction

The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may cons ist of a master and one or more slaves or a system in which devices may be either masters or slaves.

11.4.2 Main Features

■ Full duplex synchronous transfers (on 3 lines)

■ Simplex synchronous transfers (on 2 lines)

■ Master or slave operation

■ Six master mode frequencies (f

CPU

/4 max.)

■ f

CPU

/2 max. slave mode frequency

■ SS Management by software or hardware

■ Programmable clock polarity and phas e

■ End of transfer interrupt flag

■ Write co llision, Master Mo de Fault and Ove r run

flags

11.4.3 General Description

Figure 42 shows the serial peripheral interface

(SPI) block diagram. There are 3 registers:

– SPI Control Register (SPICR) – SPI Control/Status Register (SPICSR) – SPI Data Register (SPIDR)

The SPI is connec ted to ext ernal devices th rough 3 pins:

– MISO: Master In / Slave Out data – MOSI: Master Out / Slave In data – SCK: Serial Clock out by SPI mas ters and in-

put by SPI slaves

–SS

: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS

inputs can be driven by stand-

ard I/O ports on the master

Device.

Figure 42. Serial Peripheral Interface Block Diagram

SPIDR

Read Buffer

8-Bit Shift Register

Write

Read

Data/Address Bus

SPI

SPIE SPE

MSTR

CPHA

SPR0

SPR1CPOL

SERIAL CLOCK

GENERATOR

MOSI

MISO

SCK

CONTROL

STATE

SPICR

SPICSR

Interrupt

request

MASTER

CONTROL

SPR2

SPIF WCOL MODF

OVR SSISSMSOD

SOD

bit

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.3.1 Functional Description

A basic example of interconnections between a single master and a single slave is illustrated in

Figure 43.

The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first).

The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device re-

sponds by sending da ta to the master device via the MISO pin. This implies full duplex communication with both data out an d data in synchronized with the same clock signal (which is provided by the master device via the SCK pin).

To use a single data line, the MISO and MOSI pins must be connected at each node ( in this case only simplex communicati on is possib le).

Four possible data/clock timin g relationships may be chosen (see Figure 46) but m aster and slave must be programmed with the same timing mode.

Figure 43. Single Master/ Single Slave Application

8-BIT SHIFT REGISTE R

SPI

CLOCK

GENERATO R

8-BIT SHIFT REGISTE R

MISO

MOSI

MISO

SCK

SLAVE

MASTER

+5V

MSBit LSBit MSBit LSBit

Not used if SS is managed by software

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.3.2 Slave Select Management

As an alternative to using the SS

pin to control the Slave Select signal, the appli cation c an choose to manage the Slave Select signal by softwa re. This is configured by the SSM bit in the S P ICSR register (see Figure 45)

In software management, the external SS

pin is free for other application uses and t he i nternal SS signal level is driven by writing to the SSI bit in the SPICSR register.

In Master mode:

–SS

internal must be held high continuously

In Slave Mode:

There are two cases depending on the data/clock timing relationship (see Figure 44):

If CPHA=1 (data latched on 2nd clock edge):

–SS

internal must be held low during the entire transmission. T his im plies t hat in s in gle s lave applications the SS

pin either can be t ied to

, or made free for standard I/O by manag-

ing the SS

function by software (SSM= 1 and

SSI=0 in the in the SPICSR register)

If CPHA=0 (data latched on 1st clock edge):

–SS

internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS

is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Section 11.4.5.3).

Figure 44. Generic SS

Timing Dia gram

Figure 45. Hardware/Software Slave Select Management

MOSI/MISO

Master SS

Slave SS

(if CPHA=0)

Slave SS

(if CPHA=1)

Byte 1 Byte 2

Byte 3

SS internal

SSM bit

SSI bit

external pin

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.3.3 Master Mode Operation

In master mode, the serial clock is output on the SCK pin. The c lock f requency, polarity an d phase are configured by software (refer to the description of the SPICSR register).

Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

To operate the SPI in master mode, perform the following two steps in order (if t he SPICSR register is not written first, the SPICR register setting may be not taken into account):

1. Write to the SPICSR register: – Select the clock frequency by configuring the

SPR[2:0] bits.

– Select the clock pola rity and c lock phase by

configuring the CP OL a nd CP HA b its. Figur e

46 shows the four possible configurations.

Note: The slave must have the same CPOL and CPHA settings as the master.

– Either set the SSM bit and s et the SSI bit or

clear the SSM bit and tie the SS

pin high for

the complete byte transmit sequence.

2. Write to the SPICR register: – Set the MSTR and SPE bits

Note: MSTR and SPE bits remain set onl y if SS

is high).

The transmit sequence begins when software writes a byte in the SPIDR register.

11.4.3.4 Master Mode Transmit Sequen ce

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware – An interrupt request is generated if the SPIE

bit is set and the interrupt mask in the C CR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set

2. A read to the SPIDR register.

Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is rea d.

11.4.3.5 Slave Mode Operation

In slave mode, the s erial clock is received on t he SCK pin from the master device.

To operate the SPI in slave mode:

1. W rite to the SPICSR regist er to perform t he following actions:

– Select the clock po larity and clock phase by

configuring the CPOL and CPHA bits (see

Figure 46).

Note: The slave must have the same CPOL and CPHA settings as the master.

– Manage the SS

pin as described in Section

11.4.3.2 and Figure 44. If C PHA=1 SS

must

be held low continuously. If CPHA=0 SS

must be held low during byte transmission and pulled up between each b yte to let the slave write in the shift register.

2. W rite to the SP ICR register to cl ear the MS TR bit and set the SPE bit to enable the SPI I/O functions.

11.4.3.6 Slave Mode Transmit Seq uence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first.

The transmit sequence begins when the slave device receives th e clock si g n al and the most significant bit of the data on its MOSI pin.

When data transfer is c omplete:

– The SPIF bit is set by hardware – An interrupt request is generated if SPIE bit is

set and interrupt mask in the CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set.

2. A write or a read to the SPIDR register.

Notes: While the SPIF bit is se t, all writes to the SPIDR register are inhibited until the SPICSR register is read.

The SPIF bit can be cleared during a second transmission; however, it m ust be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 11.4.5.2).

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.4 Clock Phase and Clock Polarity

Four possible timing relationships may be cho sen by software, using the CPOL an d CPHA bits (Se e

Figure 46).

Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge

Figure 46, shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MIS O pin, the MOSI pin are direct ly connected between the master and the slave device.

Note: If CPOL is changed at the communication byte boundaries, the SPI m ust be disabled by resetting the SPE bit.

Figure 46. D ata Clo c k Ti m in g Di a gram

SCK

MSBit Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 LSBit

MSBit Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 LSBit

MISO

(from master)

MOSI

(from slave)

(to slave)

CAPTURE STROBE

CPHA =1

MSBit Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 LSBit

MSBit Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 LSBit

MISO

(from master)

MOSI

(to slave)

CAPTUR E STROB E

CPHA =0

Note:

This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

(from slave)

(CPOL = 1) SCK

(CPOL = 0)

SCK (CPOL = 1)

SCK (CPOL = 0)

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.5 Error Flags

11.4.5.1 Master Mode Fault (MODF)

Master mode fault occurs when the master device has its SS

pin pulled low.

When a Master mode fault occurs:

– The MODF bit is set and an SPI interrupt re-

quest is generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output

from the Device and disables the SPI peripheral.

– The MSTR bit is reset, thus forcing the Device

into slave mode.

Clearing the MODF bit is done through a software sequence:

1. A read access to the SPICSR register while the MODF bit is set.

2. A write to the SPICR register.

Notes: To avoid any conflicts in an application with multiple slaves, the SS

pin must be pulled high during the MODF bit clearing sequenc e. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence.

Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence.

In a slave device, the MODF bit can not be set, but in a multi master configuration the

Device can be in

slave mode with the MODF bit set. The MODF bit indicates that there might have

been a multi-master conflict and allows software to handle this using an interrupt routine and either perform to a reset o r return to an applicat ion defaul t s ta te.

11.4.5.2 Overrun Con ditio n (OVR )

An overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte.

When an Overrun occurs : – The OVR bit is set and an interrupt request is

generated if the SPIE bit is set.

In this case, the receiver buffer contains t he byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost.

The OVR bit is cleared by reading the SPICSR register.

11.4.5.3 Write Collision Error (WCOL)

A write collision occurs when the softwa re tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful.

Write collisions can occur both in master and slave mode. See also Section 11.4.3.2 Slave Select

Management.

Note: a "read collision" will never occur since the received data b yte is pl aced in a buffer in which access is always synchronous with the CPU operation.

The WCOL bit in the SPICSR register is set if a write collision occurs.

No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software sequence (see Figure 47).

Figure 47. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step

Read SPICSR

Read SPIDR

2nd Step

SPIF =0 WCOL=0

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step

WCOL=0

Read SPICSR

Read SPIDR

Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit

RESULT

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SERIAL PERIPHERAL INTERFACE (Cont ’d)

11.4.5.4 Single Master and Multimaster Configurations

There are two types of SPI systems: – Single Master System – Multimaster System

Single Master System

A typical single master system may be configured, using a

device as the master and four dev ices as

slaves (see Figure 48). The master device selects the individual slave de-

vices by using four pins of a parallel port to control the four SS

pins of the slave devices.

The SS

pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices.

Note: T o prevent a b us conflict on the MISO line the master allows only one active slave device during a transmission.

For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR register.

Other transmission security methods can use ports for handshake lines or dat a bytes with co mmand fields.

Multi-Master System

A multi-master system may al so be configured by the user. Transfer of master control could be implemented using a handshake method through the I/O ports or by an exchange of code messages through the serial peripheral interface system.

The multi-master system is principally handled by the MSTR bit in the SPICR register and the MODF bit in the SPICSR register.

Figure 48. Single Master / Multiple Slave Configuration

MISO

MOSI

MOSI MOSI MOSIMISO MISO MISOMISO

SS SS

SCK SCK

SCK

Ports

Slave

Device

Slave

Device

Slave

Device

Slave

Device

Master

Device

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.6 Low Power Mo des

11.4.6.1 Using the SPI to wak e-up the Device from Halt mode

In slave configuration, the SPI is able to wake-up the

Device from HALT mod e through a SPIF inter-

rupt. The data received is subsequen tly read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware.

Note: When waking up f rom Halt mo de, if the SPI remains in Slave mode, it is recommended to perform an extra communicat ions cycle to bring the SPI from Halt mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately.

Caution: The SPI can wake-up the

Device from

Halt mode only if the Slave Select signal (external

pin or the SSI bit in the SPICSR register) is low

when the

Device enters Halt mode. So if Slave se-

lection is configured as external (see Section

11.4.3.2), make sure the master drives a low level

on the SS

pin when the slave enters Halt mode.

11.4.7 Interrupts

Note: The SPI interrupt events are c onnected to

the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the in terrupt m ask in the CC register is reset (RIM instruction).

Mode Description

WAIT

No effect on SPI. SPI interrupt events cause the Device to exit from WAIT mode.

HALT

SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the Device is woken up

by an interrupt with “exit from HALT mode” capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the Device.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit from Wait

Exit

from

Halt

SPI End of Transfer Event

SPIF

SPIE

Yes Yes

Master Mode Fault Event

MODF Yes No

Overrun Error OVR Yes No

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SERIAL PERIPHERAL INTERFACE (Cont ’d)

11.4.8 Register Description CONTROL REGISTER (SPICR)

Read/Write Reset Value: 0000 xxxx (0xh)

Bit 7 = SPIE

Serial Peripheral Interrupt Enable.

This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever an End

of Transfer event, Master Mode Fault or Overrun error occurs (SPIF=1, MODF=1 or OVR=1 in the SPICSR register)

Bit 6 = SPE

Serial Peripheral Output Enable.

This bit is set and cl eared by software. It is also cleared by hardware when, in master mode, SS

=0 (see Section 11.4.5.1 Master Mode Fault

(MODF)). The SPE bit is c leared by reset, so the

SPI peripheral is not initially connected to the exte rnal pi ns. 0: I/O pins free for general purpose I/O 1: SPI I/O pin alternate functions enabled

Bit 5 = SPR2

Divider Enable

. This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 16 S PI Mas ter

mode SCK Frequency.

0: Divider by 2 enabled 1: Divider by 2 disabled

Note: This bit has no effect in slave mode.

Bit 4 = MSTR

Master Mode.

This bit is set and cl eared by software. It is also cleared by hardware when, in master mode, SS

=0 (see Section 11.4.5.1 Master Mode Fault

(MODF)).

0: Slave mode 1: Master mode. The function of the SCK pin

changes from an input to an output and the functions of the MISO and MOSI pins are reversed.

Bit 3 = CPOL

Clock Polarity.

This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: SCK pin has a low level idle state 1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication byte boundaries, the SPI m ust be disabled by resetting the SPE bit.

Bit 2 = CPHA

Clock Phase.

This bit is set and cleared by software. 0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Note: The s lave must have the same CPOL and CPHA settings as the master.

Bits 1:0 = SPR[1:0]

Serial Clock Frequency.

These bits are set and cleared by software. Used with the SPR2 bit, they select the baud rate of the SPI serial clock SCK output by the SPI in master mode.

No te : These 2 bits have no effect in slave mode. Table 16. SPI Master mode SCK Frequency

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

Serial Clock SPR2 SPR1 SPR0

CPU

/4 1 0 0

CPU

/8 0 0 0

CPU

/16 0 0 1

CPU

/32 1 1 0

CPU

/64 0 1 0

CPU

/128 0 1 1

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SERIAL PERIPHERAL INTERFACE (Cont ’d) CONTROL/STATUS REGISTER (SPICSR)

Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h)

Bit 7 = SPIF

Serial Peripheral Data Transfer Flag

(Read only).

This bit is set by hardware when a t ransfer has been completed. An interrupt is generated if SPIE=1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register).

0: Data transfer is in progress or the flag has been

cleared.

1: Data transfer between the

Device and an exter-

nal device has been completed.

Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is rea d.

Bit 6 = WCOL

Write Collision status (Read only).

This bit is set by hardware when a write to the SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see

Figure 47).

0: No write collision occurred 1: A write collision has been detected

Bit 5 = OVR S

PI Overrun error (Read only).

This bit is set by hardware when the byte currently being received in the shift register is ready to b e transferred into the SPIDR register while SPIF = 1 (See Section 11.4.5.2). An interrupt is generated if SPIE = 1 in SPICSR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected

Bit 4 = MO DF

Mode Fault flag (Read only).

This bit is set by hardware when the SS pin is pulled low in master mode (see Sect ion 11.4.5.1

Master Mode Fault (MODF)). An SPI interrupt can

be generated if SPIE=1 in the SPICSR register. This bit is cleared by a software sequence (An access to the SPICSR register while MODF=1 followed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected

Bit 3 = Reserved, must be kept cleared.

Bit 2 = SOD

SPI Output Disable.

This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE=1) 1: SPI output disabled

Bit 1 = SSM

SS Ma nagem ent .

This bit is set and cleared by software. When set, it disables the alternate func tion of the SPI SS

and uses the SSI bit value instead. See Section

11.4.3.2 Slave Select Management.

0: Hardware management (SS

managed by exter-

nal pin)

1: Software management (internal SS

signal con-

trolled by SSI bit. External SS

pin free for gener-

al-purpose I/O)

Bit 0 = SSI

SS Internal Mode.

This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of the SS

slave select signal when the SSM bit is set. 0 : Slave selected 1 : Slave deselected

DATA I/O REGISTER (SPIDR)

Read/Write Reset Value: Undefined

The SPIDR register is used to t ransmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte.

Notes: During the last clock cy cle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read.

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.

Warning: A write to the SPIDR register places data directly into the shift register f or t ransmission.

A read to the SPIDR register returns the value located in the buffer and not the co ntent of the shift register (see Figure 42).

SPIF WCOL OVR MO DF - SOD SSM SSI

D7 D6 D5 D4 D3 D2 D1 D0

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Table 17. SPI Register Map and Reset Values

Address

(Hex.)

Label

76543210

0031h

SPIDR

Reset Value

MSB

xxxxxxx

LSB

0032h

SPICR

Reset Value

SPIE

SPE

SPR2

MSTR

CPOL

CPHA

SPR1

SPR0

0033h

SPICSR

Reset Value

SPIF

WCOL

OVR

MODF

SOD

SSM

SSI

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11.5 10-BIT A/D CONVERTER (ADC)

11.5.1 Introduction

The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sampl e and hold circuitry. This peripheral has up to 7 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the ana log voltage levels from up to 7 different sources.

The result of the conversion is stored in a 10-bit Data Register. The A/D converter is controlled through a Control/Status Register.

11.5.2 Main Features

■ 10-bit conversion

■ Up to 7 channels with multiplexed input

■ Linear successive approximation

■ Data register (DR) which contains the results

■ Conversion complete status flag

■ On/off bit (to reduce consumption)

The block diagram is shown in Figure 49.

11.5.3 Functional Description

11.5.3.1 Analog Power Supply

DDA

and V

SSA

are the high and low level reference voltage pins. In some devices (refer to device pin out description) they are internally connected to the V

and VSS pins.

Conversion accuracy may therefore be impacted by voltage drops a nd noise in the event o f h eavily loaded or badly decoupled power supply lines.

Figure 49. ADC Block Diagram

CH2 CH1EOC SPEEDAD ON 0 CH0

ADCCSR

AIN0

AIN1

ANALOG TO DIGITAL

CONVERTER

AINx

ANALOG

MUX

D4 D3D5D9 D8 D7 D6 D2

ADCDRH

D1 D0

ADCDRL 00 0

AMP

SLOW

AMP

ADC

HOLD CONTROL

x 1 or x 8

AMPSEL

bit

SEL

ADC

CPU

DIV 2

DIV 4

SLOW

bit

CAL

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10-BIT A/D CONVERTER (ADC) (Cont’d)

11.5.3.2 Input Voltage Amplifier

The input voltage can be amplified by a factor of 8 by enabling the AMPSEL bit in the ADCDRL register.

When the amplifier is enab led, the input range is 0V to V

/8.

For example, if V

= 5V, then the ADC can convert voltages in the range 0V to 430mV with an ideal resolution of 0.6mV (equivalent to 13-bit resolution with reference to a V

to VDD range).

For more details, refer to the Electrical characteristics section.

Note: The amp lifier is switched on by the A DON bit in the ADCCSR register, so no additional startup time is required when the amplifier is selected by the AMPSEL bit.

11.5.3.3 Digital A/D Conversion Result

The conversion is monotonic, meaning that the result never decreases if the analog i nput does not and never increases if the analog input does not.

If the input voltage (V

AIN

) is greater than V

DDA

(high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication).

If the input voltage (V

AIN

) is lower than V

SSA

(lowlevel voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h.

The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is described in the Electrical Characteristics Section.

AIN

is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time.

11.5.3.4 A/D Conversion

The analog input ports mus t be con figured as input, no pull-up, no interrupt. Refer to the «I/O ports» chapter. Using these pins as analog inputs does not affect the ability of the port to be rea d as a logic input.

In the ADCCSR register:

– Select the CS[2:0] bits to assign the analog

channel to convert.

ADC Conversion mode

In the ADCCSR register: Set the ADON bit to enable the A/D converter and

to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel.

When a conversion is complete:

– The EOC bit is set by hardware. – The result is in the ADCDR registers.

A read to the ADCDRH resets the EOC bit.

To read the 10 bits, perform the following steps:

1. Poll EOC bit

2. Read ADCDRL

3. Read ADCDRH. This clears EOC automatically.

To read only 8 bits, perform the following steps:

1. Poll EOC bit

2. Read ADCDRH. This clears EOC automatically.

11.5.4 Low Power Modes

Note: The A/D converter may be disabled by re-

setting the ADON bit. This feature allows reduced power consumptio n when no conv ersion is needed and between single shot conversions.

11.5.5 Interrupts

None.

Mode Description

WAIT No effect on A/D Converter

HALT

A/D Converter disabled. After wakeup from Halt mode, the A/D

Converter requires a stabilization time t

STAB

(see Electrical Characteristics) before accurate conversions can be performed.

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10-BIT A/D CONVERTER (ADC) (Cont’d)

11.5.6 Register Description CONTROL/STA TUS REGISTER (ADCCSR)

Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h)

Bit 7 = EO C

End of Conversion

This bit is set by hardware. It is cleared by software reading the ADCDRH register. 0: Conversion is not complete 1: Conversion complete

Bit 6 = SPEED

ADC clock selection

This bit is set and cleared by software. It is used together with the SLOW bit to configure the ADC clock speed. Refer to the table in the SLOW bit description.

Bit 5 = ADON

A/D Converter on

This bit is set and cleared by software. 0: A/D converter and amplifier are switched off 1: A/D converter and amplifier are switched on

Bit 4:3 = Reserved. Must be kept cleared.

Bit 2:0 = CH[2:0]

Channel Selection

These bits are set and cleared by software. They select the analog input to convert.

*The number of chann els is device dependent. Refer to the device pinout description.

DATA REGISTER HIGH (ADCDRH)

Read Only Reset Value: xxxx xxxx (xxh)

Bit 7:0 = D[9:2]

MSB of Analog Converted Value

AMP CONTROL/DATA REGISTER LOW (ADCDRL)

Read/Write Reset Value: 0000 00xx (0xh)

Bit 7:5 = Reserved. Forced by hardware to 0.

Bit 4 = AMPCAL

Amplifier Calibration Bit

This bit is set and cleared by software. 0: Calibration off 1: Calibration on. The input voltage of the amp is

set to 0V.

Bit 3 = SLOW

Slow mode

This bit is set and cleared by software. It is used together with the SPEED bit to configure the ADC clock speed as shown on the table below.

Bit 2 = AMPSEL

Amplifier Selection Bit

This bit is set and cleared by software. 0: Amplifier is not selected 1: Amplifier is selected

Note: Wh en AMPSEL=1 it is mandatory that f

ADC

be less than or equal to 2 MHz.

Bit 1:0 = D[1:0]

LSB of Analog Converted Value

EOC SPEED ADON 0 CH3 CH2 CH1 CH0

Channel Pin* CH2 CH1 CH0

AIN0 0 0 0 AIN1 0 0 1 AIN2 0 1 0 AIN3 0 1 1 AIN4 1 0 0 AIN5 1 0 1 AIN6 1 1 0

D9 D8 D7 D6 D5 D4 D3 D2

000

AMP

CAL

SLOW

AMP-

SEL

D1 D0

ADC

SLOW SPEED

CPU

/2 00

CPU

/4 1x

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Table 18. ADC Register Map and Reset Values

Address

(Hex.)

Label

76543210

0034h

ADCCSR

Reset Value

EOC

SPEED0ADON

0 0

CH2

CH1

CH0

0035h

ADCDRH

Reset Value

0036h

ADCDRL

Reset Value

0 0

AMPCAL0SLOW0AMPSEL

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12 INSTRUCTION SET

12.1 ST7 ADDRESSING MODES

The ST7 Core features 17 different addressing modes which can be classified in 7 main groups:

The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do

so, most of the ad dressing modes may be subdivided in two sub-modes called long and short:

– Long address ing mode is more powerful be-

cause it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles.

– Short addressing mode is less powerful because

it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

The ST7 Assembler optimizes the use of long and short addressing modes.

Table 19. ST7 Addressing Mode Overview

Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-

ing JRxx.

Addressing Mode Example

Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset byte,#5

Mode Syntax

Destination/

Source

Pointer

Address

(Hex.)

Pointer

Size

(Hex.)

Length (Bytes)

Inherent nop + 0 Immediate ld A,#$55 + 1 Short Direct ld A,$10 00..FF + 1 Long Direct ld A,$1000 0000..FFFF + 2

No Offset Direct Indexed ld A,(X) 00..FF

+ 0 (with X register)

+ 1 (with Y register) Short Direct Indexed ld A,($10,X) 00..1FE + 1 Long Direct Indexed ld A,($1000,X) 0000..FFFF + 2 Short Indirect ld A,[$10] 00..FF 00..FF byte + 2 Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word + 2 Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte + 2 Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word + 2 Relative D irect jrne loop PC -128 /PC+1 27

+ 1 Relative I ndire ct jrne [$10] PC-128/PC+1 27

00..FF byte + 2 Bit Direct bset $10,#7 00..FF + 1 Bit Indirect bset [$10],#7 00..FF 00..FF byte + 2 Bit Direct Relative btjt $10,#7,skip 00..FF + 2 Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte + 3

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ST7 ADDRESSING MODES (Cont’d)

12.1.1 Inherent

All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.

12.1.2 Immediate

Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.

12.1.3 Direct

In Direct instructions, the operands are referenced by their memory address.

The direct addressin g mode consists of two submodes:

Direct (short)

The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space.

Direct (lon g)

The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.

12.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset.

The indirect addressing mode consists of three sub-modes:

Indexed (No Offset)

There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space.

Indexed ( S hort)

The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space.

Indexed (long)

The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 by tes after the opcode.

12.1.5 Indirect (Short, Long)

The required data byte to do the operation is found by its memory address, located in memory (pointer).

The pointer ad dress f ollows the opcode. The i ndirect addressing mode consists of two sub-modes:

Indirec t (sho rt )

The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode.

Indirect (long)

The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.

Inherent Instruction Function

NOP No operation TRAP S/W Interrupt

WFI

Wait For Interrupt (Low Power Mode)

HALT

Halt Oscillator (Lowest Power

Mode) RET Sub-routine Return IRET Interrupt Sub-routine Return SIM Set Interrupt Mask RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplicatio n SLL, SRL, SRA, RLC,

RRC

Shift and Rotate Operations SWAP Swap Nibbles

Immediate Instruction Function

LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations

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ST7 ADDRESSING MODES (Cont’d)

12.1.6 Indi rect Indexe d (Short, Lo ng )

This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode.

The indirect indexed addressing mode consists of two sub-modes:

Indirect Indexed (Short)

The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode.

Indirect In dex ed (Long)

The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.

Table 20. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes

12.1.7 Relative Mode (Direct, Indirect)

This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it.

The relative addressing mode consists of two submodes:

Relative (Direct)

The offset follows the opcode.

Relative (Indirect)

The offset is defined in memory , of which the address follows the opcode.

Long and Short

Instructions

Function

LD Load CP Compare AND, OR, XOR Logical Operations

ADC, ADD, SUB, SBC

Arithmetic Addition/subtraction operations

BCP Bit Compare

Short Instructions Only Function

CLR Clear INC, DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement BSET, BRES Bit Operations

BTJT, BTJF

Bit Test and Jump Operations

SLL, SRL, SRA, RLC, RRC

Shift and Rotate Operations

SWAP Swap Nibbles CALL, JP Call or Jump subroutine

Available Relative Direct/

Indirect Instructions

Function

JRxx Conditional Jump CALLR Call Relative

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12.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may

be subdivided into 13 main groups as illustrated in the following table:

Using a pre-byte

The instructions are described with one to four bytes.

In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are def ined. These prebytes modify the meaning of the instruction they precede.

The whole instruction becomes:

PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 A dditional word (0 to 2) according to the

number of bytes required to compute the effective address

These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode . The prebytes are:

PDY 90 Replace an X based instruction using

immediate, direct, indexed, or inherent addressing mode by a Y one.

PIX 92 Repla ce an instruction us ing direct, di-

rect bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.

PIY 91 Replace an instructi on using X indirect

indexed addressing mode by a Y one.

Load and Transfer LD CLR Stack operation PUSH POP RSP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Condition Code Flag modification SIM RIM SCF RCF

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INSTRUCTION GROUPS (Cont’d)

Mnemo Description Function/Example Dst Src H I N Z C

ADC Add with Carry A = A + M + C A M H N Z C ADD Addition A = A + M A M H N Z C AND Logical And A = A . M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subro utine CALLR Call subroutine relative CLR Clear reg, M 0 1 CP Arithmetic Compare tst(Reg - M) reg M N Z C CPL One Complement A = FFH-A reg, M N Z 1 DEC Decrement dec Y reg, M N Z HALT Halt 0 IRET Interrupt routine return Pop CC, A, X, PC H I N Z C INC Increment inc X reg, M N Z JP Absolute Jump jp [TBL.w] JRA Jump relative always JRT Jump relative JRF Never jump jrf * JRIH Jump if ext. interrupt = 1 JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H = 1 ? JRNH Jump if H = 0 H = 0 ? JRM Jump if I = 1 I = 1 ? JRNM Jump if I = 0 I = 0 ? JRMI Jump if N = 1 (minus) N = 1 ? JRPL Jump if N = 0 (plus) N = 0 ? JREQ Jump if Z = 1 (equal) Z = 1 ? JRNE Jump if Z = 0 (not equal) Z = 0 ? JRC Jump if C = 1 C = 1 ? JRNC Jump if C = 0 C = 0 ? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned >

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INSTRUCTION GROUPS (Cont’d)

Mnemo Description Function/Example Dst Src H I N Z C

JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg N Z MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0 NEG Negate (2’s compl) neg $10 reg, M N Z C NOP No Operation OR OR operation A = A + M A M N Z POP Pop from the Stack pop reg reg M

pop CC CC M H I N Z C PUSH Push onto the Stack push Y M reg, CC RCF Reset carry flag C = 0 0 RET Subroutine Return RIM Enable Interrupts I = 0 0 RLC Rotate left true C C <= Dst <= C reg, M N Z C RRC Rotate right true C C => Dst => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Subtract with Carry A = A - M - C A M N Z C SCF Set carry flag C = 1 1 SIM Disable Interrupts I = 1 1 SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C SLL Shift left Logic C <= Dst <= 0 reg, M N Z C SRL Shift right Logic 0 => Dst => C reg, M 0 Z C SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C SUB Subtraction A = A - M A M N Z C SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z TNZ Test for Neg & Zero tnz lbl1 N Z TRAP S/W trap S/W interrupt 1 WFI Wait for Interrupt 0 XOR Exclusive OR A = A XOR M A M N Z

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13 ELECTRICAL CHARACTERISTICS

13.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are referred to V

13.1.1 Minimum and Maximum val ues

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of am bient temperature, supp ly voltage an d frequencies by tests in production on 100% of the devices with an ambient temp erature at T

=25°C

and T

A=TA

max (given by the selected temperature

range). Data based on characterization results, design

simulation and/or technology characteristics are indicated in the ta ble footnotes a nd are not tested in production. Based on chara cterization, th e minimum and maximum values refer to sampl e tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ).

13.1.2 Typical values

Unless otherwise specified, typical data are based on T

=25°C, VDD=5V (for the 4.5V≤VDD≤5.5V

voltage range) and V

=3.3V (for the 3V≤VDD≤4V voltage range). They are given only as design guidelines and are not tested.

13.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

13.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in F igure 50.

Figure 50. Pin loading conditions

13.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 51.

Figure 51. Pin input voltage

ST7 PIN

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13.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and f unctional operation of the device under these cond i-

tions is not implied. Exposure to maxim um rating conditions for extended periods may affect device reliabili ty.

13.2.1 Voltage Characteristics

13.2.2 Current Characteristics

13.2.3 Thermal Characteristics

Notes:

1. Directly connectin g the RES ET

and I/O pins to VDD or V

could damage the dev ice if an uni ntenti onal int ernal re set is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, th is connectio n has to be don e through a p ull-up or pull- down resisto r (typical: 4.7 kΩ for RESET

, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration.

2. When the current limitation is not possible , the V

absolute m aximum rating m ust be respected, otherwis e refer to

INJ(PIN)

specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.

3. All power (V

) and ground (VSS) lines must always be connected to the external supply.

4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:

- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits)

- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as far as possible from the analog input pins.

5. When several inputs are submitted to a current injection , the maximum ΣI

INJ(PIN)

is the absolute sum of the positive

and negative injected currents (instantaneous values). These results are based on characterisation with ΣI

INJ(PIN)

maxi-

mum current injection on four I/O port pins of the device.

Symbol Ratings Maximum value Unit

- V

Supply voltage 7.0

Input voltage on any pin

1) & 2)

VSS-0.3 to VDD+0.3

ESD(HBM)

Electrostatic discharge voltage (Human Body Model)

see section 13.7.3 on page 104

ESD(MM)

Electrostatic discharge voltage (Machine Model)

Symbol Ratings Maximum value Unit

VDD

Total current into VDD power lines (source)

150

VSS

Total current out of VSS ground lines (sink)

150

Output current sunk by any standard I/O and control pin 25 Output current sunk by any high sink I/O pin 50 Output current source by any I/Os and control pin - 25

INJ(PIN)

2) & 4)

Injected current on ISPSEL pin ± 5

Injected current on RESET

pin ± 5 Injected current on OSC1 and OSC2 pins ± 5 Injected current on any other pin

± 5

INJ(PIN)

Total injected current (sum of all I/O and control pins)

± 20

Symbol Ratings Value Unit

STG

Storage temperature range -65 to +150 °C

Maximum junction temperature (see Table 21, “THERMAL CHARACTERISTICS,” on page 121)

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13.3 OPERATING CONDITIONS

13.3.1 General Operating Conditions: Suffix 6 Devices

= -40 to +85°C unless otherwise specified.

Figure 52. f

CLKIN

Maximum Operating Frequ enc y Vers us V

Supply Voltage

Symbol Parameter Conditions Min Max Unit

Supply voltage

OSC

= 8 MHz. max., TA = 0 to 70°C 2.4 5.5

OSC

= 8 MHz. max. 2.7 5.5

OSC

= 16 MHz. max. 3.3 5.5

CLKIN

External clock frequency on CLKIN pin

≥

3.3V 0 16 MHzV

≥

2.4V, T

A =

0 to +70°C

≥

2.7V

CLKIN

[MHz]

SUPPLY VOLTAGE [V]

4 1

2.0 2.4

3.3 3.5 4.0 4.5 5.0

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

5.5

FUNCTIONALITY GUARANTEED IN THIS AREA (UNLESS OTHERWISE STATED IN THE TABLES OF PARAME T R I C DAT A)

2.7

FUNCTIONALITY

GUARANTEED

IN THIS AREA

AT T

0 to 70° C

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13.3.2 Operating Condition s with Low Voltage Detector (LVD)

= -40 to 125°C, unless otherwise specified

Note:

1. Not tested in production.

2. Not tested in production. The V

rise time rate condition is needed to insure a correct device power-on and LVD reset.

When the V

slope is outside these values, the LVD may not ensure a proper reset of the MCU.

13.3.3 Auxiliary Voltage Detector (AVD) Thresholds

= -40 to 125°C, unless otherwise specified

Note:

1. Not tested in production.

13.3.4 Internal RC Oscillator and PLL

The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte).

Symbol Parameter Conditions Min Typ Max Unit

IT+

(LVD)

Reset release threshol d (V

rise)

High Threshold Med. Threshold Low Threshold

4.00

3.40

2.65

4.25

3.60

2.90

4.50

3.80

3.15 V

IT-

(LVD)

Reset generation threshold (V

fall)

High Threshold Med. Threshold Low Threshold

3.80

3.20

2.40

4.05

3.40

2.70

4.30

3.65

2.90

hys

LVD voltage threshold hysteresis V

IT+

(LVD)

-V

IT-

(LVD)

200 mV

POR

VDD rise time rate

20 20000

s/V

g(VDD)

Filtered glitch delay on V

Not detected by the LVD 150 ns

DD(LVD

) LVD/AVD current consumption 245 µA

Symbol Parameter Conditions Min Typ Max Unit

IT+

(AVD)

1=>0 AVDF flag toggle threshold (V

rise)

High Threshold Med. Threshold Low Threshold

4.40

3.90

3.20

4.70

4.10

3.40

5.00

4.30

3.60 V

IT-

(AVD)

0=>1 AVDF flag toggle threshold (V

fall)

High Threshold Med. Threshold Low Threshold

4.30

3.70

2.90

4.60

3.90

3.20

4.90

4.10

3.40

hys

AVD voltage threshold hysteresis V

IT+

(AVD)

-V

IT-

(AVD)

150 mV

∆

IT-

Voltage drop between AVD flag set and LVD reset activation

fall 0.45 V

Symbol Parameter Conditions Min Typ Max Unit

DD(RC)

Internal RC Oscillator operating voltage 2.4 5.5

DD(x4PLL)

x4 PLL operating voltage 2.4 3.3

DD(x8PLL)

x8 PLL operating voltage 3.3 5.5

STARTUP

PLL Startup time 60

PLL input clock

PLL

)

cycles

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OPERATING CONDITIONS (Cont’d) The RC oscillator and PLL characteristics are temperature-dependent and are grouped in four tables.

13.3.4.1 Devices with ‘”6” order code suffix (tested for T

= -40 to +85°C) @ VDD = 4.5 to 5.5V

Notes:

1. Data based on characterization results, not tested in production

2. RCCR0 is a factory-calibrated setting for

1000kHz with ±

0.2 accuracy @ T

=25°C, VDD=5V. See “INTERNAL RC OS-

CILLATOR ADJUSTMENT” on page 23

3. Guaranteed by design.

4. Averaged over a 4ms period. After the LOCKED bit is set, a period of t

STAB

is required to reach ACC

PLL

accuracy.

5. After the LOCKED bit is set ACC

PLL

is max. 10% until t

STAB

has elapsed. See Figure 12 on page 24.

Symbol Parameter Conditions Min Typ Max Unit

Internal RC oscillator frequency

RCCR = FF (reset value), T

=25°C,VDD=5V 760

kHz

RCCR = RCCR0

2 )

,TA=25°C,VDD=5V 1000

ACC

Accuracy of Internal RC oscillator with RCCR=RCCR0

TA=25°C,VDD=4.5 to 5.5V -1

=-40 to +85°C,VDD=5V -5 +2 %

=0 to +85°C,VDD=4.5 to 5.5V -2

DD(RC)

RC oscillator current consumption

=25°C,VDD=5V 970

µA

su(RC)

RC oscillator setup time TA=25°C,VDD=5V 10

PLL

x8 PLL input clock 1

MHz

LOCK

PLL Lock time

2ms

STAB

PLL Stabilization time

4ms

ACC

PLL

x8 PLL Accuracy

= 1MHz@TA=25°C,VDD=4.5 to 5.5V 0.1

= 1MHz@TA=-40 to +85°C,VDD=5V 0.1

w(JIT)

PLL jitter period fRC = 1MHz 8

kHz

JIT

PLL

PLL jitter (∆f

CPU/fCPU

DD(PLL)

PLL current consumption TA=25°C 600

µA

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OPERATING CONDITIONS (Cont’d)

13.3.4.2 Devices with ‘”6” order code suffix (tested for T

= -40 to +85°C) @ VDD = 2.7 to 3.3V

Notes:

1. Data based on characterization results, not tested in production

2. RCCR1 is a factory-calibrated setting for

700MHz with ±

0.2 accuracy @ T

=25°C, VDD=3V. See “INTERNAL RC OS-

CILLATOR ADJUSTMENT” on page 23.

3. Guaranteed by design.

4. Averaged over a 4ms period. After the LOCKED bit is set, a period of t

STAB

is required to reach ACC

PLL

accuracy

5. After the LOCKED bit is set ACC

PLL

is max. 10% until t

STAB

has elapsed. See Figure 12 on page 24.

Symbol Parameter Conditions Min Typ Max Unit

Internal RC oscillator frequency

RCCR = FF (reset value), T

=25°C, VDD= 3.0V 560

kHz

RCCR=RCCR 1

,TA=25°C,VDD= 3V 700

ACC

Accuracy of Internal RC oscillator when calibrated with RCCR=RCCR1

1)2)

TA=25°C,VDD=3V -2 +2 % T

=25°C,VDD=2.7 to 3.3V -25 +25 %

=-40 to +85°C,VDD=3V -15 15 %

DD(RC)

RC oscillator current consumption

=25°C,VDD=3V 700

µA

su(RC)

RC oscillator setup time TA=25°C,VDD=3V 10

PLL

x4 PLL input clock 1

MHz

LOCK

PLL Lock time

2ms

STAB

PLL Stabilization time

4ms

ACC

PLL

x4 PLL Accuracy

= 1MHz@TA=25°C,VDD=2.7 to 3.3V 0.1

= 1MHz@TA=40 to +85°C,VDD= 3V 0.1

w(JIT)

PLL jitter period fRC = 1MHz 8

kHz

JIT

PLL

PLL jitter (∆f

CPU/fCPU

DD(PLL)

PLL current consumption TA=25°C 190

µA

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OPERATING CONDITIONS (Cont’d) Figure 53. RC Osc Freq vs V

@ TA=25°C

(Calibrated with RCCR1: 3V @ 25°C)

Figure 54. RC Osc Freq vs V

(Calibrated with RCCR0: 5V@ 25°C)

Figure 55.

Typical RC oscillator Accuracy vs

temperature @ V

=5V

(Calibrated with RCCR0: 5V @ 25°C

Figure 56. RC Osc Freq vs V

and RCCR Value

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1.00

2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 VDD (V)

Output Freq (MHz)

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

1.10

2.5 3 3.5 4 4.5 5 5.5 6 Vdd (V)

Output Freq. (M Hz)

-45° 0° 25° 90° 105° 130°

-1

-5

-45 025 85

-2

-4

-3

(*)

(

)

(

)

(*) tested in production

Temperature (°C)

RC Accuracy

125

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

1.60

1.80

2.4 2.7 3 3.3 3.75 4 4.5 5 5.5 6 Vdd (V)

Output Freq. (MHz)

rccr=00h rccr=64h rccr=80h rccr=C0h rccr=FFh

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OPERATING CONDITIONS (Cont’d) Figure 57. PLL ∆f

CPU/fCPU

versus time

Figure 58. PLLx4 Output vs CLKIN frequency

Note: f

OSC

= f

CLKIN

/2*PLL4

Figure 59. PLLx8 Output vs CLKIN frequency

Note: f

OSC

= f

CLKIN

/2*PLL8

13.3.4.3 32MHz PLL

= -40 to 125°C, unless otherwise specified

Note 1: 32 MHz is guaranteed within this voltage range.

w(JIT)

∆

CPU/fCPU

Min

Max

w(JIT)

1.00

2.00

3.00

4.00

5.00

6.00

7.00

1 1.5 2 2.5 3

Ex t ernal I n put Cl oc k Frequency (MHz)

Output Frequency (MHz)

3.3 3

2.7

1.00

3.00

5.00

7.00

9.00

11.00

0.85 0.9 1 1.5 2 2.5

Ex ternal Input Clock Frequency (MHz)

Output Frequency (MHz)

5.5 5

4.5 4

Symbol Parameter Min Typ Max Unit

Voltage

4.5 5 5.5 V

PLL32

Frequency

32 MHz

INPUT

Input Frequency

89MHz

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13.4 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total de-

vice consumption, the two current values must be added (except for HA LT m ode fo r which th e clock is stopped).

13.4.1 Supply Current

= -40 to +125°C unless otherwise specified

Notes:

1. CPU running with memory access, all I/O pins in input mode with a static value at V

or VSS (no load), all peripherals

in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

2. All I/O pins in input mode with a static value at V

or VSS (no load), all peripherals in reset state; clock input (CLKIN)

driven by external square wave, LVD disabled.

3. SLO W mo de sele cted with f

CPU

based on f

OSC

divided by 32. Al l I/O pin s in inpu t mod e with a static v alue at VDD or

(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

4. SLO W-WAIT mod e selected with f

CPU

based on f

OSC

divided by 32. All I/O pins in input mode with a static val ue at

or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

5. All I/O pins in input mode with a static value at V

or VSS (no load). Data tested in production at VDD max. and f

CPU

max.

6. This consumption refers to the Halt period only and not the associated run period which is software dependent.

Figure 60. Typical IDD in RUN vs. f

CPU

Figure 61. Typical IDD in SLOW vs. f

CPU

Symbol Parameter Conditions Typ Max Unit

Supply current in RUN mode

=5.5V

CPU

=8MHz

7.5 12 mA

Supply current in WAIT mode f

CPU

=8MHz

3.7 6

Supply current in SLOW mode f

CPU

=500kHz

1.6 2.5

Supply current in SLOW WAIT mode f

CPU

=500kHz

1.6 2.5

Supply current in HALT mode

-40°C≤T

≤

+85°C

110

+125°C

15 50

Supply current in AWUFH mode

5)6)

+25°C

20 30

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

2 2.5 3 3.5 4 4.5 5 5.5 6

Vdd (V)

Idd (mA)

8 MHz 4 MHz 1 MHz

TBD

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

22.533.544.555.56

Vdd (V)

Idd (mA)

250 KHz 125 KHz

62.5 Khz

ST7LITE2

100/131

SUPPLY CURRENT CHARACTERISITCS (Cont’d) Figure 62. Typical I

in WAIT vs. f

CPU

Figure 63. Typical IDD in SLOW-WAIT vs. f

CPU

Figure 64. Typical IDD in AWUFH mode at T

=25°C

Figure 65. Typical I

vs. Temperature

at V

= 5V and f

CPU

= 8MHz

13.4.2 On-chip peripherals

1. Data based on a differential IDD measurement between reset configuration (timer stopped) and a timer running in PWM mode at f

cpu

=8MHz.

2. Data based on a differential I

measurement between reset configuration and a permanent SPI master communica-

tion (data sent equal to 55h).

3. Data based on a differential I

measurement between reset configuration and continuous A/D conversions with am-

plifier off.

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

2 2.5 3 3.5 4 4.5 5 5.5 6

Vdd (V)

Idd (mA)

250 KHz 125 KHz

62.5 Khz

TBD

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

2 2.5 3 3.5 4 4.5 5 5.5 6

Vdd (V)

Idd (mA)

250 KHz 125 KHz

62.5 Khz

0.000

0.005

0.010

0.015

0.020

0.025

0.030

0.035

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Vdd(V)

Idd(mA)

fawu_rc ~125 KHz

2.0

3.0

4.0

5.0

6.0

7.0

8.0

2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6

Vdd (V)

Idd (mA)

25°

-45° 90° 130°

Symbol Parameter Conditions Typ Unit

DD(AT)

12-bit Auto-Reload Timer supply current

CPU

=4MHz V

3.0V 50

CPU

=8MHz V

5.0V 150

DD(SPI)

SPI supply current

CPU

=4MHz V

3.0V 50

CPU

=8MHz V

5.0V 300

DD(ADC)

ADC supply current when converting

ADC

=4MHz

3.0V TBD

5.0V TBD

SGS Thomson Microelectronics ST7FLITE29F2M6, ST7FLITE29F2B6, ST7FLITE29, ST7FLITE25F2M6, ST7FLITE25F2B6 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual