SGS Thomson Microelectronics ST72141K2, ST72141 Datasheet

Rev. 1.3

April 2000 1/132

This ispreliminary information on anew product in development or undergoing evaluation. Details are subject tochange without notice.

ST72141K

8-BIT MCU WITH ELECTRIC-MOTOR CONTROL,

ADC, 16-BIT TIMERS, SPI INTERFACE

PRODUCT PREVIEW

■ Memories

– 8K Program memory

(ROM/OTP/EPROM)

– 256 Bytes RAM

■ Clock, Reset and Supply Management

– Enhanced reset system
– Low voltage supply supervisor
– 3 Power saving modes

■ 14 I/O Ports

– 14 multifunctional bidirectional I/O lines with:

External interruptcapability (2 vectors), 13 al­ternate function lines, 3 high sink outputs

■ Motor Control peripheral

– 6 PWM output channels
– Emergency pin toforce outputs to HiZ state
– 3 analog inputs for rotor position detection

with no need for additional sensors

– Comparator for current limitation

■ 3 Timers

– Two 16-bittimers with: 2 input captures, 2out-

put compares,external clock input, PWM and
Pulse generator modes

– Watchdog timer for system integrity

■ Communications Interface

– SPI synchronous serial interface

■ Analog Peripheral

– 8-bit ADC with 8 input pins

■ Instruction Set

– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation

■ Development Tools

– Full hardware/softwaredevelopment package

Device Summary

SDIP32

SO34S

Features ST72141K2

Program memory - bytes 8K
RAM (stack) - bytes 256 (64)

Peripherals

Motor control,

Watchdog, Two 16-bit timers,

SPI, ADC
Operating Supply 3.5V to 5.5V
CPU Frequency 4 or 8 MHz (with 8 or 16 MHz oscillator)
Operating Temperature -40°C to +85°C
Packages SO34 / SDIP32

1

Table of Contents

132

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2

1 GENERAL DESCRIPTION . . . . . . ................................................ 5

1.1 INTRODUCTION . . . . . .. . . . . . ............................................. 5

1.2 PIN DESCRIPTION . . ..................................................... 6

1.3 EXTERNAL CONNECTIONS . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ......... 9

1.4 REGISTER & MEMORY MAP . . ............................................10

1.5 EPROM PROGRAM MEMORY . . . . . . . . . . . . . . . . . . .. . . . . . .................... 13

2 CENTRAL PROCESSING UNIT . . ............................................... 14

2.1 INTRODUCTION . . . . . .. . . . . . ............................................14

2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 14

2.3 CPU REGISTERS . . . .................................................... 14

3 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . ................................17

3.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . ........................... 18

3.2 RESET MANAGER . . .................................................... 19

3.3 LOW CONSUMPTION OSCILLATOR . . . . . . . .. . . . . . . . . . . . . . . . . . . . . ........... 23

3.4 MAIN CLOCK CONTROLLER (MCC) . . . . ....................................24

4 INTERRUPTS . . .............................................................25

4.1 NON MASKABLE SOFTWARE INTERRUPT .................................. 25

4.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . .............................. 25

4.3 PERIPHERAL INTERRUPTS ............................................... 25

5 POWER SAVING MODES . . . . . . . . . . ...........................................28

5.1 INTRODUCTION . . . . . .. . . . . . ............................................28

5.2 HALT MODE . . . . . . . . . . . . . . . . . . . ........................................ 29

5.3 WAIT MODE . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . ........ 30

5.4 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . ................................. 30

6 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . ........................................31

6.1 INTRODUCTION . . . . . .. . . . . . ............................................31

6.2 FUNCTIONAL DESCRIPTION . . . . . ......................................... 31

6.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . ................................. 31

6.2.2 Output Modes . . . . . . ...............................................31

6.2.3 Alternate Functions . . ...............................................31

6.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.3.1 Register Description . . . . . ............................................36

7 MISCELLANEOUS REGISTER . . ...............................................38

7.0.1 I/O Port Interrupt Sensitivity Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.0.2 I/O Port Alternate Functions ...........................................38

7.0.3 Clock Prescaler Selection . . . . . . . . .................................... 38

7.0.4 Miscellaneous Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . ...........39

8 ON-CHIP PERIPHERALS . . . . . . . . . . . ........................................... 40

8.1 MOTOR CONTROLLER (MTC) . . . . ......................................... 40

8.1.1 Introduction . . . .................................................... 40

8.1.2 Main Features . . . . . . ...............................................40

8.1.3 Application Example . . . . . . . . . . . . . . . . . . .............................. 40

8.1.4 Functional description . . . . . . . . . . . . . . . . . . . . ........................... 44

8.1.5 Low PowerModes . . . ...............................................66

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3

8.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 66

8.1.7 Register Description . . . . . ............................................67

8.2 WATCHDOG TIMER (WDG) . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.2.1 Introduction . . . .................................................... 75

8.2.2 Main Features . . . . . . ...............................................75

8.2.3 Functional Description . . . . ...........................................76

8.2.4 Low PowerModes . . . ...............................................76

8.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 76

8.2.6 Register Description . . . . . ............................................76

8.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . ........................................78

8.3.1 Introduction . . . .................................................... 78

8.3.2 Main Features . . . . . . ...............................................78

8.3.3 Functional Description . . . . ...........................................78

8.3.4 Low PowerModes . . ............................................... 90

8.3.5 Interrupts . . . . . ....................................................90

8.3.6 Summary of Timer modes . . . . . . . . . . . . . . .............................. 90

8.3.7 Register Description . . . . . ............................................91

8.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . .. . . . . . . . . . . . . .. . . . . . ............96

8.4.1 Introduction . . . .................................................... 96

8.4.2 Main Features . . . . . . ...............................................96

8.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

8.4.4 Functional Description . . . . ...........................................98

8.4.5 Low PowerModes . . . ..............................................105

8.4.6 Interrupts . . . . . ...................................................105

8.4.7 Register Description . . . . . ...........................................106

8.5 8-BIT A/D CONVERTER (ADC) . . . . . . . .. . . . . . .. . . .......................... 109

8.5.1 Introduction . . . ................................................... 109

8.5.2 Main Features . . . . . . .............................................. 109

8.5.3 Functional Description . . . . ..........................................110

8.5.4 Low PowerModes . . . ..............................................110

8.5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................ 110

8.5.6 Register Description . . . . . ...........................................111

9 INSTRUCTION SET . . . . . . . . . . . . . . . . . . .......................................112

9.1 ST7 ADDRESSING MODES . . . . . . . . . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

9.1.1 Inherent . . . . . . .. . . . .............................................. 113

9.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 113

9.1.3 Direct . .......................................................... 113

9.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . .......................... 113

9.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

9.1.6 Indirect Indexed (Short, Long) . .......................................114

9.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

9.2 INSTRUCTION GROUPS . . .. . . . . . . . . . . . . ................................115

10 ELECTRICAL CHARACTERISTICS . . . . ........................................ 118

10.1ABSOLUTE MAXIMUM RATINGS . . . .......................................118

10.2RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . ..........119

10.3DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . .. . . . . . ........... 119

10.4GENERAL TIMING CHARACTERISTICS . . . . . . . . . . . .. . . . . . . . . . . . . . . . . ....... 119

Table of Contents

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10.5I/O PORT CHARACTERISTICS . ........................................... 120

10.6SUPPLY, RESET AND CLOCK CHARACTERISTICS . . . . . . . . . . . . . . .. . . . . . . . . . . 121

10.6.1Supply Manager ...................................................121

10.6.2RESET Sequence Manager . . . . . . . . . . ................................121

10.6.3Clock System . . . . . . . . . . . .......................................... 121

10.7MEMORY AND PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

11 GENERAL INFORMATION ................................................... 128

11.1PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . .......................... 128

11.2ORDERING INFORMATION . . . . . . . . . . . . . ................................. 129

12 SUMMARY OF CHANGES . .................................................. 131

1

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1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST72141K devices are members of the ST7
microcontroller family designed specifically for mo­tor control applications and including A/D conver­sion and SPI interface capabilities. They include
an on-chip Moter Controller peripheral for control
of electric brushless moters with or without sen­sors. An example application, for 6-step control of
a Permanent Magnet DC motor, is shown in Figure

1.
The ST72141K devices are based on a common

industry-standard 8-bit core, featuring an en­hanced instruction set.

Under software control, they can be placed in
WAIT, SLOW, or HALT mode, reducing power
consumption when the application is in idle or
standby state.

The enhanced instruction set and addressing
modes of the ST7 offer bothpower andflexibility to
software developers,enabling the design of highly
efficient and compact application code. In addition
to standard 8-bitdata management, all ST7micro­controllers feature true bit manipulation, 8x8 un­signed multiplication and indirect addressing
modes.

Figure 1. Example of a 6-step-controlled Motor

Figure 2. Device Block Diagram

0
1
2
3
4
5

A
B
C

Net Step

Σ1Σ2Σ3Σ4Σ5Σ6Σ1Σ2Σ

3

C

A

B

300V

4

1

I

4

I

1

I

3

I

6

I

2

I

5

300V
150V
0

300V
150V
0

300V
150V
0

ST7

MTC

MCO5 -0

MCIB

MCIA
MCIC

2

0

35

6

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSC1
OSC2

RESET

MOTOR CTRL

TIMER B

TIMER A

PORT B

WATCHDOG

MCO5:0

OSC

Internal
CLOCK

CONTROL

256b-RAM

PA7:0

V

SS

V

DD

POWER

SUPPLY

8K-EPROM

PORT A

8-BIT ADC

SPI

OC1A

MCIA:C
MCES

MCCFI

PB5:0

DIV

LVD

(6-BIT)

(8-BIT)

4

ST72141K

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1.2 PIN DESCRIPTION
Figure 3. 34-Pin SO Package Pinout

Figure 4. 32-Pin SDIP Package Pinout

18

19

20

21

22

23

31
30
29
28
27
26
25
24

1
2
3
4
5
6
7
8
9
10
11
12
13

14

MCO5
MCO4

EXTCLK_A/ (HS) PB0

EXTCLK_B/ (HS) PB1

SS/ (HS) PB2

SCK/PB3

MOSI/PB4

NC

MISO/PB5

MCES

MCO0

MCO1

MCO2

MCO3

MCCFI

V

DD

PA0/AIN0

PA1/AIN1/ICAP2_B

PA2/AIN2/ICAP1_B

PA3/AIN3/OCMP2_B

PA4/AIN4/OCMP1_B

PA5/AIN5/ICAP2_A

PA6/AIN6/ICAP1_A

PA7/AIN7/OCMP2_A

NC

OCMP1_A

V

PP

V

SS

EI1

EI0

15
16

17

RESET

OSC2

OSC1

34
33
32

MCIA

MCIB

MCIC

28
27
26
25
24
23
22
21
20
19
18
17

16

15

1
2
3
4
5
6
7
8
9
10
11
12
13
14

29

30

31

32

MCO5
MCO4

RESET

OSC2

OSC1

EXTCLK_A/ (HS) PB0

EXTCLK_B/ (HS) PB1

SS/ (HS) PB2

SCK/PB3

MCES

MCO0

MCO1

MCO2

MCO3

MOSI/PB4

MISO/PB5

MCIA

MCIB

PA0/AIN0

PA1/AIN1/ICAP2_B

PA2/AIN2/ICAP1_B

PA3/AIN3/OCMP2_B

PA4/AIN4/OCMP1_B

PA5/AIN5/ICAP2_A

PA6/AIN6/ICAP1_A

V

PP

V

SS

V

DD

MCCFI

MCIC

OCMP1_A
PA7/AIN7/OCMP2_A

EI1

EI0

5

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PIN DESCRIPTION (Cont’d)
Legend / Abbreviations:

Type: I = input, O = output, S = supply
Input level: A = Dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD,

CT= CMOS 0.3VDD/0.7VDDwith input trigger

Output level: HS = high sink (on N-buffer only),

R=70Ω/100Ω ratio of logical levels.

Analog level if used as PWM filtered with an external capacitor

Port configuration capabilities:

– Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
– Output: OD = open drain, T = true open drain, PP = push-pull

Note: the Reset configuration of each pin is shown in bold.
Table 1. Device Pin Description

Pin n°

Pin Name

Type

Level Port / Control

Main

Function

(after reset)

Alternate Function

SDIP32

SO34

Input

Output

Input Output

float

wpu

int

ana

OD

PP

1 1 MCO5 O C X Motor Control Output Channel 5
2 2 MCO4 O C X Motor Control Output Channel 4
3 3 MCO3 O C X Motor Control Output Channel 3
4 4 MCO2 O C X Motor Control Output Channel 2
5 5 MCO1 O C X Motor Control Output Channel 1
6 6 MCO0 O C X Motor Control Output Channel 0
7 7 MCES I C

T

X Motor Control Emergency Stop Input

8 8 PB5/MISO I/O C

T

X EI1 X X Port B5 SPI Master In / Slave Out Data

9 NC Not Connected

9 10 PB4/MOSI I/O C

T

X EI1 X X Port B4 SPI Master Out / Slave In Data

10 11 PB3/SCK I/O C

T

X EI1 X X Port B3 SPI Serial Clock

11 12 PB2/SS I/O C

T

HS X EI1 T Port B2 SPI Slave Select (active low)

12 13 PB1/EXTCLK_B I/O C

T

HS X EI1 T Port B1 Timer B Input Clock

13 14 PB0/EXTCLK_A I/O C

T

HS X EI1 T Port B0 Timer A Input Clock

14 15 OSC1

These pins connect a crystal or ceramic
resonator, or an external RC, or an external
source to the on-chip oscillator

15 16 OSC2
16 17 RESET I/O C X X Toppriority nonmaskable interrupt (active low)
17 18 PA0/AIN0 I/O C

T

X EI0 X X X Port A0 ADC Analog Input 0

18 19 PA1/ICAP2_B/AIN1 I/O C

T

X EI0 X X X Port A1

Timer B Input Capture 2 or
ADC Analog Input 1

19 20 PA2/ICAP1_B/AIN2 I/O C

T

X EI0 X X X Port A2

Timer B Input Capture 1 or
ADC Analog Input 2

6

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20 21 PA3/OCMP2_B/AIN3 I/O C

T

X EI0 X X X Port A3

Timer B Output Compare 2 or
ADC Analog Input 3

21 22 PA4/OCMP1_B/AIN4 I/O C

T

X EI0 X X X Port A4

Timer B Output Compare 1 or
ADC Analog Input 4

22 23 PA5/ICAP2_A/AIN5 I/O C

T

X EI0 X X X Port A5

Timer A Input Capture 2 or
ADC Analog Input 5

23 24 PA6/ICAP1_A/AIN6 I/O C

T

X EI0 X X X Port A6

Timer A Input Capture 1 or
ADC Analog Input 6

24 25 PA7/OCMP2_A/AIN7 I/O C

T

X EI0 X X X Port A7

Timer A Output Compare 2 or
ADC Analog Input 7

26 NC Not Connected

25 27 OCMP1_A O R Timer A Output Compare 1
26 28 V

PP

I

Must be tied low during normal operating
mode,EPROM Programming voltage pin.

27 29 V

SS

S Ground

28 30 V

DD

S Main power supply
29 31 MCCFI I A Motor Control Current Feedback Input
30 32 MCIC I A Motor Control Input C
31 33 MCIB I A Motor Control Input B
32 34 MCIA I A Motor Control Input A

Pin n°

Pin Name

Type

Level Port / Control

Main

Function

(after reset)

Alternate Function

SDIP32

SO34

Input

Output

Input Output

float

wpu

int

ana

OD

PP

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1.3 EXTERNAL CONNECTIONS

The following figure shows the recommended ex­ternal connections for the device.

The VPPpin is only used for programming OTP
and EPROM devices and must be tied to ground in
user mode.

The 10 nF and 0.1 µF decoupling capacitors on
the power supply lines are a suggested EMC per­formance/cost tradeoff.

The external reset network is intended to protect
the device against parasitic resets, especially in
noisy environments.

Unused I/Os should be tied high to avoid any un­necessary power consumption on floating lines.
An alternative solution is to program the unused
ports as inputs with pull-up.

Figure 5. Recommended External Connections

V

PP

V

DD

V

SS

OSC1

OSC2

RESET

V

DD

0.1µF

+

See
Clocks
Section

V

DD

0.1µF

0.1µF

EXTERNAL RESET CIRCUIT

Or configure unused I/O ports

Unused I/O

10µF

4.7K

10K

by software as input with pull-up

V

DD

Detector (LVD) isused

Optional if Low Voltage

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1.4 REGISTER & MEMORY MAP

As shown in Figure 6, the MCU is capable of ad­dressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128
bytes of register locations, 256 bytes of RAM and
8Kbytes of user program memory. The RAM

space includes up to 64 bytes for the stack from
0140h to 017Fh.

The highest address bytes contain the user reset
and interrupt vectors.

Figure 6. Memory Map

Table 2. Interrupt Vector Map

0000h

Program Memory

(8K Bytes)

Interrupt & Reset Vectors

HW Registers

DFFFh

0080h

007Fh

(see Table 3)

E000h

FFDFh
FFE0h

FFFFh

(see Table 2)

0180h

Reserved

017Fh

Short Addressing

RAM

16-bit Addressing

0100h

013Fh

0080h

00FFh

256 Bytes RAM

RAM

Stack or

16-bit Addressing

0140h

017Fh

RAM

(64 Bytes)

“Zero page”

(64 Bytes)

(128 Bytes)

Vector Address Description Remarks

FFE0-FFE1h
FFE2-FFE3h
FFE4-FFE5h
FFE6-FFE7h

FFE8-FFE9h
FFEA-FFEBh
FFEC-FFEDh
FFEE-FFEFh

FFF0-FFF1h
FFF2-FFF3h
FFF4-FFF5h
FFF6-FFF7h
FFF8-FFF9h

FFFA-FFFBh
FFFC-FFFDh

FFFE-FFFFh

Not used
Not used
Not used
Not used
Not used
TIMER B interrupt vector
TIMER A interrupt vector
SPI interrupt vector
Motor control interrupt vector (events: E, O)
Motor control interrupt vector (events: C, D)
Motor control interrupt vector (events: R, Z)
External interrupt vector EI1: port B7..0
External interrupt vector EI0: port A7..0
Not used
TRAP (software) interrupt vector
RESET vector

Internal Interrupt

External Interrupt
External Interrupt

CPU Interrupt

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Table 3. Hardware Register Map

Address Block

Register

Label

Register Name

Reset

Status

Remarks

0000h
0001h
0002h

Port A

PADR
PADDR
PAOR

Port A Data Register
Port A Data Direction Register
Port A Option Register

00h
00h
00h

R/W
R/W

R/W
0003h Reserved Area (1 Byte)
0004h

0005h
0006h

Port B

PBDR
PBDDR
PBOR

Port B Data Register
Port B Data Direction Register
Port B Option Register

00h
00h
00h

R/W

R/W

R/W.
0007h

to

001F

Reserved Area (24 Byte)

0020h MISCR Miscellaneous Register 00h R/W
0021h

0022h
0023h

SPI

SPIDR
SPICR
SPISR

SPI Data I/O Register
SPI Control Register
SPI Status Register

xxh
0xh
00h

R/W
R/W
Read Only

0024h
0025h

WATCHDOG

WDGCR
WDGSR

Watchdog Control Register
Watchdog Status Register

7Fh
x0h

R/W
Read Only

0026h

to

0030h

Reserved Area (11 Bytes)

0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah

003Bh
003Ch
003Dh

003Eh

003Fh

TIMER A

TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR

Timer A Control Register 2
Timer A Control Register 1
Timer A Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register

00h
00h

xxh
xxh

xxh
80h
00h
FFh

FCh
FFh
FCh

xxh

xxh
80h
00h

R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W

0040h Reserved Area (1 Byte)

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0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah

004Bh
004Ch
004Dh

004Eh

004Fh

TIMER B

TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR

Timer B Control Register 2
Timer B Control Register 1
Timer B Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register

00h
00h

xxh
xxh

xxh
80h
00h

FFh
FCh
FFh
FCh

xxh

xxh
80h
00h

R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W

0050h

to

005Fh

Reserved Area (16 Bytes)

0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah

006Bh
006Ch
006Dh

MOTOR
CONTROL

MTIM
MZPRV
MZREG
MCOMP
MDREG
MWGHT
MPRSR
MIMR
MISR
MCRA
MCRB
MPHST
MPAR
MPOL

Timer Counter Register
Zn-1 Capture Register
Zn Capture Register
C

n+1

Compare Register
D capture/Compare Register
Weight Register
Prescaler and Ratio Register
Interrupt Mask Register
Interrupt Status Register
Control Register A
Control Register B
Phase State Register
Output Parity Register
Output Polarity Register

00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

006Eh

to

006Fh

Reserved Area (2 bytes)

0070h
0071h

ADC

ADCDR
ADCCSR

Data Register
Control/Status Register

00h
00h

Read Only
R/W

0072h

to

007Fh

Reserved Area (14 Bytes)

Address Block

Register

Label

Register Name

Reset

Status

Remarks

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1.5 EPROM PROGRAM MEMORY

The programmemory of the OTP and EPROMde­vices can be programmed with EPROM program­ming tools available from STMicroelectronics.

EPROM Erasure

EPROM devices are erased by exposure to high
intensity UVlightadmitted through the transparent
window. This exposure discharges the floating
gate to its initial state through induced photo cur­rent.

It is recommended that the EPROM devices be
kept out of direct sunlight, since the UV content of
sunlight can be sufficient to cause functional fail­ure. Extended exposure to room level fluorescent
lighting may also cause erasure.

An opaque coating (paint, tape, label, etc...)
should be placed over the package window if the
product is to be operated under theselighting con­ditions. Covering the window also reduces IDDin
power-saving modes due to photo-diode leakage
currents.

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2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.

2.2 MAIN FEATURES

■ 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

2.3 CPU REGISTERS

The 6 CPU registers shown in Figure 7 are not
present in the memory mapping and are accessed
by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose reg­ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.

Index Registers (X and Y)

In indexed addressing modes, these 8-bitregisters
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in­struction (PRE) to indicate that the following in­struction refers to the Y register.)

The Y registeris not affectedby the interrupt auto­matic procedures (notpushed to and popped from
the stack).

Program Counter (PC)

The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) andPCH
(Program CounterHigh which is the MSB).

Figure 7. CPU Registers

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

70

1C11HINZ

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

70

70

70

0

7

15 8

PCH

PCL

15

87 0

RESET VALUE = STACKHIGHER ADDRESS

RESET VALUE =

1X11X1XX

RESET VALUE = XXh

RESET VALUE = XXh

RESET VALUE= XXh

X = Undefined Value

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CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)

Read/Write
Reset Value: 111x1xxx

The 8-bit Condition Code register contains the in­terrupt mask and four flags representative of the
result ofthe instruction just executed. This register
can also be handled by the PUSH and POP in­structions.

These bits can be individually tested and/or con­trolled by specific instructions.

Bit 4 = H

Half carry

.

This bit is set by hardware whena carryoccursbe­tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is resetby hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc­tion. The H bit is useful in BCD arithmetic subrou­tines.

Bit 3 = I

Interrupt mask

.

This bit is set by hardware when entering in inter­rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.

This bit is controlledby the RIM, SIM and IRET in­structions and is tested by the JRM and JRNM in­structions.

Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware when you en-

ter it and reset by the IRET instruction at the end of
the interrupt routine. If the I bit is cleared by soft­ware in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur­rent interrupt routine.

Bit 2 = N

Negative

.

This bit is set and cleared by hardware. It is repre­sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7

th

bit of the result.
0:Theresultof the last operation is positive or null.
1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit isaccessed bythe JRMI andJRPL instruc­tions.

Bit 1 = Z

Zero

.

This bit is set and cleared by hardware. Thisbit in­dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test

instructions.

Bit 0 = C

Carry/borrow.

This bit is set and cleared by hardware and soft­ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow hasoccurred.

This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.

70

111HINZC

ST72141K

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CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)

Read/Write
Reset Value: 01 7Fh

The Stack Pointer is a 16-bit register which is al­ways pointingto the next free location in the stack.
It isthen decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 8).

Since the stack is 128 bytes deep, the 9th most
significant bits are forced by hardware. Following
an MCU Reset, or after a Reset Stack Pointer in­struction (RSP), the Stack Pointer contains its re­set value (the SP6 to SP0 bits areset) which is the
stack higher address.

The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in­struction.

Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with­out indicating the stack overflow. The previously
stored information is then overwritten and there­fore lost. The stack also wrapsin case of anunder­flow.

The stack is used to save the return address dur­ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by meansof the PUSH and POP instruc­tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 8.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from thestack.

A subroutine call occupies twolocations and an in­terrupt five locations in the stack area.

Figure 8. Stack Manipulation Example

15 8

00000001

70

0 SP6 SP5 SP4 SP3 SP2 SP1 SP0

PCH

PCL

SP

PCH
PCL

SP

PCL

PCH

X

A

CC

PCH

PCL

SP

PCL

PCH

X

A

CC

PCH

PCL

SP

PCL

PCH

X

A

CC

PCH

PCL

SP

SP

Y

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 017Fh

@ 0100h

Stack Higher Address = 017Fh
Stack Lower Address =

0100h

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3 SUPPLY, RESET AND CLOCK MANAGEMENT

The ST72141K includes a range of utility features
for securing the application in critical situations(for
example in case of a power brown-out), and re­ducing the number of external components. An
overview is shown in Figure 9.

Main Features

■ Main supply low voltage detection (LVD)

■ RESET Manager

■ Low consumption resonator oscillator

■ Main clock controller (MCC)

Figure 9. Clock, RESET, Option and Supply Management Overview

f

OSC

MAIN CLOCK

CONTROLLER

(MCC)

LOW VOLTAGE

DETECTOR

(LVD)

f

CPU

FROM

WATCHDOG

PERIPHERAL

OSC2

OSC1

RESET

V

DD

V

SS

f

MOTOR_CONTROL

OSCILLATOR

RESET

f

SPI

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3.1 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management
features in the application, the Low Voltage Detec­tor function (LVD) generates a static reset when
the VDDsupply voltage is below a V

LVDf

reference
value. This means that it secures the power-up as
well as the power-down keeping the ST7 in reset.

The V

LVDf

reference value for a voltage drop is

lower than the V

LVDr

reference value for power-on
in order to avoid a parasitic reset when the MCU
starts running and sinks current on the supply
(hysteresis).

The LVD Reset circuitry generates a reset when
VDDis below:

–V

LVDr

when VDDis rising

–V

LVDf

when VDDis falling

The LVD function is illustrated in Figure 10.

Provided the minimum VDDvalue (guaranteed for
the oscillator frequency) is below V

LVDf

, the MCU

can only be in two modes:

– under full software control
– in static safe reset

In these conditions, secure operation is always en­sured for the application without the need for ex­ternal reset hardware.

During aLow Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.

Notes:
The LVDallows the device to be used without any

external RESET circuitry.

Figure 10. Low Voltage Detector vs Reset

V

DD

V

LVDr

RESET

V

LVDf

HYSTERISIS

V

LVDhyst

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3.2 RESET MANAGER

The RESET block includes three RESET sources
as shown in Figure 11:

■ ExternalRESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

The RESET service routine vector is fixed at ad­dresses FFFEh-FFFFh in theST7 memory map.

A 4096 CPUclock cycle delay allows the oscillator
to stabilise and ensures that recovery has taken
place from the Reset state.

The RESET vector fetch phase duration is 2 clock
cycles.

Figure 11. Reset Block Diagram

f

CPU

COUNTER

RESET

R

ON

V

DD

WATCHDOG RESET

LVD RESET

INTERNAL
RESET

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RESET MANAGER (Cont’d)
External RESET pin

The RESETpin is both an input andan open-drain
output with integrated RONweak pull-up resistor
(see Figure11). This pull-up has no fixedvalue but
varies in accordance with the input voltage. Itcan
be pulled low by external circuitry to reset the de­vice.

A RESET signal originating from an external
source must have a duration of at least t

PULSE

in
order to be recognized. Two RESET sequences
can be associated with this RESET source as
shown in Figure 12.

When the RESET is generated by a internal
source, during the two first phases of the RESET
sequence, the device RESET pin acts as an out­put that ispulled low.

Generic Power On RESET

The function of the POR circuit consists of waking
up the MCU by detecting (at around 2V) a dynamic
(rising edge) variation of the VDDSupply. At the
beginning of this sequence, the MCU is configured
in the RESET state. When the power supply volt­age rises toa sufficient level, the oscillator starts to
operate, whereupon an internal 4096 CPU cycles
delay is initiated, in order to allow the oscillator to
fully stabilize before executing the first instruction.
The initialization sequence is executed immediate­ly following the internal delay.

To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a suffi­cient level forthe chosen frequency (seeElectrical
Characteristics) before the reset signal is re­leased. In addition, supply rising must start from
0V.

As a consequence, the POR does not allow to su­pervise static, slowly rising, or falling, or noisy (os­cillating) VDDsupplies.

An external RC network connected to the RESET
pin, or the LVD reset can be used instead to get
the best performance.

Figure 12. External RESET Sequences

RESET

RUN

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

RUN

RESET PIN

EXTERNAL RESET SOURCE

t

PULSE

V

DD

V

LVDf

V

DD nominal

WATCHDOG RESET

DELAY

ST72141K

21/132

RESET MANAGER (Cont’d)
Internal Low VoltageDetection RESET (option)

Two different RESET sequences caused by the in­ternal LVD circuitry can be distinguished:

- LVD Power-On RESET

- Voltage Drop RESET

In the second sequence, a “delay” phase is used
to keep the device in RESET state until VDDrises
up to V

LVDr

(see Figure 13).

Figure 13. LVD RESET Sequences

RESET

RUN

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

POWER-

RESET PIN

EXTERNAL RESET SOURCE

WATCHDOG RESET

RESET

RUN

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

RUN

RESET PIN

EXTERNAL RESET SOURCE

V

DD

V

DDnominal

WATCHDOG RESET

DELAY

V

LVDr

V

LVDf

V

DD

V

DDnominal

V

LVDr

LVD POWER-ON RESET

VOLTAGE DROP RESET

OFF

ST72141K

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RESET MANAGER (Cont’d)
Internal Watchdog RESET

The RESET sequence generated by a internal
Watchdog counter overflow has the shortest reset
phase (see Figure 14).

Figure 14. Watchdog RESET Sequence

RESET

RUN

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

RUN

RESET PIN

EXTERNAL RESET SOURCE

V

DD

V

LVDf

V

DDnominal

WATCHDOG RESET

WATCHDOG UNDERFLOW

t

WDGRST

ST72141K

23/132

3.3 LOW CONSUMPTION OSCILLATOR

The main clock of the ST7 can be generated by
two differentsources:

■ an external source

■ a crystal or ceramic resonator oscillators

External Clock Source

In this mode, asquare clock signal with ~50% duty
cycle has to drive the OSC2 pin while the OSC1
pin is tied to VSS(see Figure 15).

Figure 15. External Clock

Crystal/Ceramic Oscillators

This oscillator (based on constant current source)
is optimized in terms of consumption and has the
advantage of producing a very accurate rate on
the main clock of the ST7.
When using this oscillator, the resonator and the
load capacitances have to be connected as shown
in Figure 16 and have to be mounted as close as
possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time.

This oscillator is not stopped during the RESET
phase to avoid losing time in the oscillator start-up
phase.

Figure 16. Crystal/Ceramic Resonator

OSC1 OSC2

EXTERNAL

ST7

SOURCE

OSC1 OSC2

LOAD

CAPACITANCES

ST7

C

L1

C

L0

ST72141K

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3.4 MAIN CLOCK CONTROLLER (MCC)

The MCC block supplies the clock for the ST7
CPU and its internal peripherals. It allows the
SLOW power saving mode and the Motor Contral
and SPI peripheral clocks to be managed inde­pendently. The MCC functionality is controlled by
two bits of the MISCR register: SMS and XT16.

The XT16 bitacts on the clockof the motor control
and SPI peripherals while the SMS bit acts on the
CPU and the other peripherals.

Figure 17. Main Clock Controller (MCC) Block Diagram

DIV 2

SMS--

CPU CLOCK

MISCR

TO CPU AND

PERIPHERALS

f

OSC

f

CPU

OSC2

OSC1

----XT16

OSCILLATOR

MCC

DIV 16

4MHz

MOTOR CONTROL

PERIPHERAL

DIV 2

4MHz

SPI

PERIPHERAL

DIV 2

ST72141K

25/132

4 INTERRUPTS

The ST7 core may be interruptedby one oftwo dif­ferent methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a non­maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 18.
The maskableinterrupts must be enabled clearing
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec­tion).

When an interrupt has to be serviced:
– Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– The I bit of the CC register is set to prevent addi-

tional interrupts.

– ThePC isthenloaded with the interrupt vectorof

the interruptto service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Tablefor vector address­es).

The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from thestack.

Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.

Priority management

By default, a servicing interrupt cannot be inter­rupted because the I bit is set by hardware enter­ing in interrupt routine.

In the case when severalinterrupts are simultane­ously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Map­ping Table).

Interrupts and Low power mode

All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifi­cally mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT“ column in the Interrupt Mapping Ta­ble).

4.1 NON MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruc­tion is executed regardless of the stateof theI bit.

It will be serviced according to the flowchart on
Figure 18.

4.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the I bit is cleared. Theseinterrupts
allow the processor to leave the Halt low power
mode.

The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).

An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt serviceroutine.

If several input pins, connected to the same inter­rupt vector, are configured as interrupts, their sig­nals are logically ANDed beforeentering the edge/
level detection block.

Caution:The type of sensitivitydefinedin the Mis­cellaneous or Interrupt register (if available) ap­plies to the ei source. In case of an ANDedsource
(as described on the I/O ports section), a low level
on an I/O pin configured as input with interrupt,
masks the interrupt requesteven in case of rising­edge sensitivity.

4.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:

– The I bit of the CC register is cleared.
– Thecorresponding enable bit is setin thecontrol

register.

If any of these two conditions is false, the interrupt
is latched and thus remains pending.

Clearing an interrupt request is done by:
– Writing “0” to the corresponding bit in the status

register or

– Access tothe status registerwhile the flag isset

followed by a read or write of an associated reg­ister.

Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en­abled) will therefore be lost ifthe clear sequence is
executed.

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INTERRUPTS (Cont’d)
Figure 18. Interrupt Processing Flowchart

I BIT SET?

Y

N

IRET?

Y

N

FROM RESET

LOAD PC FROM INTERRUPT VECTOR

STACK PC, X, A, CC

SET I BIT

FETCH NEXT INSTRUCTION

EXECUTEINSTRUCTION

THIS CLEARS I BIT BY DEFAULT

RESTORE PC,X, A,CC FROM STACK

INTERRUPT

Y

N

PENDING?

ST72141K

27/132

INTERRUPTS (Cont’d)
Table 4. Interrupt Mapping

N°

Source

Block

Description

Register

Label

Priority

Order

Exit

from

HALT

Address

Vector

RESET Reset

N/A

Highest

Priority

Lowest
Priority

yes FFFEh-FFFFh

TRAP Software Interrupt no FFFCh-FFFDh
0 Not used FFFAh-FFFBh
1 EI0 External Interrupt Port A7..0 (C5..0*)

N/A

yes FFFAh-FFFBh
2 EI1 External Interrupt Port B7..0 (C5..0*) yes FFF8h-FFF9h
3

MTC

Motor Control Interrupt (events: R, Z)

MISR

no FFF4h-FFF5h
4 Motor Control Interrupt (events: C, D) no FFF2h-FFF3h
5 Motor Control Interrupt (events: E, O) no FFF0h-FFF1h
6 SPI SPI Peripheral Interrupts SPISR no FFEEh-FFEFh
7 TIMER A TIMER A Peripheral Interrupts TASR no FFECh-FFEDh
8 TIMER B TIMER B Peripheral Interrupts TBSR no FFEAh-FFEBh
9 Not used FFE8h-FFE9h

10 Not used FFE6h-FFE7h
11 Not used FFE4h-FFE5h
12 Not Used FFE2h-FFE3h
13 Not Used FFE0h-FFE1h

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5 POWER SAVING MODES

5.1 Introduction

To give a large measure of flexibilitytotheapplica­tion in terms of power consumption, three main
power saving modes are implemented in the ST7
(see Figure 19).

After a RESET the normal operating mode is se­lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (f

CPU

).

From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the the oscil­lator status.

Figure 19. Power saving mode consumption / transitions

POWERCONSUMPTION

WAIT SLOW RUNHALT

High

Low

SLOW WAIT

ST72141K

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POWER SAVING MODES (Cont’d)

5.2 HALT Mode

The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
ST7 HALT instruction (see Figure 21).

The MCU can exit HALT mode on reception of ei­ther an external interrupt or a reset (see Table 2).
When exiting HALT mode by means of a RESET
or an interrupt, the oscillator is immediately turned
on and the 4096 CPU cycle delay is used to stabi­lize theoscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up(see Fig­ure 20).

When entering HALT mode, the I bit in the CC
Register is forced to 0 to enable interrupts.

In the HALT mode the main oscillator is turned off
causing all internal processing to be stopped, in­cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla­tor).

Figure 20. HALT Mode timing overview

Figure 21. HALT modes flow-chart

HALT

RUN

RUN

4096 CPU CYCLE

DELAY

RESET

OR

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

HALT INSTRUCTION

Notes:

CPU

OSCILLATOR
PERIPHERALS

I BIT

OFF
OFF

0

OFF

RESET

EXTERNAL*

Y

N

N

Y

CPU

OSCILLATOR
PERIPHERALS

ON
OFF
OFF

INTERRUPT

HALT

FETCH RESET VECTOR

OR SERVICE INTERRUPT **

4096 clock cycles delay

CPU

OSCILLATOR
PERIPHERALS

ON
ON
ON

External interrupt or internal interrupts with Exit from Halt Mode capability

*

**

Before servicing an interrupt, the CC register is pushed on the stack.

WATCHDOG

YN

ENABLE

ST72141K

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POWER SAVING MODES (Cont’d)

5.3 WAIT Mode

WAIT mode places the MCU in a low power con­sumption mode by stopping the CPU.
This power saving mode is selectedby calling the
“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the I bit of the CC register are forced to 0, to ena­ble all interrupts. All other registers and memory
remain unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occurs, whereup­on the Program Counter branches to the starting
address of the interrupt or Reset serviceroutine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.

Refer to Figure22.

5.4 SLOW Mode

This mode has two targets:
– To reduce powerconsumption bydecreasingthe

internal clock in the device,

– To adapt the internal clock frequency (f

CPU

)to

the available supply voltage.

SLOW mode is controlled by the SMS bit in the
MISCR register. This bit enables or disables Slow
mode selecting the internal slow frequency (f

CPU

).

In this mode, the oscillator frequency can bedivid­ed by 32 instead of 2 in normal operating mode.
The CPU and peripheralsare clocked atthis lower
frequency except the Motor Control and the SPI
peripherals which have their own clock selection
bit (XT16) in the MISCR register.

Figure 22. WAIT mode flow-chart

WFI INSTRUCTION

RESET

INTERRUPT

Y

N

N

Y

CPU

OSCILLATOR
PERIPHERALS

I BIT

ON
ON

0

OFF

if exit caused by a RESET, a 4096 CPU

clock cycle delay is inserted.

CPU

OSCILLATOR
PERIPHERALS

ON

OFF*

OFF

Note:

*

The peripheral clock is stopped only when exit caused by RESET and not by an interrupt.

**

Before servicing an interrupt, the CC register is pushed on the stack.

FETCH RESET VECTOR

OR SERVICE INTERRUPT**

CPU

OSCILLATOR
PERIPHERALS

ON
ON
ON