SGS Thomson Microelectronics ST70135A Datasheet
■ DMT MODEM FOR CPE ADSL,
COMPATIBLE WITH THE FOLLOWING
STANDARDS:
- ANSI T1.413 ISSUE 2
- ITU-T G.992.1 (G.DMT)
- ITU-T G.992.2 (G.LITE)
ST70135A
ASCOTTMDMT TRANSCEIVER
■ SUPPORTS EITHER ATM (UTOPIA LEVEL
1 & 2) OR BITSTREAM INTERFACE
■ 16 BIT MULTIPLEXED MICROPROCESSOR
INTERFACE (LITTLE AND BIG ENDIAN
COMPATIBILITY)
■ ANALOG FRONT END MANAGEMENT
■ DUAL LATENCY PATHS: FAST AND
INTERLEAVED
■ ATM’S PHY LAYER: CELL PROCESSING
(CELL DELINEATION, CELL INSERTION,
HEC)
■ ADSL’S OVERHEAD MANAGEMENT
■ REED SOLOMON ENCODE/DECODE
■ TRELLIS ENCODE/DECODE (VITERBI)
■ DMT MAPPING/ DEMAPPING OVER 256
CARRIERS
■ FINE (2PPM) TIMING RECOVER USING
ROTOR AND ADAPTATIVE FREQUENCY
DOMAIN EQUALIZING
■ TIME DOMAIN EQUALIZATION
■ FRONT END DIGITAL FILTERS
■ 0.35µm HCMOS6 TECHNOLOGY
■ 144 PIN PQFP PACKAGE
■ POWER CONSUMPTION 1 WATTAT 3.3V
PQFP144
ORDERING NUMBER:
ST70135A
APPLICATIONS
Routers at SOHO, stand-alone modems, PC
modems
GENERAL DESCRIPTION
The ST70135A is the DMT modem and ATM
framer of the STMicroelectronics ASCOT
chipset. When coupled with ST70134 analog
front-end and an external controller running
dedicated firmware, the product fulfills ANSI
T1.413 ”Issue 2” DMT ADSL specification.
The chip supports UTOPIA level 1 and UTOPIA
level 2 interface and a non ATM synchronous
bit-stream interface.
The ST70135A can be split up into two different
sections. The physical one performs the
DMT modulation, demodulation, Reed-Solomon
encoding, bit interleaving and 4D trellis coding.
The ATM section embodies framing functions for
the generic and ATM Transmission Convergence
(TC) layers.
The generic TC consists of data scrambling and
Reed Solomon error corrections, with and without
interleaving. The ST70135A is controlled and
programmed by an external controller (ADSL
Transceiver Controller, ATC) that sets the
programmable coefficients.
The firmware controls the initialization phase and
carries out the consequent adaptation operations.
1/29April 2000
ST70135A
Figure 1 : Block Diagram
TEST SIGNALS CLOCK
TES TMODUL E DATASYMBOLT IMINGUNIT VCXO
AFE
INTERFACE
AFE
CONTROL
DSP
FRONT-END
AFE CONTROL
INTERFACE
FFT/IFFT
ROTO R
CONTROLLE R ATM
INTERFACE
CONTROLLE R
BUS
TRANSIENT ENERGY CAPABILITIES
ESD
ESD (Electronic Discharged) tests have been
performed for the Human Body Model (HBM) and
for the Charged Device Model (CDM). The pins of
TRELLIS
CODING
MAPPER/
DEMAPP ER
GENERAL
PURPOSEI/Os
the device are to be able to withstand minimum
2000V for the HBM and minimum250V for CDM.
Latch-up
The maximum sink or source current from any pin
is limited to 200mA to prevent latch-up.
GENERIC
TC
REED/
SOLOMON
SPECIFIC TC
INTERFACE
MODULE
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Minimum Typical Maximum Unit
V
P
T
DD
tot
amb
Supply Voltage 3.0 3.3 3.6 V
TotalPower Dissipation 900 1400 mW
Ambient Temperature 1m/s airflow 0 70 °C
STM
UTOPIA
2/29
Figure 2 : Pin Connection
AFTXD_1
VSS
AFTXD_0
VSS
AD_0
AD_1
AD_2
VDD
AD_3
AD_4
VSS
AD_5
AD_6
VDD
AD_7
AD_8
AD_9
VSS
AD_10
AD_11
VDD
AD_12
VSS
PCLK
VDD
AD_13
AD_14
AD_15
VSS
BE1
ALE
VDD
CSB
WR_RDB
RDYB
OBC_TYPE
INTB
RESETB
VSS
VDD
144 143 142 141
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37 38 39 40
AFTXD_3
AFTXD_2
IDDq
VDD
AFTXED_3
AFTXED_2
ST70135A
AFRXD_1
AFRXD_0
VDD
PDOWN
GP_OUT
TESTSE
TRSTB
VSS
TCK
VDD
TMS
TDO
TDI
SLT_FRAME_S
SLT_REQ_S
VSS
AFTXED_1
AFTXED_0
VDD
CTRLDATA
MCLK
CLWD
VSS
AFRXD_3
AFRXD_2
134 133 132 131 130 129 128 127 126 125140 139 138 137 136 135
118 117 116 115 114 113 112 111 110 109124 123 122 121 120 119
ST70135A
47 48 49 50 51 52 53 54 55 5641 42 43 44 45 46
63 64 65 66 67 68 69 70 71 7257 58 59 60 61 62
VSS
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD
SLT_REQ_F
SLT_DAT_S0
SLT_DAT_S1
SLT_DAT_F0
SLT_DAT_F1
VSS
SLT_FRAME_F
SLAT_CLOCK
SLR_VAL_F
SLR_DAT_F0
SLR_DAT_F1
SLR_VAL_S
VDD
SLR_DAT_S0
SLR_DAT_S1
SLR_FRAME_S
VSS
SLR_FRAME_F
U_TX_ADDR_0
U_TX_ADDR_1
U_TX_ADDR_2
VDD
U_TX_ADDR_3
U_TX_ADDR_4
U_TX_DATA_0
U_TX_DATA_1
VDD
U_TX_DATA_2
U_TX_DATA_3
U_TX_DATA_4
U_TX_DATA_5
VDD
U_TX_DATA_6
U_TX_DATA_7
VSS
VDD
VSS
U_RXDATA_0
U_RXDATA_1
VDD
U_RXDATA_2
U_RXDATA_3
VSS
U_RXDATA_4
U_RXDATA_5
VDD
U_RXDATA_6
U_RXDATA_7
U_RX_ADDR_0
U_RX_ADDR_1
U_RX_ADDR_2
VSS
U_RX_ADDR_3
U_RX_ADDR_4
GP_IN0
VDD
GP_IN1
VSS
U_RX_REFB
U_TX_REFB
VDD
U_RXCLK
U_RXSOC
U_RXCLAV
U_RXENBB
VSS
U_TXCLK
U_TXSOC
U_TXENBB
U_TX_CLAV
VDD
3/29
ST70135A
PIN FUNCTIONS
Pin Name Type Supply Driver BS Function
1 VSS 0V Ground
2 AD_0 B VDD BD8SCR B Data 0
3 AD_1 B VDD BD8SCR B Data 1
4 AD_2 B VDD BD8SCR B Address / Data 2
5 VDD (VSS + 3.3V) Power Supply
6 AD_3 B VDD BD8SCR B Address / Data 3
7 AD_4 B VDD BD8SCR B Address / Data 4
8 VSS 0V Ground
9 AD_5 B VDD BD8SCR B Address / Data 5
10 AD_6 B VDD BD8SCR B Address / Data 6
11 VDD (VSS + 3.3V) Power Supply
12 AD_7 B VDD BD8SCR B Address / Data 7
13 AD_8 B VDD BD8SCR B Address / Data 8
14 AD_9 B VDD BD8SCR B Address / Data 9
15 VSS 0V Ground
16 AD_10 B VDD BD8SCR B Address / Data 10
17 AD_11 B VDD BD8SCR B Address / Data 11
18 VDD (VSS + 3.3V) Power Supply
19 AD_12 B VDD BD8SCR B Address / Data 12
20 VSS 0V Ground
21 PCLK I VDD IBUF I Processor clock
22 VDD (VSS + 3.3V) Power Supply
23 AD_13 B VDD BD8SCR B Address / Data 13
24 AD_14 B VDD BD8SCR B Address / Data 14
25 AD_15 B VDD BD8SCR B Address / Data 15
26 VSS 0V Ground
27 BE1 I VDD IBUF I Address 1
28 ALE I VDD IBUF C Address Latch
29 VDD (VSS + 3.3V) Power Supply
30 CSB I VDD IBUF I Chip Select
31 WR_RDB I VDD IBUF I Specifies the direction of the access cycle
32 RDYB OZ VDD BT4CR O Controls the ATC bus cycle termination
33 OBC_TYPE I-PD VDD IBUF I ATC Mode Selection (0 = i960; 1 = generic)
34 INTB O VDD IBUF O Requests ATC interrupt service
35 RESETB I VDD IBUF I Hard reset
36 VSS 0V Ground
4/29
PIN FUNCTIONS (continued)
Pin Name Type Supply Driver BS Function
37 VDD (VSS + 3.3V) Power Supply
38 U_RxData_0 OZ VDD BD8SRC B Utopia RX Data 0
39 U_RxData_1 OZ VDD BD8SRC B Utopia RX Data 1
40 VSS 0V Ground
41 U_RxData_2 OZ VDD BD8SRC B Utopia RX Data 2
42 U_RxData_3 OZ VDD BD8SRC B Utopia RX Data 3
43 VDD (VSS + 3.3V) Power Supply
44 U_RxData_4 OZ VDD BD8SRC B Utopia RX Data 4
45 U_RxData_5 OZ VDD BD8SRC B Utopia RX Data 5
46 VSS 0V Ground
47 U_RxData_6 OZ VDD BD8SRC B Utopia RX Data 6
48 U_RxData_7 OZ VDD BD8SRC B Utopia RX Data 7
49 VDD (VSS + 3.3V) Power Supply
50 U_RxADDR_0 I VDD IBUF I Utopia RX Address 0
51 U_RxADDR_1 I VDD IBUF I Utopia RX Address 1
52 U_RxADDR_2 I VDD IBUF I Utopia RX Address 2
53 U_RxADDR_3 I VDD IBUF I Utopia RX Address 3
54 VSS 0V Ground
55 U_RxADDR_4 I VDD IBUF I Utopia RX Address 4
56 GP_IN_0 I-PD VDD IBUFDQ I General purpose input 0
57 VDD (VSS + 3.3V) Power Supply
58 GP_IN_1 I-PD VDD IBUFDQ I General purpose input 1
59 VSS 0V Ground
60 U_RxRefB O VDD IBUF O 8kHz clock to ATM device
61 U_TxRefB I VDD BT4CR I 8kHz clock from ATM device
62 VDD (VSS + 3.3V) Power Supply
63 U_Rx_CLK I VDD IBUF Utopia RX Clock
64 U_Rx_SOC OZ VDD BD8SCR Utopia RX Start of Cell
65 U_RxCLAV OZ VDD BD8SCR Utopia RX Cell Available
66 U_RxENBB I VDD IBUF Utopia RX Enable
67 VSS 0V Ground
68 U_Tx_CLK I VDD IBUF Utopia TXClock
69 U_Tx_SOC I VDD IBUF Utopia TX Start of Cell
70 U_TxCLAV OZ VDD BD8SCR Utopia TX Cell Available
71 U_TxENBB I VDD IBUF Utopia TX Enable
72 VDD (VSS + 3.3V) Power Supply
ST70135A
5/29
ST70135A
PIN FUNCTIONS (continued)
Pin Name Type Supply Driver BS Function
73 VSS 0V Ground
74 U_TxData_7 I VDD IBUF I Utopia TX Data 7
75 U_TxData_6 I VDD IBUF I Utopia TX Data 6
76 VDD (VSS + 3.3V) Power Supply
77 U_TxData_5 I VDD IBUF I Utopia TX Data 5
78 U_TxData_4 I VDD IBUF I Utopia TX Data 4
79 U_TxData_3 I VDD IBUF I Utopia TX Data 3
80 U_TxData_2 I VDD IBUF I Utopia TX Data 2
81 VDD (VSS + 3.3V) Power Supply
82 U_TxData_1 I VDD IBUF I Utopia TX Data 1
83 U_TxData_0 I VDD IBUF I Utopia TX Data 0
84 U_TxADDR_4 I VDD IBUF I Utopia TX Address 4
85 U_TxADDR_3 I VDD IBUF I Utopia TX Address 3
86 VDD (VSS + 3.3V) Power Supply
87 U_TxADDR_2 I VDD IBUF I Utopia TX Address 2
88 U_TxADDR_1 I VDD IBUF I Utopia TX Address 1
89 U_TxADDR_0 I VDD IBUF I Utopia TX Address 0
90 SLR_ FRAME_F O VDD BT4CR Frame Identifier Fast
91 VSS 0V Ground
92 SLR_FRAME_S O VDD BT4CR Receive Frame Identifier Interleaved
93 SLR_DATA_S_1 O VDD BT4CR Receive Data Interleave 1
94 SLR_DATA_S_0 O VDD BT4CR Receive Data Interleave 0
95 VDD (VSS + 3.3V) Power Supply
96 SLR_VAL_S O VDD BT4CR Receive Data Valid Indicator Interleaved
97 SLR_DATA_F_1 O VDD BT4CR Receive Data Fast 1
98 SLR_DATA_F_0 O VDD BT4CR Receive Data Fast 0
99 SLR_VAL_F O VDD BT4CR Receive Data Valid Indicator Fast
100 SLAP_CLOCK O VDD BT4CR Clock for SLAP I/F
101 SLT_FRAME_F O VDD BT4CR Transmit Start of frame Indicator Fast
102 VSS 0V Ground
103 SLT_DATA_F_1 I VDD IBUFDQ Transmit Data Fast 1
104 SLT_DATA_F_0 I VDD IBUFDQ Transmit Data Fast 0
105 SLT_DATA_S_1 I VDD IBUFDQ Transmit Data Interleave 1
106 SLT_DATA_S_0 I VDD IBUFDQ Transmit Data Interleave 0
107 SLT_REQ_F O VDD BT4CR Transmit Byte Request Fast
108 VDD (VSS + 3.3V) Power Supply
6/29
ST70135A
PIN FUNCTIONS (continued)
Pin Name Type Supply Driver BS Function
109 VSS 0V Ground
110 SLT_REQ_S O VDD BT4CR Transmit Byte Request Interleaved
111 STL_FRAME_S O VDD BT4CR Transmit Start of frame Indication Interleaved
112 TDI I-PU VDD IBUFUQ JTAG I/P
113 TDO OZ VDD BT4CR JTAG O/P
114 TMS I-PU VDD IBUFUQ JTAG Made Select
115 VDD (VSS + 3.3V) Power Supply
116 TCK I-PD VDD IBUFDQ JTAG Clock
117 VSS 0V Ground
118 TRSTB I-PD VDD IBUFDQ JTAG Reset
119 TESTSE I VDD IBUF none Enables scan test mode
120 GP_OUT O VDD BD8SCR O General purpose output
121 PDOWN O VDD BT4CR O Power down analog front end (Reset)
122 VDD (VSS + 3.3V) Power Supply
123 AFRXD_0 I VDD IBUF I Receive data nibble
124 AFRXD_1 I VDD IBUF I Receive data nibble
125 AFRXD_2 I VDD IBUF I Receive data nibble
126 AFRXD_3 I VDD IBUF I Receive data nibble
127 VSS 0V Ground
128 CLWD I VDD IBUF I Start of word indication
129 MCLK I VDD IBUF C Master clock
130 CTRLDATA O VDD BT4CR O Serial data Transmit channel
131 VDD (VSS + 3.3V) Power Supply
132 AFTXED_0 O VDD BT4CR O Transmit echo nibble
133 AFTXED_1 O VDD BT4CR O Transmit echo nibble
134 VSS 0V Ground
135 AFTXED_2 O VDD BT4CR O Transmit echo nibble
136 AFTXED_3 O VDD BT4CR O Transmit echo nibble
137 VDD (VSS + 3.3V) Power Supply
138 IDDq I VDD IBUF none Testpin, active high
139 AFTXD_0 O VDD BT4CR O Transmit data nibble
140 AFTXD_1 O VDD BT4CR O Transmit data nibble
141 VSS 0V Ground
142 AFTXD_2 O VDD BT4CR O Transmit data nibble
143 AFTXD_3 O VDD BT4CR O Transmit data nibble
144 VDD (VSS + 3.3V) Power Supply
7/29
ST70135A
I/O DRIVER FUNCTION
Driver Function
BD4CR CMOS bidirectional, 4mA, slew rate control
BD8SCR CMOS bidirectional, 8mA, slew rate control, Schmitt trigger
IBUF CMOS input
IBUFDQ CMOS input, pull down, IDDq control
IBUFUQ CMOS input, pull up, IDDq control
PIN SUMMARY
Mnemonic Type BS Type Signals Function
Power Supply
VDD (VSS + 3.3V) Power Supply
VSS 0V Ground
ATC INTERFACE
ALE I C 1 Used to latch the address of the internal register to be
accessed
PCLK I I 1 Processor clock
CSB I I 1 Chip selected to respond to bus cycle
BE1 I I 1 Address 1 (not multiplexed)
WR_RDB I I 1 Specifies the direction of the access cycle
RDYB OZ O 1 Controls the ATC bus cycle termination
INTB O O 1 Requests ATC interrupt service
AD IO B 16 Multiplexed Address/Data bus
OBC_TYPE I-PD I 1 Select between i960 (0) or generic (1) controller interface
TEST ACCESS PART INTERFACE
TDI I-PU 1 Refer to section
TDO OZ 1
TCK I-PD 1
TMS I-PU 1
TRSTB I-PD 1
ANALOG FRONT END INTERFACE
AFRXD I I 4 Receive data nibble
AFTXD O O 4 Transmit data nibble
AFTXED O O 4 Transmit echo nibble
CLWD I I 1 Start of word indication
PDOWN O O 1 Power down analog front end
CTRLDATA O O 1 Serial data transmit channel
MCLK I C 1 Master cloc
8/29
Mnemonic Type BS Type Signals Function
ATMUTOPIA INTERFACE
U_RxData OZ B 8 Receive interface Data
U_TxData I I 8 Transmit interface Data
U_RxADDR I I 5 Receive interface Address
U_TxADDR I I 5 Transmit interface Address
U_RxCLAV OZ O 1 Receive interface Cell Available
U_TxCLAV OZ O 1 Transmit interface Cell Available
U_RxENBB I-TTL I 1 Receive interface Enable
U_TxENBB I-TTL I 1 Transmit interface Enable
U_RxSOC OZ O 1 Receive interface Start of Cell
U_TxSOC I-TTL I 1 Transmit interface Start of Cell
U_RxCLK I-TTL C 1 Receive interface Utopia Clock
U_TxCLK I-TTL C 1 Transmit interface Utopia Clock
U_RxRefB O O 1 8kHz reference clock to ATM device
U_TxRefB I-TTL I 1 8kHz reference clock from ATM device
ATMSLAP INTERFACE
SLR_VAL_S O 1
SLR_VAL_F O 1
SLR_DATA_S O 2
SLR_DATA_F O 2
SLT_REQ_S O 1
SLT_REQ_F O 1
SLT_DATA_S I 2
SLT_DATA_F I 2
SLAP_CLOCK O 1
SLR_FRAME_I O 1
SLT_FRAME_I O 1
SLR_FRAME_F O 1
SLT_FRAME_F O 1
MISCELLANEOUS
GP_IN I-PD I 2 General purpose input
GP_OUT O O 1 General purpose output
RESETB I I I Hard reset
TESTSE I none none Enable scan test mode
IDDq I none none Testpin, active high
ST70135A
9/29
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