SGS Thomson Microelectronics ST24LC21 Datasheet
1Kb (x8) DUAL MODE SERIAL EEPROM
1 MILLION ERASE /WRI TE CY CLES
40 YEARS DATA RETENTION
2.5V to 5.5V SINGLE SUPPLY VOLT AGE
400k Hz COMPATIBILIT Y OV ER th e FULL
RANGE o f SUPPLY VOLTAGE
TWO WIRE SERI AL INTERFACE I2C BUS
COMPA TIBLE
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQ UE NTIA L READ
MODES
SELF TIME D PRO G RA MM ING CY C LE
AUTOMATIC ADDRESS INCRE MENTING
ENHANCED ESD /LATCH UP
PERFORMA NCES
ST24LC21 is replaced by the ST24LC21B
for VESA Plug& Play
8
1
PSDIP8 (B)
0.25mm Frame
Figure 1. Logic Diag ra m
ST24LC21
NOT FOR NEW DESIGN
8
1
SO8 (M)
DESCRIP TION
The ST24LC21 is a 1K bit electrically erasable
programmable memory (EEPROM), organized by
8 bits.This device can operate in two modes: T ransmit Only mode and I
2
C bidirectional mode. When
powered, the device is i n Transmit Only mode with
EEPROM data clock ed out from the ris ing edge of
the signal applied on VCLK.
The device will switch to the I2C bidirectional m ode
upon the falling edge of the signal applied on SCL
pin. The ST24LC21 cannot switch from the I
2
bidirectional mode to the Tr ansmit Only m ode (except when the power supply is removed). The
device operates with a power supply value as low
as 2.5V . Bot h Plastic Dual-in-Line and Plastic Sm all
Outline packages are available.
T able 1. Signal Names
SDA Serial Data Address Input/Output
2
SCL Serial Clock (I
V
CC
V
SS
Supply Voltage
Ground
C mode)
V
CC
C
SCL
VCLK
ST24LC21
V
SS
SDA
AI01489
VCLK Clock Transmit only mode
June 1997 1/18
This is information on a product still in production but not recommended for new designs.
ST24LC21
Figure 2A. DIP Pin Connect io ns
ST24LC21
1
NC V
2
3
NC
4
SS
8
7
6
5
AI01499
VCLKNC
SCL
SDAV
CC
Figure 2B. SO Pin Connecti ons
ST24LC21
NC V
1
2
NC
SS
3
4
8
7
6
5
AI01500
CC
VCLKNC
SCL
SDAV
Warning: NC = Not Connected Warning: NC = Not Connected
T ab le 2. Absolut e Maximu m Ra t ings
(1)
Symbol Parameter Value Unit
T
T
T
STG
LEAD
Ambient Operating Temperature grade 1 0 to 70 °C
A
Storage Temperature –65 to 150 °C
Lead Temperature, Soldering (SO8 package)
(PSDIP8 package)
40 sec
10 sec
215
260
°C
V
V
V
ESD
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maxim um Ratings"
Input or Output Voltages –0.3 to 6.5 V
IO
Supply Voltage –0.3 to 6.5 V
CC
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicat ed in the Operati ng sections of this specific ati on is not implied. Expos ure to Absolut e Maximum
Rating conditions for extended periods may affect device rel i abi lity. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
(2)
(3)
4000 V
500 V
T ab le 3. Device Select Co de
Device Code Chip Enable RW
Bit b7 b6 b5 b4 b3 b2 b1 b0
Device Select 1 0 1 0 X X X R
Note: The MSB b7 is sent first.
X = 0 or 1.
W
2/18
Figure 3. Transmi t Only Mode W avefo rms
V
CC
SCL
ST24LC21
SDA
VCLK
V
CC
SCL
SDA
VCLK
Bit 7
tVPU
12 891011
Bit 6 Bit 4 Bit 0
Bit 5
12 13 17 18 19 20
Bit 7
Bit 6
Bit 6
AI01501
T ab le 4. Operating Modes
Mode RW bit VCLK Bytes Initial Sequence
Current Address Read ’1’ X 1 START, Device Select, R
Random Address Read
’0’ X
1
START, Device Select, R
’1’ X reSTART, Device Select, R
Sequential Read ’1’ X 1 to 128 Similar to Current or Random Mode
Byte Write ’0’ V
Page Write ’0’ V
Note: X = VIH or V
IL
IH
IH
1 START, Device Select, RW = ’0’
8 START, Device Select, RW = ’0’
W = ’1’
W = ’0’, Address,
W = ’1’
3/18
ST24LC21
Figure 4. Transit ion Mode W avefo rm s
SCL
SDA
VCLK
Bi-Directional ModeTransmit Only Mode
AI01502
Transmit Only Mode
After a Power-up, the device is in the Transmit O nly
mode. A proper initialization sequence must supply
nine clock pulses on the VCLK pin (in order to
internally synchronize the device). During this initialization sequence, the S DA pin is in high im pedance. On the rising edge of the tenth pulse applied
on VCLK pin, the device will output the first bit of
byte located at address 00h (most significant bit
first).
A byte is clocked out (on SDA pin) with nine clock
pulses on VCLK: 8 clock pulses for the data byte
and one extra clock pulse for a Don’t Care bit.
As long as the SCL pin is held high, each byte of
the memory arr ay is transmitted s erially on the SDA
pin with an automatic address increment.
When the last byte is transmitted, the address
counter will roll-over to location 00h.
2
C Bidirectional Mode
I
The device can be switched from Transmit Only
mode to I2C Bidirectional mode by applying a valid
high to low transition on the SCL pin (see Figure 4).
When the device is in the I2C Bidirectional mode,
the VCLK input enables (or inhibits) the executio n
of any write instruction: if VCLK = 1, write instructions are executed; if VCLK = 0, write instructions
are not executed.
2
The device is compatible wit h the I
C standard, two
wire serial interfac e which uses a bi-directional dat a
bus and serial clock. The device carries a built-in 4
bit, unique device identification code (1010) corresponding to the I
The device behaves as a slave device in the I
2
C bus definition.
2
protocol with all memory operations synchronized
by the serial clock. Read and write operations are
initiated by a START condition generated by the
bus master. The START condition is followed by a
stream of 7 bits (identification code 1010XX X), plus
one read/write bit and terminated by an acknowledge bit.
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are terminated with a STOP condition.
Power On Reset: V
lock out write protect. In
CC
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the V
CC
voltage has reached the POR thres hold value, t he
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when V
drops down from the
CC
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V
CC
must be applied before applying any logic signal.
C
4/18
ST24LC21
SIGNAL DESCRIPTIONS
2
I
C Serial Clock (SCL ). The SCL input pin is used
to synchronize all data in and out of the memory . A
resistor can be connected from the SCL line to V
CC
to act as a pull up (see Figure 5).
Tr ansmit Only C lock (VCLK). The VCLK input pin
is used to synchronize data out when the
ST24LC21 is in Transmit Only mode. The VCLK
input offers also a Write Enable (active high) function when the ST24LC21 is in I
2
C bidirectional
mode.
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory .
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V
to act as pull up (see Figure 5).
CC
DEVICE OPER ATION
2
I
C Bus Background
The ST24LC21 supports the I
2
C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device t hat reads
the data as a receiver . The device that c ontrols th e
data transfer is known as the master and the other
as the slave. The master will alway s initiate a dat a
transfer and will provide the serial clock for synchronisation. The ST24LC21 are always slave d evices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condit ion must
precede any command for data transfer. Except
during a programming cycle, the ST24LC21 continuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition terminates communication between the ST24LC21 a nd
the bus master. A STOP condition at the end of a
Read command forces the standby stat e. A STO P
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter , either master or slave, will re lease
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Figure 5. Maximum RL Value versus Bus Capacitance (C
20
16
12
8
Maximum RP value (kΩ)
4
0
10 1000
C
BUS
fc = 400kHz
100
(pF)
fc = 100kHz
) for an I2C Bus
BUS
V
MASTER
CC
SDA
SCL
R
R
C
BUS
L
C
BUS
AI01665
L
5/18
ST24LC21
T able 5. Input Parameters
(1)
(TA = 25 °C, f = 100 kHz )
Symbol Parameter Test Condition Min Max Unit
C
IN
C
IN
t
LP
Note: 1. Sampled only, n ot 100% tested.
Input Capacitance (SDA) 8 pF
Input Capacitance (other pins) 6 pF
Low-pass filter input time constant
(SDA and SCL)
300 ns
T ab le 6. DC Characteristics
= 0 to 70 °C; VCC = 2.5V to 5.5V)
(T
A
Symbol Parameter Test Condition Min Max Unit
I
I
I
LI
I
LO
CC
CC1
Input Leakage Current 0V ≤ VIN ≤ V
Output Leakage Current
Supply Current
Supply Current V
Supply Current (Standby)
0V ≤ V
V
= 5V, fC = 400kHz
CC
(Rise/Fall time < 10ns)
= 2.5V, fC = 400kHz 1 mA
CC
V
IN
V
IN
= 5V, fC = 400kHz
V
CC
≤ VCC
OUT
SDA in Hi-Z
= VSS or VCC,
= 5V
V
CC
= VSS or VCC,
CC
±2 µA
±2 µA
2mA
100 µA
300 µA
I
V
V
V
CC2
V
V
OL
V
= VSS or VCC,
IN
V
= 2.5V
Supply Current (Standby)
V
IL
IH
IL
IH
Input Low Voltage (SCL, SDA) –0.3 0.3 V
Input High Voltage (SCL, SDA) 0.7 V
Input Low Voltage (VCLK)
Input High Voltage (VCLK) 2 VCC + 1 V
Output Low Voltage
CC
V
= VSS or VCC,
IN
= 2.5V, fC = 400kHz
CC
CC
2.5V ≤ VCC ≤ 4V –0.3 0.2 V
V
> 4V –0.3 0.8 V
CC
IOL = 3mA 0.4 V
I
= 6mA, VCC = 5V 0.6 V
OL
5 µA
50 µA
CC
VCC + 1 V
CC
V
V
6/18
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