SGS Thomson Microelectronics ST24LW21, ST24LC21B, ST24FW21, ST24FC21 Datasheet
1 Kbit (x8) Dual Mode Serial EEPROM
1 MILLION ERASE/WRITE CYCLES
40 YEARS DA TA RETE NTION
3.6V to 5.5V SINGLE SUPPLY VOLTA GE
HARDWARE WRITE CONT ROL (ST24LW21
and ST24FW21)
TTL SCHMITT-TRIGGER on VCLK INPUT
100k / 400k Hz COMPATIBILITY with the I2C
BUS BIT TRANSFER RANGE
TWO WIRE SERIAL INTERFACE I2C BUS
COMPATIBLE
I2C PAGE WRITE (up to 8 Bytes)
I2C BYTE, RANDOM and SEQUENTIAL RE AD
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCE D ESD/LATCH UP
PERFORMANCES
ERROR RECOVERY MECHA NI SM
(ST24FC21 and ST24FW21) VESA 2
COMPATIBLE
ST24LC21B, ST24LW21
ST24FC21, ST24FW21
for VESA PLUG & PLAY
8
1
PSDIP8 (B)
0.25mm Frame
Figure 1. Logic Diagram
8
1
SO8 (M)
150mil Width
V
DESCRIPTION
CC
The ST24LC21B, ST24LW21, ST24FC21 and
ST24FW21 are 1K bit electrically erasable programmable memory (EEPROM), organized in
128x8 bits. In the text, products are referred as
SCL
SDA
ST24xy21, where "x" is either "L" for VESA 1 or "F"
for VESA 2 com patible memories and where "y"
indicates the Write Control pin connection: "C"
ST24xy21VCLK
means WC on pin 7 and "W" means WC on pin 3.
WC
T ab le 1. Signal Names
SDA Serial Data Address Input/Output
2
SCL Serial Clock (I
V
CC
V
SS
VCLK Clock Transmit only mode
WC Write Control
January 1999 1/21
Supply Voltage
Ground
C mode)
Note:
WC signal is only available for ST24LW21 and ST24FW21
products.
V
SS
AI01741
ST24LC21B, ST24LW21, ST24FC21, ST24FW21
Figure 2A. DIP Pin Connections
ST24LC21B
8
7
6
5
AI01742
VCLKNC
SCL
SDAV
Warning:
1
NC V
2
3
NC
4
SS
NC = Not Connected.
Figure 2C. DIP Pin Connections
ST24FC21
1
NC V
2
3
DU
4
SS
8
7
6
5
AI01744
VCLKNC
SCL
SDAV
CC
CC
Figure 2B. SO Pin Connections
ST24LC21B
8
7
6
5
AI01743
Warning:
NC V
1
2
NC
SS
NC = Not Connected.
3
4
Figure 2D. SO Pin Connections
ST24FC21
NC V
1
2
DU
SS
3
4
8
7
6
5
AI01745
CC
VCLKNC
SCL
SDAV
CC
VCLKNC
SCL
SDAV
Warning:
be left open or connected to V
NC = Not Connected. DU = Don’t Use, must
or VSS.
CC
Figure 2E. DIP Pin Connections
ST24FW21
ST24LW21
8
7
6
5
AI01746
VCLKNC
SCL
SDAV
Warning:
2/21
1
NC V
2
3
WC
4
SS
NC = Not Connected.
CC
Warning:
be left open or connected to V
NC = Not Connected. DU = Don’t Use, must
or VSS.
CC
Figure 2F. SO Pin Connections
ST24FW21
ST24LW21
8
7
6
5
AI01747
Warning:
NC V
1
2
WC
SS
NC = Not Connected.
3
4
CC
VCLKNC
SCL
SDAV
ST24LC21B, ST24LW21, ST24FC21, ST24FW21
T ab le 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
T
V
Notes:
T
STG
LEAD
V
V
ESD
Ambient Operating Temperature –40 to 85
A
Storage Temperature –65 to 150
Lead Temperature, Soldering (SO8 package)
Input or Output Voltages –0.3 to 6.5 V
IO
Supply Voltage –0.3 to 6.5 V
CC
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress rating s only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
(1)
(PSDIP8 package)
40 sec
10 sec
(2)
(3)
215
260
4000 V
500 V
T ab le 3. Device Select Code
Device Code Chip Enable RW
Bit b7 b6 b5 b4 b3 b2 b1 b0
Device Select 1 0 1 0 X X X R
Note:
The MSB b7 is sent first.
X = 0 or 1.
W
C
°
C
°
C
°
DESCRIPTION (cont’d)
The ST24xy21 can operate in two modes: Trans-
mit-Only mode and I
2
C bidirectional mode. When
powered, the device is in Tr ansmit-Only mode with
EEPROM data clocked out from the rising edge of
the signal applied on VCLK.
2
The device will switch to the I
upon the falling edge of the signal applied on SCL
pin. When in I
2
C mode, the ST24LC21B (or the
C bidirectional mode
ST24LW21) cannot switch back to the Transmit
Only mode (except when the power supply is removed). For the ST24FC21 (or the ST24FW21) ,
after the falling edge of SCL, the memory enter in
a transition state which allowed to switch back to
the Transmit-Only mode if no valid I
2
C activity is
observed. The device operates with a power supply
value as low as +3.6V. Both Plastic Dual-in-Line
and Plastic Small Outline packages are available.
Transmit Only Mode
After a Power-up, the ST24xy21 is in the Transmit
Only mode. A proper initialization sequence (see
Figure 3) must supply nine clock pulses on the
VCLK pin (in order to internally synchronize the
device). During this initialization sequence, the
SDA pin is in high im pedance. On the rising edge
of the tenth pulse applied on VCLK pin, the device
will output the first bit of byte located at address 00h
(most significant bit first).
A byte is clocked out (on SDA pin) with nine clock
pulses on VCLK: 8 clock pulses for the data byte
and one extra clock pulse for a Don’t Care bit.
As long as the SCL pin is held high, each byte of
the memory array is transm itted serially on the SDA
pin with an automatic address increment.
When the last byte is transmitted, the address
counter will roll-over to location 00h.
3/21
ST24LC21B, ST24LW21, ST24FC21, ST24FW21
Figure 3. Transmit Only Mode Wavefor ms
V
CC
SCL
SDA
VCLK
V
CC
SCL
SDA
VCLK
tVPU
1 2 8 9 10 11
Bit 6 Bit 4 Bit 0
Bit 5
12 13 17 18 19 20
Bit 7
Bit 7
Bit 6
Bit 6
AI01501
T able 4. I2C Operating Modes
Mode
Current Address
Read
Random Address
Read
R
ST24LC21B
W
bit
ST24FC21
VCLK
’1’ X X 1 START, Device Select, R
’0’ X X
’1’ X X reSTART, Device Select, R
Sequential Read ’1’ X X 1 to 128 Similar to Current or Random Mode
Byte Write ’0’ V
Page Write ’0’ V
Note:
X = V
or V
IH
IL
IH
IH
4/21
ST24LW21
ST24FW21WCBytes Initial Sequence
W = ’1’
START, Device Select, RW = ’0’, Address,
1
W = ’1’
V
IH
V
IH
1 START, Device Select, RW = ’0’
8 START, Device Select, RW = ’0’
ST24LC21B, ST24LW21, ST24FC21, ST24FW21
Figure 4. Transition from Transmit Only (DDC1) to Bi-directional (DDC2B) Mode Waveforms
Transmit Only Mode
SCL
SDA
VCLK
- Temporary Bi-Directional Mode
(ST24FC21 and ST24FW21)
- Locked Bi-Directional Mode
(ST24LC21B and ST24LW21)
START
CONDITION
I2C Bidirectional Mode
The ST24xy21 can be switched from T ransmit Only
mode to I
2
C Bidirectional mode by apply ing a valid
high to low transition on the SCL pin (see Figure 4).
– When the ST24LC21B (or the ST24FC21) is in
2
C Bidirectional mode, the VCLK input
the I
(pin 7) enables (or inhibits) the exec ution of
any write instruction: if VCLK = 1, write instructions are executed; if VCLK = 0, write instructions are not executed.
– When the ST24LW21 (or the ST24FW21) is in
2
C Bidirectional mode, the Write Control
the I
(WC on pin 3) input enables (or inhibits) the
execution of any write instruction: if WC = 1,
write instructions are executed;if WC = 0,
write instructions are not executed.
2
The ST24xy21 is compatible with the I
C standard,
two wire serial interface whic h uses a bidirectional
data bus and serial clock. The device carries a
built-in 4 bit, unique device identification code
(1010) named Device Select code corresponding
2
to the I
The ST24xy21 behaves as a slave device in t he
2
I
C bus definition.
C protocol with all memory operations synchronized by the serial clock SCL. Read and write
operations are initiated by a STAR T condition gen-
- Locked Bi-Directional
Mode (ST24FC21
and ST24FW21)
1
MSB
2
89
ACK
erated by the bus master. The START condition is
followed by a stream of 7 bits (Device Select code
1010XXX), plus one read/write bit and terminated
by an acknowledge bit.
When data is written into the memory, the
ST24xy21 responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time.
When data is read by the bus master, it must
acknowledges the receipt of the data bytes in the
same way. Data transfers are terminated with a
STOP condition (see READ and WRITE desc riptions in the following pages).
Power On Reset: V
lock out write protect
CC
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the V
voltage has reached the POR threshold value
(around 3V), the internal reset is active, all operations are disabled and the device will not respond
to any command. In the same way, when V
down from the operating voltage to below the P OR
threshold value, all operations are disabled and the
device will not respond to any command. A stable
must be applied before applying any logic
V
CC
signal.
AI01892
CC
CC
drops
5/21
ST24LC21B, ST24LW21, ST24FC21, ST24FW21
Figure 5. Error Recovery Mechanism Flowchart for the ST24FC21 and ST24FW21 products
Memory Power On
Internal Address Pointer = 0
Transition
State
(VESA 2)
VCLK
NO
NO
VCLK Internal Counter = 0
Start Internal 2 sec Timer
(START + Device Select)
NO
SCL
SDA Hi-Z
SCL
NO
Valid
2
C access
I
VCLK
YES
YES
YES
?
Send Data bit (MSB first) pointed
by the Address Pointer and
auto-increment pointed bit/byte
Reset VCLK Internal Counter
and Reset Internal Timer
YES
I2C communication idle
waiting for a Device Select byte
Transmit-Only Mode
(DDC1)
6/21
Increment VCLK Counter
NO
Counter = 128
or Timer > 2 sec
Switch Back to
Transmit-Only Mode
YES
YES
Reset Counter and Timer
Send Acknowledge
Respond to the Incoming
2
C Command
I
I2C Mode
(DDC2B)
AI01748
ST24LC21B, ST24LW21, ST24FC21, ST24FW21
Figure 6. Maximum RL Value versus Bus Capacitance (C
20
16
12
8
Maximum RP value (kΩ)
4
0
10 1000
C
BUS
fc = 400kHz
100
(pF)
Error Recovery Modes available in the
ST24FC21 and the ST24FW21
When the ST24FC21 (or the ST24FW21) first
switches to the I
enters a transition state which is functionally identical to I
2
C operation. But, if the ST24FC21 (or the
2
C mode (VESA DDC2B mode), it
ST24FW21) does not received a valid I
quence, that is a START condition followed by a
valid Device Select code (1010XXX R
W), within
either 128 VCLK periods or a period of time of
t
RECOVERY
(approximately 2 seconds), the
ST24FC21 (or the ST24FW21) will revert to the
Transmit-Only mode (VESA DDC1 mode).
If the ST24FC21 (or the ST24FW21) decodes a
2
valid I
C Device Select code, it will lock into I2C
mode. Under this condition, signals applied on the
VCLK input will not disturb READ access from the
ST24FC21 (or the ST24FW21). For WRITE access, refer to the Signal Desc r iption paragraph.
When in the transition state, the count of VCLK
pulses and the internal 2 seconds timer are reset
by any activity on the SCL line. This me ans that,
after each high to low transition on SCL, the m emory will re-initialise its transition state and will switch
back to Transmit-Only mode only after 128 more
VCLK pulses or after a new t
RECOVERY
delay.
2
C se-
fc = 100kHz
SIGNAL DESCRIP TIONS
I
to synchronize all data in and out of the memory . A
resistor can be connected from the SCL line to V
to act as a pull up ( see Figure 6).
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V
Tr ansmit Only Clock (VCLK). The VCLK input pin
is used to synchronize data out when the
ST24xy21 is in Transmit Only mode.
For the ST24LC21B and the ST24FC21 Only, the
VCLK offers also a Write Enable (active high) function when the ST24LC21B and the ST24FC21 are
in I
Write Control (WC). An hardware Wri te Control
feature (WC) is offered only on ST24LW21 and
ST24FW21 on pin 3. This feature is usefull to
protect the contents of the memory from any erroneous erase/write cycle. The Write Control signal
is used to enable (WC = V
the internal write protection. When unconnected,
the WC input is internally tied to V
2
C Serial Clock (SCL). The SCL input pin is used
2
C bidirectional mode.
pull-down resistor and the memory is write protected.
) for an I2C Bus
BUS
V
MASTER
to act as pull up (see F igure 6).
CC
CC
R
SDA
SCL
) or disable (WC = VIH)
IL
R
L
SS
L
C
BUS
AI01665
by a 100k ohm
C
BUS
CC
7/21
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