SGS Thomson Microelectronics ST25W16, ST25C16, ST24W16, ST24C16 Datasheet

with User-Defined Block Write Protection

1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DAT A RE TENTION

SINGLE SUPPLY VOLTAGE:
– 4.5V to 5.5V for ST24x16 versions
– 2.5V to 5.5V for ST25x16 versions
HARDWARE WRITE CONT ROL VERSIONS:

ST24W16 and ST25W16
TWO WIRE SERIAL INTERFACE, FULLY I2C

BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 8

BYTES) for the ST24C16
PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ

MODES
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREME NTING
ENHANCE D ESD/LATCH UP

PERFORMANCES

ST24C16, ST25C16

ST24W16, ST25W16

16 Kbit Serial I2C Bus EEPROM

8

1

PSDIP8 (B)

0.25mm Frame

Figure 1. Logic Diagram

8

1

SO8 (M)

150mil Width

DESCRIPTION

This specification covers a range of 16 Kbit I

2

C bus
EEPROM products, the ST24/25C16 and the
ST24/25W16. In the text, products are referred to
as ST24/25x16 where "x" is: "C" for Standard ver­sion and "W" for hardware Write Control version.

The ST24/25x16 are 16 Kbit electrically erasable
programmable memories (EEPROM), organized
as 8 blocks of 256 x8 bits. These are manufactured
in STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endur-

T ab le 1. Signal Names

PRE Write Protect Enable
PB0, PB1 Protect Block Select
SDA Serial Data Address Input/Output
SCL Serial Clock

MODE
WC Write Control (W version)

V

CC

V

SS

Multybyte/Page Write Mode
(C version)

Supply Voltage
Ground

V

CC

2

PB0-PB1 SDA

PRE

SCL

MODE/WC*

Note:

WC signal is only available for ST24/25W16 products.

ST24x16
ST25x16

V

SS

AI00866B

February 1999 1/17

ST24/25C16, ST24/25W16

Figure 2A. DIP Pin Connections

ST24x16
ST25x16

1

PRE V

2
3

PB1

4

SS

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

Ambient Operating Temperature –40 to 125

8
7
6
5

AI00867B

CC

MODE/WCPB0
SCL
SDAV

(1)

Figure 2B. SO8 Pin Connections

ST24x16
ST25x16

PRE V

1
2

PB1

SS

3
4

8
7
6
5

AI00500B

CC

MODE/WCPB0
SCL
SDAV

C

°

T

STG

T

LEAD

V

IO

V

CC

V

ESD

Notes:

1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refe r also to t he STM icro ele ctr oni cs SURE Pro gr am and
other relevant quality documents .

2. 100pF through 1500Ω; MIL-STD-883C, 3015.7

3. 200pF through 0Ω; EIAJ IC-121 (condition C)

DESCRIPTION (cont’d) carry a built-in 4 bit, unique device identification
ance of one million erase/write cycles with a data

retention of 40 years. The ST25x16 operates wit h
a power supply value as low as 2.5V. Both Plastic
Dual-in-Line and Plastic Small Outline packages
are available.

The memories are compatible with the I
ard, two wire serial interface which uses a bi-direc­tional data bus and serial clock. The memories

Storage Temperature –65 to 150
Lead Temperature, Soldering (SO8)

Input or Output Voltages –0.6 to 6.5 V
Supply Voltage –0.3 to 6.5 V
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

(PSDIP8)

(3)

code (1010) corresponding to the I
tion. The memories behave as slave devices in the

2

C protocol with all memory operations synchro-

I

40 sec
10 sec

(2)

215
260

4000 V

500 V

2

C bus defini-

nized by the serial clock . Read and write operations
are initiated by a START condition generated by the
bus master. The START condition is followed by a

2

C stand-

stream of 4 bits (identification code 1010), 3 block
select bits, plus one read/write bit and terminated
by an acknowledge bit. When writing data to the

C

°

C

°

2/17

ST24/25C16, ST24/25W16

T ab le 3. Device Select Code

Device Code Memory MSB Addresses RW

Bit b7 b6 b5 b4 b3 b2 b1 b0
Device Select 1 0 1 0 A10 A9 A8 R

Note:

The MSB b7 is sent first.

T ab le 4. Operating Modes

Mode RW bit MODE pin Bytes Initial Sequence

Current Address Read ’1’ X 1 START, Device Select, R

Random Address Read

Sequential Read ’1’ X 1 to 2048 As CURRENT or RANDOM Mode
Byte Write ’0’ X 1 START, Device Select, R
Multibyte Write ’0’ V
Page Write ’0’ V

Note:

X = V

or VIL.

IH

memory it responds to the 8 bits received by as­serting an acknowledge bit during the 9th bit time.
When data is read by the bus master, it acknow­ledges the receipt of the data bytes in the sam e
way. Data transfers are terminated with a STOP
condition.

Data in the 4 upper blocks of t he memory may be
write protected. The protected area is programma­ble to start on any 16 byte boundary. The block in
which the protection starts is selected by the input
pins PB0, PB1. Protection is enabled by setting a
Protect Flag bit when the PRE input pin is driven

’0’
’1’ reSTART, Device Select, R

X1

IH

IL

8 START, Device Select, RW = ’0 ’

16 START, Device Select, RW = ’0’

Power On Reset: V

order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Untill the V
voltage has reached the POR threshold value, the
internal reset is active: all operations are disabled
and the device will not respond to any c ommand.
In the same way, when V
operating voltage to below the POR threshold
value, all operations are disabled and the dev ice
will not respond to any command. A stable V
must be applied before applying any logic signal.

START, Device Select, R

lock out write pr otec t. In

CC

CC

W = ’1’
W = ’0’, Address,

W = ’1’

W = ’0’

drops down from the

High.

W

CC

CC

3/17

ST24/25C16, ST24/25W16

SIGNALS DESCRIPTION
Serial Clock (SCL). The SCL input signal is used

to synchronise all data in and out of the memory . A
resistor can be connected from the SCL line to V

CC

to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA signal is bi-directional

and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V

to act as pull up (see Figure 3).

CC

Protected Block Select (PB0, PB1). PB0 and PB1
input signals select the block in the upper part of
the memory where write protection starts. These
inputs have a CMOS compatible input level.

Protect Enable (PRE). The PRE input signal, in
addition to the status of the Block Address Pointer
bit (b2, location 7FFh as in Figure 7), sets the PRE

Mode (MODE). The MODE input is available on pin
7 (see also
cally. It must be at V
mode, V
Write mode. When unconnected, the MODE input
is internally read as V

Write Control (

feature is offered only for ST24W16 and ST25W16
versions on pin 7. This feature is usefull to protect
the contents of the memory from any erroneous
erase/write cycle. The Write Control signal is used
to enable (
internal write protection. When unconnected, the
WC input is internally read as VIL. The devices with
this Write Control feature no longer supports the
Multibyte Write mode of operation, however all
other write modes are fully supported.

Refer to the AN404 Application Note for more de­tailed information about Write Control feature.

write protection active.

Figure 3. Maximum RL Value versus Bus Capacitance (C

WC feature) and may be driven dynami-

or VIH for the Byte Write

for Multibyte Write mode or VIL for Page

IH

IL

(Multibyte Write mode).

IH

WC). An hardware Write Control

WC at VIH) or disable (WC at VIL) the

) for an I2C Bus

BUS

20

V

CC

16

R

12

max (kΩ)

L

R

8

4

0

VCC = 5V

100 200 300 400

C

(pF)

BUS

MASTER

SDA

SCL

R

BUS

L

C

BUS

AI01100

L

C

4/17

ST24/25C16, ST24/25W16

T able 5. Input Parameters

(1)

(TA = 25 °C, f = 100 kHz )

Symbol Parameter Test Condition Min Max Unit

C

IN

C

IN

Z

WCL

Z

WCH

t

LP

Note:

1. Sampled only, not 100% tested.

Input Capacitance (SDA) 8 pF
Input Capacitance (other pins) 6 pF
WC Input Impedance (ST24/25W16) VIN ≤ 0.3 V
WC Input Impedance (ST24/25W16) VIN ≥ 0.7 V
Low-pass filter input time constant

(SDA and SCL)

CC

CC

520k

500 k

100 ns

T ab le 6. DC Characteristics

(T

= 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)

A

Symbol Parameter Test Condition Min Max Unit

I

LI

I

LO

I

CC

Input Leakage Current 0V ≤ VIN ≤ V

Output Leakage Current

Supply Current (ST24 series)

Supply Current (ST25 series) V

0V ≤ V

V

= 5V, fC = 100kHz

CC

(Rise/Fall time < 10ns)

= 2.5V, fC = 100kHz 1 mA

CC

≤ VCC

OUT

SDA in Hi-Z

CC

2

±

2

±

2mA

Ω
Ω

A

µ

A

µ

I

CC1

I

CC2

V

V

V

V

V

OL

V

= VSS or VCC,

IN

= 5V

V

Supply Current (Standby)
(ST24 series)

V

Supply Current (Standby)
(ST25 series)

V

IL

IH

IL

IH

Input Low Voltage (SCL, SDA) –0.3 0.3 V
Input High Voltage (SCL, SDA) 0.7 V
Input Low Voltage

(PB0 - PB1, PRE, MODE,

WC)

Input High Voltage
(PB0 - PB1, PRE, MODE,

WC)

CC

V

= VSS or VCC,

IN

= 5V, fC = 100kHz

CC

V

= VSS or VCC,

IN

= 2.5V

V

CC

V

= VSS or VCC,

IN

= 2.5V, fC = 100kHz

CC

CC

–0.3 0.5 V

V

– 0.5 VCC + 1 V

CC

100

300

5

50

CC

µ

µ

µ

µ

VCC + 1 V

A

A

A

A

V

Output Low Voltage (ST24 series) IOL = 3mA, VCC = 5V 0.4 V
Output Low Voltage (ST25 series) I

= 2.1mA, VCC = 2.5V 0.4 V

OL

5/17

ST24/25C16, ST24/25W16

T ab le 7. AC Characteristics

(T

= 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)

A

Symbol Alt Parameter Min Max Unit

t

CH1CH2

t

CL1CL2

t

DH1DH2

t

DL1DL1

(1)

t

CHDX

t

CHCL

t

DLCL

t

CLDX

t

CLCH

t

DXCX

t

CHDH

t

DHDL

(2)

t

CLQV

t

CLQX

f

C

(3)

t

W

Notes:

1. For a reSTART condition, or following a write cycle.

2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.

3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (5 address MSB are not constant)

the maximum programming time is doubled to 20ms.

t
t
t
t

t

SU:STA

t

HIGH

t

HD:STA

t

HD:DAT

t

LOW

t

SU:DAT

t

SU:STO

t

BUF

t

AA

t

DH

f

SCL

t

WR

R

F

R

F

Clock Rise Time 1
Clock Fall Time 300 ns
Input Rise Time 1
Input Fall Time 300 ns
Clock High to Input Transition 4.7
Clock Pulse Width High 4
Input Low to Clock Low (START) 4
Clock Low to Input Transition 0
Clock Pulse Width Low 4.7
Input Transition to Clock Transition 2 50 ns
Clock High to Input High (STOP) 4.7
Input High to Input Low (Bus Free) 4.7
Clock Low to Next Data Out Valid 0.3 3.5
Data Out Hold Time 300 ns
Clock Frequency 100 kHz
Write Time 10 ms

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

Tabl e 8. AC Measurement Conditions

Input Rise and Fall Times
Input Pulse Voltages 0.2V
Input and Output Timing Ref.

Voltages

50ns

≤

0.3V

to 0.8V

CC

to 0.7V

CC

CC

CC

Figure 4. AC Testing Input Output Waveforms

0.8V

6/17

0.2V

CC

CC

0.7V

0.3V

AI00825

CC

CC

DEVICE OPERATION

2

C Bus Background

I
The ST24/25x16 support the I

2

C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn­chronisation. The ST24/25x16 are always slave
devices in all communications.

Start Co nditi on. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A ST ART condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x16 con­tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.