SGS Thomson Microelectronics ST14C02C Datasheet

2 Kbit (256 x 8) Serial I2C Bus EEPROM

■ Single Supply Voltage (3 V to 5.5 V)

C bus.

2

C Serial Interface

2

C standard.

2

C bus

■ Two Wire I

■ BYTE and MULTBYTE WRITE (up to 4 Bytes)

■ PAGE WRIT E (up to 8 Bytes )

■ BYTE, RANDOM and SEQUENTIAL READ

Modes

■ Self-Tim e d P ro g r amming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ 1 Million Erase/Write Cycles (minimum)

■ 10 Year Data Retention (minimum)

DESCRIPTION

This device is an electrically erasable programma­ble memory (EEPROM) fabricated with

STMicroelectronics’s High Endurance, Advanced
Polysilicon, CMOS technology. This guarantees
an endurance typically well above one million
Erase/Write cycles, with a data retention of 10
years. The memory operates with a power supply
as low as 3 V.

The device is available in wafer form (either sawn
or unsawn) and in micromodule form (on film).

The memory is compatible with the I
This is a two wire serial interface that uses a bi-di­rectional data bus and serial clock. The me mory
carries a built-in 7-bit unique Device Type Identifi­er code (1010000) in accordance with the I
definition. Only one memory can be attached to

2

each I

Memory Card IC

Micromodule (D15)

Wafer

Figure 1. Logic Diagram

V

CC

ST14C02C

2

2

Micromodule (D20)

2

2

Table 1. Signal Names

SDA Serial Data/Address Input/

Output
SCL Serial Clock
MODE Write Mode
V

CC

GND Ground

Supply Voltage

SCL

MODE

ST14C02C

GND

SDA

AI01162

1/12DS.ST14C02C/9811V2

ST14C02C

Figure 2. D15 Contact Connections

V

CC

SCL

GND

SDA

AI02492

The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and write o perations are
initiated by a START condition, gene rated by the
bus master. The STA RT condition is followed by
the Device Select Code which is compos ed of a
stream of 7 bits (1010000), plus one read/write bit
(R/W

) and is terminated by an acknowledge bit.

When writing data to the memory, the mem ory in­serts an acknowledge bit during the 9

th

bit time,

following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af­ter a NoACK for READ.

Figure 3. D20 Contact Connections

V

CC

SCL

GND

SDA

MODE

AI02491

Power On Reset: VCC Lock-Out Write Protect

In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re­set (POR) circuit is included. The internal reset is
held active until the V

voltage has reached the

CC

POR threshold value, and all operations are dis­abled – the device will not respond to any com­mand. In the same way, when V

drops from the

CC

operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any com ma nd. A s table a nd v alid V

CC

must be applied before applying any logic signal.

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

V

IO

V

CC

V

ESD

Note: 1. Exc ept for the rating “Operating Temperature Ra nge”, stresses above those li sted in t he Table “A bsolute Maximum Ratings” m ay

2/12

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indi cated in t he Operating sect i ons of thi s specif i cation is not imp l i ed. Exposure to Absolute M aximum Rating condi­tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL -STD-883C, 3015.7 (1 00 pF, 1500 Ω)

3. EIA J I C-121 (Condition C) (200 pF, 0 Ω)

Ambient Operating Temperature 0 to 70 °C

Storage Temperature

Input or Output range -0.3 to 6.5 V
Supply Voltage -0.3 to 6.5 V

Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

1

Wafer form
Module form

2

3

-65 to 150

-40 to 120

4000 V

500 V

°C

Table 3. Endurance and Data Retention

Device Endurance (Erase/Write Cycles) Data Retention (Years)

ST14C02C 1,000,000 10

ST14C02C

SIGNAL DESCRIPTION
Serial Clock (SCL)

The SCL input pin is used to sync hronize all data
in and out of the memory. A pull up resistor can be
connected from the SCL line to V

. (Figure 4 in-

CC

dicates how the value of the pull-up resistor can be
calculated).

Serial Data (SDA)

The SDA pin is bi-directional, and is used to trans­fer data in or out of the memory. It is an open drain

output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to V

. (Figure 4 indicates how the value of the

CC

pull-up resistor can be calculated).

Mode (MOD E )

The MODE input may be driven dynamically. It
mus t be held at:

■ V

or VIH for the Byte Write mode

IL

■ V

for Multibyte Write mode

IH

■ V

for Page Write mode

IL

When unconnected, the MODE input is internally
read as a V

(Multibyte Write mode). Note that the

IH

voltages are CMOS levels, and are not TTL com­patible.

On the D15 micromodule, the MODE pin is not
connected to a contact. T his pin is left f loating on
the silicon. This type of ST14C02C is always in its
MultiByte mode, and cannot be changed from this.

DEVICE OPERATION

2

The memory device supports the I

C protocol, as
summarized in Figure 5. Any device that sends
data on to the bus is defined to be a transmitte r,
and any device that reads the data to be a receiv­er. The device that controls the data transfer is
known as the mast er, and the other as the slave.
A data transfer can only be initiated by the master,
which will also provide the serial clock for synchro­nization. The memory device is always a slave de­vice in all communication.

Figure 4. Maximum RL Value versus Bus Capacitance (C

20

16

12

max (kΩ)

L

R

8

4

0

VCC = 5V

100 200 300 400

C

(pF)

BUS

) for an I2C Bus

BUS

V

CC

SDA

MASTER

SCL

R

R

BUS

L

C

BUS

AI01100

3/12

L

C

ST14C02C

Figure 5. I2C Bus Protocol

SCL

SDA

SCL

SDA

SCL

SDA

START

CONDITION

START

CONDITION

SDA

INPUT

1 23 789

MSB

1 23 789

MSB ACK

SDA

CHANGE

CONDITION

ACK

STOP

STOP

CONDITION

AI00792

Start Condition

START is identified by a high t o low transition of
the SDA line while the clock, SCL, is s table i n t he
high state. A START condition must precede any
data transfer command. The memory continuously
monitors (except during a programming cycle) the
SDA and SCL lines for a START condition, and will
not respond unless one is given.

Stop Condition

STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high

Table 4. Device Select Code

b7 b6 b5 b4 b3 b2 b1 b0

Device Select 1010000RW

Note: 1. The most significant bit, b 7, is sent first.

4/12

1

state. A STO P condition terminates c ommunica­tion between the memory an d the bus master. A
STOP condition at the end of a Read command
forces the memory device into its standby state. A
STOP condition at the end of a Write com mand
triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a suc­cessful data transfer. The bus transmitter, either
master or slave, will release the SDA bus after
sending 8 bits of data. During t he 9

Device Code RW

th

clock pulse

ST14C02C

period the receiver pulls the SDA bus low to ac­knowledge the receipt of the 8 data bits.

Data Input

During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi-

only

tion, and the data must change

when the SCL

line is low.

Memory Addressing

To start communication betwee n the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
8 bits to the SDA bus line (with the most significant
bit first). These bits represent the Device Select
Code (7 bits) and a RW

bit.

The seven most s ignificant bits of the Device Se­lect Code are the Device Type Identifier, according
to the I

2

C bus definition. For the mem ory device,
the seven bits are fixed at 1010000b (A0h), as
shown in Table 4.

th

The 8

bit is the read or write bit (RW). This bit is

set to ‘1’ for read and ‘0’ for write operations. If a
match occurs on the Device Select Code, the cor­responding memory gives an acknowledgment on
the SDA bus during the 9

th

bit time.

Write Operations

The Multibyte Write mode is selected when the
MODE pin is at V
selected when MODE pin is at V

, and the Page Write mo de is

IH

. The MODE pin

IL

may be driven dynamically to CMOS input levels.

Following a START condition, the master sends a
Device Select Code with the RW

bit res et to ‘0’.
The memory device acknowledges this, and waits
for a byte address. The 8-bit byte address allows
access within a 256-byte memory address-space.
After receipt of the byte address, the device again
responds with an acknowledge bit.

Byte Write

In the Byte Write mode, the master sends one data
byte, which is acknowledge d by the memory, as
shown in Figure 6. The master then terminates the
transfer by generating a STOP condition. The
Write mode is independent of the state of the
MODE p in,

as shown in Table 5, which could be
left floating if only this mode is to be used. Howev­er this is not a recommended operating mode , as
this pin has to be connected to either V

or VIL to

IH

minimize the stand-by current.

Multibyte Write

For the Multibyte Write mode, the MODE pin must
be held at V

as shown in Table 5. The Multibyte

IH,

Write mode can be started from any address in the
memory. The master sends one, two, three or four
bytes of data, which are each acknowledged by
the memory. The transfer is terminated by the
master generating a STOP condition. The maxi­mum duration of the write cycle is t

=10 ms (as

W

shown in Table 8), except when bytes span across
two rows. (That is, when they have different values
for the 6 most significant address bits, A7-A2). The
programming time is th en doubled to a maximum
of 20 ms. Writing more than four bytes in the Multi-

Figure 6. Wri te Mo de S e qu e nces

BYTE WRITE DEV SEL BYTE ADDR DATA IN

PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2

ACK ACK ACK

R/W

START

ACK

R/W

START

ACK ACK

DATA IN N

STOP

ACK ACK

STOP

AI01941

5/12

ST14C02C

Table 5. Operating Modes

Mode RW bit

Current Address Read ‘1’ X 1 START, Device Select, RW

‘0’ X START, Device Select, RW

Random Address Read

‘1’ X 1 reSTART, Device Select, RW
Sequential Read ‘1’ X ≥ 1 Similar to Current or Random Mode
Byte Write ‘0’ X 1 START, Device Select, RW

MODE

1

Bytes Initial Sequence

= ‘1’
= ‘0’, Address

= ‘1’

= ‘0’
Multibyte Write ‘0’ V
Page Write ‘0’ V

Note: 1. X = V

IH

or V

.

IL

IH

IL

byte Write mode may modify data bytes in an ad­jacent row. (Each row is 8 bytes long). However,
the Multibyte Write can properly write u p to eight
consecutive bytes only if the first address is the
first address of the row (the seven following bytes
thereby being written to the seve n follo wing bytes
of this same row).

When not connected, the MODE pin is internally

pulled to “1” and the multibyte write option is s e­lected.

Page Write

For the Page Write mode, the M ODE p in m ust be
held at V

(as shown in Table 5). The Page Write

IL

mode allows up to eight bytes to be written in a sin­gle write cycle, provided that they are all located in
the same row. That is, the five most significant
memory address bits (A7-A 3) must be the same.
The master sends between one and eight bytes of
data, each of which are acknowledged by the
memory. After each byte is transferred, the inter­nal byte address counter is incremented (this han­dles the three least significant address bits). Care
must be taken to avoid address counter ‘roll-over’,
as this could result in data being overwritten.

The transfer is terminated by the master generat­ing a STOP condition. For any write mode, the
generation by the master of the STOP condition
starts the internal memory program cycle. All in­puts are disabled until the completion of this cycle
and the memory will not respond to any request.

Minimizing System Delays by Polling On ACK

During the internal write cycle, the memory discon­nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi­mum write t ime ( t

) is indicated in Table 8, but the

w

typical time is shorter. To make use of this, an ACK
polling sequence can be used by the master.

≤ 4 START, Device Select, RW = ‘0’
≤ 8 START, Device Select, RW = ‘0’

The sequence, as shown in Figure 7, is as follows:
– Initial condition: a Write is in progress.
– Step 1: the m aster issues a ST ART condition

followed by a device select byte (first byte of the
new instruction).

– Step 2: if the memory is busy with the internal

write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it responds
with an ACK, indicating that the memory is
ready to receive the second part of the next in­struction (the first byte of this instruction having
been sent during Step 1).

Read Operations

Read operations are inde pendent of the state of
the MODE pin. On delivery, the memory content is
set at all “1’s” (FFh).

Current Address Read

The memory has an internal byte address counter.
Each time a byte is read, this counter is increment­ed. For the Current Address Read mode, following
a START condition, the master sends a device se­lect with the RW

bit set to ‘1’. The memory device
acknowledges this, and outputs the byte ad­dressed by the internal by te address counter, as
shown in Figure 9. The counter is then increment­ed. The master must

not

acknowledge the byte
output, and terminates t he transfer with a STOP
condition.

Random Address Read

A dummy write is performed to load the address
into the address counter, as shown in Figure 6.
This is followed by another START condition from
the master and the device selec t is repeated with
the RW

bit set to ‘1’. The memory device acknowl-

edges this, and outputs the by te addressed. The

not

master must

acknowledge the byte output, and

terminates the transfer with a STOP condition.

6/12

Figure 7. Wri te Cy cle Pol l in g Fl owchart usin g A C K

WRITE Cycle

in Progress

START Condition

DEVICE SELECT

with RW = 0

ACK

NO

Returned

ST14C02C

First byte of instruction
with RW = 0 already
decoded by ST14C02C

Next

Operation is

Addressing the

Memory

ReSTART

STOP

Table 6. AC Measurement Conditions

Input Rise and Fall Times ≤ 20 ns

0.2V

0.3V

to 0.8V

CC

to 0.7V

CC

Input Pulse Voltages
Input and Output Timing

Reference Voltages

YES

YESNO

Proceed

WRITE Operation

CC

CC

Send

Byte Address

Proceed

Random Address

READ Operation

AI02454

Figure 8. AC Testing Input/Output Waveform

0.8V

0.2V

CC

CC

0.7V

0.3V

AI00825

CC

CC

Table 7. Capacitance 1 (TA = 25 °C, f = 100 kHz)

Symbol Parameter Test Condition Min. Max. Unit

C

IN

C

IN

t

NS

Note: 1. Sampled only, not 100% tested.

Input Capacitance (SDA) 8 pF
Input Capacitance (other pins) 6 pF
Noise suppression Time Con-

stant (SCL & SDA Inputs)

100 400 ns

7/12

ST14C02C

Figure 9. Read Mode Sequences

CURRENT
ADDRESS
READ

RANDOM
ADDRESS
READ

SEQUENTIAL
CURRENT
READ

SEQUENTIAL
RANDOM
READ

ACK

DEV SEL DATA OUT

R/W

START

ACK

DEV SEL * BYTE ADDR

R/W

START

ACK ACK ACK NO ACK

DEV SEL DATA OUT 1

R/W

START

ACK ACK

DEV SEL * BYTE ADDR

NO ACK

STOP

ACK ACK

DEV SEL * DATA OUT

START

DEV SEL * DATA OUT 1

NO ACK

R/W

DATA OUT N

ACK ACK

STOP

STOP

R/W

START

ACK NO ACK

DATA OUT N

Sequenti a l Rea d

This mode can be initiated with either a Current
Address Read or a Random A ddress Read. How­ever, in this case the master

does

acknowledge
the data byte output, and the memory continues to
output the next byte in sequence. To terminate the

not

stream of bytes, the master must
the last byte ou tput, and

must

acknowledge

generate a STOP
condition. The output data comes from consecu­tive byte addresses, with the internal byte address
counter automatically incremented after each byte
output. After the last memory address, the address

counter will ‘roll -ove r’ and the me mor y will c ontin ­ue to output data from the start of the memory
block.

R/W

START

STOP

AI01942

Acknowledge in Read Mode

In all read modes the memory waits for an ac­knowledgment during the 9

th

bit time. If the master
does not pull the SDA line l ow during this time, the
memory device terminates the data transfer and
switches to its standby state.

8/12

ST14C02C

Table 8. AC Characteristics

(T

= 0 to 70 °C; VCC = 3V to 5.5V)

A

Symbol Alt. Parameter

t

CH1CH2

t

CL1CL2

t

DH1DH2

t

DL1DL2

1

t

CHDX

t

CHCL

t

DLCL

t

CLDX

t

CLCH

t

DXCX

t

CHDH

t

DHDL

t

CLQV

t

CLQX

f

C

2

t

W

Note: 1. For a r eS T ART condi tion, or foll owing a write cycle.

2. In the Multiby te Write m ode onl y, if the ac cessed b ytes sp an over t wo conse cutive 8- byte row s (that i s, if the 6 m ost signif icant
address bi ts are not constant) the max i m um programming time is doubled to 20 ms

t

R

t

F

t

R

t

F

t

SU:STA

t

HIGH

t

HD:STA

t

HD:DAT

t

LOW

t

SU:DAT

t

SU:STO

t

BUF

t

AA

t

DH

f

SCL

t

WR

Clock Rise Time 1 µs

Clock Fall Time 300 ns
SDA Rise Time 1 µs
SDA Fall Time 300 ns
Clock High to Input Transition 4.7 µs
Clock Pulse Width High 4 µs
Input Low to Clock Low (START) 4 µs
Clock Low to Input Transition 0 µs
Clock Pulse Width Low 4.7 µs
Input Transition to Clock Transition 250 ns
Clock High to Input High (STOP) 4.0 µs
Input High to Input Low (Bus Free) 4.7 µs
Clock Low to Data Out Valid 3.5 µs
Data Out Hold Time After Clock Low 300 ns
Clock Frequency 100 kHz
Write Time 10 ms

ST14C02C

Min Max

Unit

Table 9. DC Characteristics

= 0 to 70 °C; VCC = 3V to 5.5V)

(T

A

Symbol Parameter Test Condition Min. Max. Unit

I

LI

I

LI

I

LO

I

CC

I

CC1

V

IL

V

IH

V

IL

V

IH

V

OL

Input Leakage Current

Input Leakage Current (MODE pad)
Output Leakage Current

Supply Current

Supply Current (Stand-by) V

0V ≤ V

0V ≤ V

0V ≤ V

OUT

= 5 V, fc = 100 kHz

V

CC

(Rise/Fall time < 10 ns)

= VSS or V

IN

Input Low Voltage (SCL, SDA) - 0.3 0.3 V
Input High Voltage (SCL, SDA) 0.7 V
Input Low Voltage (MODE) - 0.3 0.5 V
Input High Voltage (MODE)
Output Low Voltage IOL = 3 mA, VCC = 5 V 0.4 V

≤ V

≤ V

IN

CC

≤ V

IN

CC

SDA in Hi-Z

CC,

, V

CC

CC

± 2 µA

± 10 µA

± 2 µA

2mA

= 5 V 100 µA

CC

VCC + 1 V

CC

V

- 0.5 VCC + 1

CC

V

V

9/12

ST14C02C

Figure 10. AC Waveforms

SCL

SDA IN

SCL

SDA OUT

SCL

tCHCL

tDLCL

tCHDX

START

CONDITION

tCLQV tCLQX

tCLDX

SDA

INPUT

DATA VALID

DATA OUTPUT

SDA

CHANGE

tW

tCLCH

tDXCX

tCHDH

tDHDL

STOP &

BUS FREE

SDA IN

tCHDH

STOP

CONDITION

ORDERING INFORMATION

Devices are shipped from the factory with the

memory content set at all ‘1’s (FFh).
The notation used for the device number is as

shown in Table 10. For a list of available options
(speed, package, etc...) or for further information
on any aspect of this device, please contact the ST
Sales Office nearest to you.

Sawn wafers are scribed an d m ount ed in a frame
on adhesive tape. The orientation is defined by the
position of the GND pad on the die, viewed with
active area of product visible, relative to the notch-

tCHDX

WRITE CYCLE

START

CONDITION

AI00795B

es of the frame (as shown in Figure 11). The orien­tation of the die with respect t o the plastic frame
notches is specified by the Customer.

One further concern, when specify ing devices to
be delivered in this form, is that wafers mounted
on adhesive tape must be used within a limited pe­riod from the mounting date:

– two months, if wafers are stored a t 25°C, 55%

relative h umidity

– six months, if wafers are stored at 4°C, 55% rel-

ative humidity

10/12

Table 10. Ordering Information Scheme

Example: ST14C02C - D20

where “x” indicates the sawing orientation, as follows (and as shown in Figure 11)

ST14C02C

Delivery Form

D15 Module on Super 35 mm film
D20 Module on Super 35 mm film
W2 Unsawn wafer (275 µm ± 25 µm thickness)

W4 Unsawn wafer (180 µm ± 15 µm thickness)

S2x Sawn wafer (275 µm ± 25 µm thickness)
S4x Sawn wafer (180 µm ± 15 µm thickness)

1 GND at top right
2 GND at bottom right
3 GND at bottom left
4 GND at top left

Figure 11. Sawing Orientation

GND

1ORIENTATION

VIEW: WAFER FRONT SIDE

GND

GND GND

234

AI02171

11/12

ST14C02C

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to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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