SGS Thomson Microelectronics ST14C02C Datasheet

2 Kbit (256 x 8) Serial I2C Bus EEPROM

■ Single Supply Voltage (3 V to 5.5 V)

C bus.

2

C Serial Interface

2

C standard.

2

C bus

■ Two Wire I

■ BYTE and MULTBYTE WRITE (up to 4 Bytes)

■ PAGE WRIT E (up to 8 Bytes )

■ BYTE, RANDOM and SEQUENTIAL READ

Modes

■ Self-Tim e d P ro g r amming Cycle

■ Automatic Address Incrementing

■ Enhanced ESD/Latch-Up Behavior

■ 1 Million Erase/Write Cycles (minimum)

■ 10 Year Data Retention (minimum)

DESCRIPTION

This device is an electrically erasable programma­ble memory (EEPROM) fabricated with

STMicroelectronics’s High Endurance, Advanced
Polysilicon, CMOS technology. This guarantees
an endurance typically well above one million
Erase/Write cycles, with a data retention of 10
years. The memory operates with a power supply
as low as 3 V.

The device is available in wafer form (either sawn
or unsawn) and in micromodule form (on film).

The memory is compatible with the I
This is a two wire serial interface that uses a bi-di­rectional data bus and serial clock. The me mory
carries a built-in 7-bit unique Device Type Identifi­er code (1010000) in accordance with the I
definition. Only one memory can be attached to

2

each I

Memory Card IC

Micromodule (D15)

Wafer

Figure 1. Logic Diagram

V

CC

ST14C02C

2

2

Micromodule (D20)

2

2

Table 1. Signal Names

SDA Serial Data/Address Input/

Output
SCL Serial Clock
MODE Write Mode
V

CC

GND Ground

Supply Voltage

SCL

MODE

ST14C02C

GND

SDA

AI01162

1/12DS.ST14C02C/9811V2

ST14C02C

Figure 2. D15 Contact Connections

V

CC

SCL

GND

SDA

AI02492

The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and write o perations are
initiated by a START condition, gene rated by the
bus master. The STA RT condition is followed by
the Device Select Code which is compos ed of a
stream of 7 bits (1010000), plus one read/write bit
(R/W

) and is terminated by an acknowledge bit.

When writing data to the memory, the mem ory in­serts an acknowledge bit during the 9

th

bit time,

following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af­ter a NoACK for READ.

Figure 3. D20 Contact Connections

V

CC

SCL

GND

SDA

MODE

AI02491

Power On Reset: VCC Lock-Out Write Protect

In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re­set (POR) circuit is included. The internal reset is
held active until the V

voltage has reached the

CC

POR threshold value, and all operations are dis­abled – the device will not respond to any com­mand. In the same way, when V

drops from the

CC

operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any com ma nd. A s table a nd v alid V

CC

must be applied before applying any logic signal.

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

V

IO

V

CC

V

ESD

Note: 1. Exc ept for the rating “Operating Temperature Ra nge”, stresses above those li sted in t he Table “A bsolute Maximum Ratings” m ay

2/12

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indi cated in t he Operating sect i ons of thi s specif i cation is not imp l i ed. Exposure to Absolute M aximum Rating condi­tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL -STD-883C, 3015.7 (1 00 pF, 1500 Ω)

3. EIA J I C-121 (Condition C) (200 pF, 0 Ω)

Ambient Operating Temperature 0 to 70 °C

Storage Temperature

Input or Output range -0.3 to 6.5 V
Supply Voltage -0.3 to 6.5 V

Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

1

Wafer form
Module form

2

3

-65 to 150

-40 to 120

4000 V

500 V

°C

Table 3. Endurance and Data Retention

Device Endurance (Erase/Write Cycles) Data Retention (Years)

ST14C02C 1,000,000 10

ST14C02C

SIGNAL DESCRIPTION
Serial Clock (SCL)

The SCL input pin is used to sync hronize all data
in and out of the memory. A pull up resistor can be
connected from the SCL line to V

. (Figure 4 in-

CC

dicates how the value of the pull-up resistor can be
calculated).

Serial Data (SDA)

The SDA pin is bi-directional, and is used to trans­fer data in or out of the memory. It is an open drain

output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to V

. (Figure 4 indicates how the value of the

CC

pull-up resistor can be calculated).

Mode (MOD E )

The MODE input may be driven dynamically. It
mus t be held at:

■ V

or VIH for the Byte Write mode

IL

■ V

for Multibyte Write mode

IH

■ V

for Page Write mode

IL

When unconnected, the MODE input is internally
read as a V

(Multibyte Write mode). Note that the

IH

voltages are CMOS levels, and are not TTL com­patible.

On the D15 micromodule, the MODE pin is not
connected to a contact. T his pin is left f loating on
the silicon. This type of ST14C02C is always in its
MultiByte mode, and cannot be changed from this.

DEVICE OPERATION

2

The memory device supports the I

C protocol, as
summarized in Figure 5. Any device that sends
data on to the bus is defined to be a transmitte r,
and any device that reads the data to be a receiv­er. The device that controls the data transfer is
known as the mast er, and the other as the slave.
A data transfer can only be initiated by the master,
which will also provide the serial clock for synchro­nization. The memory device is always a slave de­vice in all communication.

Figure 4. Maximum RL Value versus Bus Capacitance (C

20

16

12

max (kΩ)

L

R

8

4

0

VCC = 5V

100 200 300 400

C

(pF)

BUS

) for an I2C Bus

BUS

V

CC

SDA

MASTER

SCL

R

R

BUS

L

C

BUS

AI01100

3/12

L

C

ST14C02C

Figure 5. I2C Bus Protocol

SCL

SDA

SCL

SDA

SCL

SDA

START

CONDITION

START

CONDITION

SDA

INPUT

1 23 789

MSB

1 23 789

MSB ACK

SDA

CHANGE

CONDITION

ACK

STOP

STOP

CONDITION

AI00792

Start Condition

START is identified by a high t o low transition of
the SDA line while the clock, SCL, is s table i n t he
high state. A START condition must precede any
data transfer command. The memory continuously
monitors (except during a programming cycle) the
SDA and SCL lines for a START condition, and will
not respond unless one is given.

Stop Condition

STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high

Table 4. Device Select Code

b7 b6 b5 b4 b3 b2 b1 b0

Device Select 1010000RW

Note: 1. The most significant bit, b 7, is sent first.

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1

state. A STO P condition terminates c ommunica­tion between the memory an d the bus master. A
STOP condition at the end of a Read command
forces the memory device into its standby state. A
STOP condition at the end of a Write com mand
triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a suc­cessful data transfer. The bus transmitter, either
master or slave, will release the SDA bus after
sending 8 bits of data. During t he 9

Device Code RW

th

clock pulse