SGS Thomson Microelectronics M40SZ100Y, M40SZ100W Datasheet
5V or 3V NVRAM SUPERVISOR FOR LPSRAM
FEATURES SUMMARY
■ CONVERT LOW POWER SRAMs INTO
NVRAMs
■ 5V OR 3V OPERATING VOLTAGE
■ PRECISION POWER MONITORING and
POWER SWITCHING CIRCUITRY
■ AUTOMATIC WRITE-PROTECTION WHEN
V
IS OUT - OF-TOLERANC E
CC
■ CHOICE OF SUPPLY VOLTAGES and
POWER-FAIL DESELECT VOLTAGES:
– M40SZ100Y : V
4.20V ≤ V
PFD
– M40SZ100W: V
2.55V ≤ V
■ RESET OUTPUT (RST) FOR POWER ON
PFD
RESET
■ 1.25V REFERENCE (for PFI/PFO)
■ LESS THAN 10ns CHIP ENABLE ACCESS
PROPAGATION DELAY (at 5V)
■ OPTIONAL PACKA GING INCLUDES A 28-
LEAD SOIC and SNAPHAT
ordered separately)
■ 28-LEAD SOIC PAC KAG E PROVIDES
DIRECT CONNECTION FOR A SNAPHAT
TOP WHICH CONTAINS THE BATTERY
■ BATTERY LOW PIN (BL)
= 4.5 to 5.5V;
CC
≤ 4.50V
= 2.7 to 3.6V;
CC
≤ 2.70V
®
TOP (to be
M40SZ100Y
M40SZ100W
Figure 1. 16-pi n S O I C Package
16
1
SO16 (MQ)
Figure 2. 28-pi n S O I C Package*
SNAPHAT (SH)
Battery
28
1
SOH28 (MH)
* Contact Local Sales Office
Rev. 1.3
1/19September 2003
M40SZ100Y, M40SZ100W
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic Diagram (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
SOIC16 Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SOIC28 Connections (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Hardware Hookup (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC and AC Measurement Conditions (Table 3.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AC Testing Load Circuit (Figure 8.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AC Testing Input/Output Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Retention Lifetime Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Power Down Timing (Figure 10.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Up Timing (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Down/Up AC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-on Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset Input (RSTIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
RSTIN Timing Waveform (Figure 12.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reset AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Battery Low Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-fail Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CC
Supply Voltage Protection (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SNAPHAT® Battery Table (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
SUMMARY DESCRIPTION
The M40SZ100Y/W NVRAM Controller is a selfcontained device which converts a standard lowpower SRAM into a non-volatile mem ory. A prec ision voltage reference and comparator monitors
the V
When an invalid V
tioned chip enable output (E
input for an out-of-tolerance condition.
CC
condition occurs, t he condi-
CC
) is forced inactive
CON
to write protect the stored data in the SRAM. During a power failure, the SRAM is switched from the
pin to the lithium cell within the SNAPHAT (or
V
CC
external battery for the 16-lead S OIC) to provide
the energy required for data retention. On a subsequent power-up, the SRAM remains write protected until a valid power condition returns.
The 28-pin, 330 mil SOIC provides soc kets with
gold plated contacts for direct connection to a separate SNAPHAT
®
housing containing the battery.
The SNAPHAT housing has gold plated pins
which mate with the sockets, ensuring reliable
connection. The housing is keyed to prevent improper insertion. This unique design allows the
SNAPHAT battery p acka ge t o be m ount ed o n t op
M40SZ100Y, M40SZ100W
of the SOIC package after the c ompletion of the
surface mount process which greatly reduces the
board manufacturing process complexity of either
directly soldering or inserting a battery into a soldered holder. Providing non-volatility becomes a
“SNAP.” This feature is also a vailable in the “topless” 16-pin SOIC package (MQ).
Insertion of the SNAPHAT housing after reflow
prevents potential battery damage due to the high
temperatures required for device surface-moun ting. The SNAPHA T housing is also k eyed to prevent reverse insertion.
The 28-pin SOIC and battery packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 2 8-lead SOIC, t he ba ttery/crystal package (e.g., SNAPHAT) part number is “M4ZXX-BR00SH” (see Table 13, page 17).
Caution: Do not place the SNAPHAT battery top
in conductive foam, as this will drain the lithium
button-cell battery.
Figure 3. Logic Diagram
V
V
E
PFI
RSTIN
Note: 1. For 16-pin SOIC pac kage only.
M40SZ100Y
M40SZ100W
V
CC
SS
BAT
(1)
V
OUT
BL
E
CON
PFO
RST
AI03933
Table 1. Signal Names
E Chip Enable Input
E
CON
RST
RSTIN
BL
V
OUT
V
CC
(1)
V
BAT
PFI Power Fail Input
PFO
V
SS
NC Not Connected Internally
Note: 1. For SO1 6 onl y.
Conditioned Chip Enable Output
Reset Output (Open Drain)
Reset Input
Battery Low Output (Open Drain)
Supply Voltage Output
Supply Voltage
Back-up Supply Voltage
Power Fail Output
Ground
3/19
M40SZ100Y, M40SZ100W
Figure 4. SOI C 16 Connection s
NC
NC
RST
NC
RSTIN
PFO
V
BAT
V
SS
Note: 1. DU = Do Not Use
1
2
3
4
M40SZ100Y
M40SZ100W
5
6
710
8
16
15
14
13
12
11
Figure 5. SOI C 28 Connection s
1
BL
NC
V
CC
NC
V
OUT
NC
PFI
BL
E
E
9
CON
AI03935
NC
NC
NC
NC
NC
NC
RSTIN
NC
NC
PFO
V
SS
2
3
4
5
6
7
M40SZ100Y
M40SZ100W
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI03934
V
CC
NC
NC
V
OUT
NC
NC
PFI
NC
E
NC
RST
NCNC
NC
E
CON
Figure 6. Block Diagram
V
CC
V
BAT
RSTIN
E
PFI
1.25V
Note: Open dra i n output
VBL= 2.5V
V
= 2.5V
SO
V
= 4.4V
PFD
COMPARE
COMPARE
COMP ARE
(2.65V for SZ100W)
COMPARE
POR
V
OUT
(1)
BL
RST
E
CON
PFO
AI04766
(1)
4/19
Figure 7. Hardware Hookup
M40SZ100Y, M40SZ100W
3.0V, 3.3V or 5V
Unregulated
Voltage
R1
R2
Note: 1. User supplied for the 16-pin pa ck age
Regulator
V
IN
From Microprocessor
V
CC
0.1µF
V
CC
E
RSTIN
PFI
V
SS
V
BAT
V
OUT
M40SZ100Y
M40SZ100W
E
CON
PFO
(1)
RST
BL
V
CC
0.1µF
To Microprocessor NMI
To Microprocessor Reset
To Battery Monitor Circuit
1Mb or 4Mb
LPSRAM
E
AI04767
MAXIMUM RATI N G
Stressing the device ab ove the rating listed in t he
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the dev ice at
these or any other conditions above those indicat-
not implied. Exposure to Absol ute Maxim um Ra ting conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics SURE Program and other relevant quality documents.
ed in the Operating sections of this specification is
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
STG
(1)
T
SLD
V
IO
V
CC
I
O
P
D
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to ex ceed 180°C for between 90 to 120
secon ds).
CAUTION: Negative und ershoots below –0.3V are not allowed on any pin while in the Battery Ba ck-up mod e.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAP HAT sock ets.
Storage Temperature (VCC Off)
Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltages
Supply Voltage
Output Current 20 mA
Power Dissipation 1 W
SNAPHAT –40 to 85 °C
SOIC –55 to 125 °C
–0.3 to V
CC
+0.3
M40SZ100Y –0.3 to 7 V
M40SZ100W –0.3 to 4.6 V
V
5/19
M40SZ100Y, M40SZ100W
DC AND AC PARAMETERS
This section summarizes the operat ing and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the M easure-
Table 3. DC and AC Measurement Conditions
Parameter M40SZ100Y M40SZ100W
Supply Voltage
V
CC
Ambient Operating Temperature –40 to 85°C –40 to 85°C
ment Conditions listed in the rel evant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
4.5 to 5.5V 2.7 to 3.6V
Load Capacitance (C
)
L
100pF 50pF
Input Rise and Fall Times ≤ 5ns ≤ 5ns
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Figure 8. AC Testing Load Circuit
DEVICE
UNDER
TEST
CL includes JIG capacitance
333Ω
CL = 100pF
or 50pF
1.73V
AI02393
0.2 to 0.8V
0.3 to 0.7V
CC
CC
Figure 9. AC Testing Input/Output Waveforms
0.8V
CC
0.2V
CC
0.2 to 0.8V
0.3 to 0.7V
CC
CC
0.7V
0.3V
AI02568
CC
CC
Note: 1. CL = 100pF for M40SZ100Y and 50pF for M40SZ100W.
Table 4. Capacitance
Symbol
C
IN
C
OUT
Note: 1. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outpu ts deselected
Input Capacitance 7 pF
(3)
Output Capacitance 10 pF
6/19
Parameter
(1,2)
Min Max Unit
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