SGS Thomson Microelectronics M39208 Datasheet

M39208

Single Chip 2 Mbit Flash and 64 Kbit Parallel EEPROM Memory

PRELIMINARY DATA

2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPARATIONS

100ns ACCESS TIME
(Flash and EEPROM blocks)

WRITE, PROGRAM and ERASE STATUS BITS
CONCURRENT MODE (Read Flash while

writing to EEPROM)
100,000 ERASE/WRITE CYCLES
10 YEARS DA TA RETE NT ION
LOW POWER CONSUMPTION
– Stand-by mode: 60µA
– Automatic Stand-by mode
– Deep Power Down mode
64 bytes ONE TIME PROGRAMMABLE

MEMORY
ST A NDA RD EPRO M /OTP MEMORY

P ACKAGE
EXTENDED TEMPERATURE RANGES

TSOP32 (NA)

8 x 20 mm

Figure 1. Logic Diagram

TSOP32 (NB)

8 x 14 mm

DESCRIPTION

The M39208 is a memory device combining Flash
and EEPROM into a single chip and using single
supply voltage. The memory is mapped in two
blocks: 2 Mbit of Flash memory and 64 Kbit of
EEPROM memory. Each space is independant for
writing, in concurrent mode the Flash Memory can
be read while the EEPROM is being written.

T ab le 1. Signal Names

A0-A17 Address Inputs
DQ0-DQ7 Data Input / Outputs
EE EEPROM Block Enable
EF Flash Block Enable
G Output Enable
W Write Enable
V

CC

V

SS

Supply Voltage
Ground

A0-A17

W

EE

EF

V

CC

18

M39208

G

V

SS

8

DQ0-DQ7

AI02589

February 1999 1/30

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change with out not i ce.

M39208

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

BIAS

T

STG

(2)

V

IO

V

CC

, VG, V

V

A9

Notes:

EF

1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to t he STMicroelectroni cs SURE Pro gr am and other
relevant quality documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

Ambient Operating Temperature –40 to 85
Temperature Under Bias –50 to 125
Storage Temperature –65 to 150
Input or Output Voltages –0.6 to 5 V
Supply Voltage –0.6 to 5 V

(2)

A9, G, EF Voltage –0.6 to 13.5 V

Figure 2. TSOP Pin Connections

(1)

of the data can be secured with the help of the
Software Data Protection (SDP).

The M39208 Flash Memory block offers 4 sectors
of 64 Kbytes, each sector may be erased individu­ally, and programmed Byte-by-Byte. Each sector

A11

A9 A10

A8 EF
A13
A14
A17

V

CC

EE
A16
A15
A12

A7
A6 A1
A5 A2
A4

1

W

8
9

16 17

M39208

32

25
24

AI02587

G

DQ7
DQ6
DQ5
DQ4
DQ3
V

SS

DQ2
DQ1
DQ0
A0

A3

can be separately protected and unprotected
against program and erase. Sector erasure may be
suspended, while data is read from other sectors
of the Flash memory block (or EEPROM memory
block), and then resumed.

During a Program or Erase cycle in the Flash
memory block or during a Write in the EEPROM
memory block, the status of the M39208 internal
logic can be read on the Data Outputs DQ7,DQ6,
DQ5 and DQ3.

PIN DESCRIPTION
Address Inputs (A0-A17).

The address inputs for
the memory array are latched during a write opera­tion. A0-A12 access locations in the EEPROM
memory block A0-A17 access locations in the Flash
memory block. The memory block selected is given
by the state on the

When a specific voltage (V

EE and EF inputs r espectively.

) is applied on the A9

ID

address input, additional specific areas can be
accessed: Read the Manufacturer identifier, Read
the Flash block identifier, Read/Write the EEPROM
block identifier, Verify the Flash Sector Protection
Status.

DESCRIPTION

An additional 64 bytes of EPROM are One Time
Programmable.

The M39208 EEPROM memory block may be writ­ten by byte or by page of 64 bytes and the integrity

(Cont’d)

Data Input/Out put (DQ0-DQ7) .

inputs one byte which is latched when
and Write Enable

W are driven active.

Data read is valid when one Chip Enable (Chip
Enable Flash or Chip Enable EEPROM) and Out­put Enable are driven active. The out put is high

C

°

C

°

C

°

A write operation

EE (or EF)

2/30

Figure 3. Flash Block Sectors

M39208

A17

AI02588

impedance when the chip is deselected (both

EF driven high) or the outputs are disabled (G

and

A16

1

1

0

0

1

0

1

0

64K Bytes Block

64K Bytes Block

EE

driven high).
Read operations are used to output the contents

from the memory, the Manufacturer identifier, the
Flash Sector protection Status, the Flash block
Identifier, the EEPROM identifier or the OTP row
content.

Memory Block Enable (

Block Enable (

EE or EF) activates the memory

EE and EF).

The Memo ry

control logic, input buffers, decoders and sense
amplifiers. When the

EE input is driven high, the
EEPROM memory block is not selected; when the
EF input is driven high, the Flash memory block is
not selected. Attempts to access both EEPROM
and Flash blocks (

EE low and EF low) are forbid­den. Switching between the two memory block
enables (
same clock cycle, a delay of greater than t

EE and EF) must not be made on the

must

EHFL

be inserted.
The M39208 is in standby when both

EF and EE
are High (when no internal Erase or programming
is running). The power consumption is reduced to
the standby level and the outputs are in the high
impedance state, independent of the Output En-

G or Write Enable W inputs.

able
After 150ns of inactivity and when the addresses

are driven at CMOS levels, the chip automatically
enters a pseudo standby mode where consumption
is reduced to the CMOS standby value, while the
outputs continue to drive the bus.

The Output Enable gates the

Output Enable (

G).

outputs through the data buffers during a read
operation. The data outputs are in the high imped­ance state when the Output Enable

G is High.

TOP

ADDRESS

3FFFFh

2FFFFh

1FFFFh

0FFFFh

BOTTOM

ADDRESS

30000h

20000h

10000h

00000h

During Sector Protect and Sector Unprotect opera­tions, the

G input must be forced to VID level (12V

+ 0.5V) (for Flash memory block only).

Addresses are latched on the

Write Enable (

falling edge of
the rising edge of

W).

W, and Data Inputs are latched on

W.

OPERATIONS

The M39208 memory is addressed through 18
inputs A0-A17 and provides data on eight Data
Inputs/Outputs DQ0-DQ7 with the help of four con­trol lines: Chip Enable EEPROM (
Flash (
(

EF), Output Enable (E) and Write Enable

W) inputs.

EE), Chip Enable

An operation is defined as the basic decoding of
the logic level applied to the control input pins (

EF,
EE, G, W) and the specified voltages applied on
the relevant address pins. These operat ions are
detailed in Table 3.

Read.

is

Both Chip Enable and Output Enable (that

EF and G or EE and G) must be low in order to

read the output of the memory.
Read operations are used to output the contents

from the Flash or EEPROM block , the Manufac­turer identifier, the Flash Sector protection Status,
the Flash block Identifier, the EEPROM identifier or
the OTP row content.

Notes:
– The Chip Enable input mainly provides power

control and should be used for device selection.
The Output Enable input should be used to gate
data onto the output in combination with active
EF or EE input signals.

– The data read depends on the previous instruc-

tion entered into the memory (see Table 4).

3/30

M39208

Table 3. Basic Operations

Operation EF EE G W DQ0 - DQ7

V

Read

Write

Output Disable

Standby V

Note:

X = V

or VIH.

IL

A W rite operation can be used for two goals:

Write.

IL

V

IH

V

IL

V

IH

V

IL

V

IH

IH

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

– either write data in the EEPROM memory block
– or enter a sequence of bytes composing an

instruction.

The reader should note that Programming a Flash
byte is an instruction (see Instructions paragraph).

Writing data requires:
– the Chip Enable (either
– the Write Enable (

EE or EF) to be Low

W) to be Low with Output

Enable (G) High.

Addresses in Flash block (or EEPROM block) are
latched on the falling edge of

W or EF (EE) which­ever occurs last; the data to be written in Flash
block (EEPROM block) is latched on the rising edge

W or EF (EE) whichever occurs first.

of

Specific Read and Write Operations.

Device
specific data is accessed through operations de­coding the V

level applied on A9 ( VID = 12V +

ID

0.5V) and the logic levels applied on address inputs
(A0, A1, A6). These specific operations are:

– Read the Manufacturer identifier
– Read the Device identifier
– Define the Flash Sector protection
– Read the EEPROM identifier
– Write the EEPROM identifier
Note: The OTP row (64 bytes) is acc es sed with a

specific software sequence detailed in the para­graph "Write in OTP row".

Instructions

An instruction is defined as a sequence of specific
Write operations. Each received byte is sequen­tially decoded (and not executed as standard Write
operations) and the instruction is executed when

V

IL

V

IL

V

IH

V

IH

V

IH

V

IH

XX Hi-Z

V

IH

V

IH

V

IL

V

IL

XHi-Z
XHi-Z

Read in Flash Block

Read in EEPROM Block

Write in Flash Block

Write in EEPROM Block

the correct number of bytes are properly received
and the time between two consecutive bytes is
shorter than the time-out value.

The sequencing of any instruction must be followed
exactly , any invalid combination of instruction bytes
or time-out between two consecutive bytes will
reset the device logic into a Read memory state
(when addressing the Flash block) or directly de­coded as a single operation when addressing the
EEPROM block.

The M39208 set of instructions includes:
– Program a byte in the Flash block
– Read a Flash sector protection status
– Erase instructions: Flash Sector Erase, Flash

Block Erase, Flash Sector Erase Suspend, Flash

Sector Erase Resume
– EEPROM power down
– Deep power down
– Set/Reset the EEPROM software writ e protec-

tion (SDP)
– OTP row access
– Reset and Return
– Read identifiers: read the manufacturer identi-

fier, Read the Flash block identifier
These instructions are detailed in Table 4.
For efficient decoding of the instruction, the two first

bytes of an instruction are the coded cycles and are
followed by a command byte or a confirmation byte.
The coded cycles consist of writing the data AAh at
address 5555h during the first cycle and data 55h
at address 2AAAh during the second cycle.

In the specific case of the Erase instruction, the
instruction expects confirmation by two additional
coded cycles.

4/30

M39208

T able 4. Instructions

(1)

Instruction EE EF Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7

Read

Read Manufacturer
Identifier

(2)

10

AAh

@5555h

55h

@2AAAh

90h
@5555h

Identifier

with

(A0,A1,A6)

at (0,0,0)

Read

Read Flash
Identifier

(2)

10

AAh

@5555h

55h

@2AAAh

90h
@5555h

identifier

with

(A0,A1,A6)

at (1,0,0)

Read OTP Row 0 1

AAh

@5555h

55h

@2AAAh

90h
@5555h

Read

byte 1

Read

byte 2

Read

Read Block
Protection Status

(2)

10

AAh

@5555h

55h

@2AAAh

90h
@5555h

Identifier

with

(A0,A1,A6)

at (0,1,0)

Program a Flash Byte 1 0

Erase one Flash
Block

10

Erase the Whole Flash 1 0

AAh

@5555h

AAh

@5555h

AAh

@5555h

55h

@2AAAh

55h

@2AAAh

55h

@2AAAh

A0h

@5555h

80h

@5555h

80h

@5555h

Data

@address

AAh

@5555h

AAh

@5555h

55h

@2AAAh

55h

@2AAAh

30h

@Sector

address

10h

@5555h

B0h

Suspend Block Erase 1 0

@any

address

30h

Resume Block Erase 1 0

@any

address

EEPROM Power
Down

01

Deep Power Down 1 0
SDP Enable

(EEPROM)
SDP Disable

(EEPROM)

01

01

Write in OTP Row 0 1
Return (from OTP

Read or EEPROM

01

Power Down)

Reset 1 0

Reset (short
instruction)

Notes:

1. AAh @5555h means Write byte AAh at address 5555h.

2. This instruction can also be performed as a simple Read operation with A9=V

3. Additional blocks to be erased must be entered within 80µs.

10

AAh

@5555h

20h

@5555h

AAh

@5555h

AAh

@5555h

AAh

@5555h

F0h @

any

address

AAh

@5555h

F0h

@any

address

55h

@2AAAh

55h

@2AAAh

55h

@2AAAh

55h

@2AAAh

55h

@2AAAh

30h

@5555h

A0h

@5555h

80h

@5555h

B0h

@5555h

F0h

@any

Address

Write

byte 1

AAh

@5555h

Write

byte 1

(refer to READ chapter).

ID

Write

byte 2

55h

@2AAAh

Write

byte 2

20h

@5555h

Read

byte N

30h

@Sector

address

Write

byte N

Write

byte N

(3)

5/30

M39208

T ab le 5. Device Identifiers

Identifier EF EE G WA0A1A6A9

Read the
Manufacturer
Identifier

Read the Flash
Block Identifier

Read the
EEPROM Block
Identifier

Note:

X = Don’t Care.

POWER SUPPLY and CURRENT CONSUMP­TION

EEPROM Power Down.

with the EEPROM in power down with the help of
the EEPROM power down instruction (see Table

4). Once the EEPROM power down instruction is
decoded, the EEPROM block cannot be ac ces sed
unless a further Return instruction is decoded.

Deep Power Down.

lowest I

consumption mode with the help of the

CC

Deep Power Down instruction (see Table 4). Once
the instruction is d ecoded, the device is set in a
sleep mode until a Reset instruction is decoded.

Power Up.

The M39208 internal logic is reset upon
a power-up condition to Read memory status. Any
Write operation in EEPROM is inhibited during the
first 5 ms following the power-up.

Either

EF, EE or W must be tied to VIH during
Power-up for the maximum security of the data
contents and to remove the possibility of a byte
being written on the first rising edge of
W. Any write cycle initiation is locked when Vcc is
below V

LKO

.

READ

Read operations and instructions can be used to:
– read the contents of the Memory Array (Flash

block and EEPROM block)

– read the Memory Array (Flash block and

V

V

V

V

IL

V

IL

V

IH

V

IH

V

IH

V

IL

V

IL

IL

IL

IH

V

IH

V

IH

The M39208 can be set

The M39208 can be set in the

EF, EE o r

V

V

V

IL

V

IH

XXVILV

V

IL

IL

IL

V

IL

Read data (Flash a nd EEPR OM bloc ks)

Both Chip Enable

G) must be low in order to read the data from the

(
memory.

Read the Manufacturer Identifier

The manufacturer’s identifier can be read with two
methods: a Read operation or a Read instruction.

Read Operation.

be read with a Read operation with specific logic
levels applied on A0, A1, A6 and the V
= 12V + 0.5V) on A9 (see Table 5).

Read Instruction.

can also be read with a single instruction composed
of 4 operations: 3 specific Write operations (see
Table 4) and a Read which outputs the Manufac­turer identifier, the Flash block identifier or the Flash
sector protection status.

Read the Flash Block Identifier

The Flash block identifier can be read with two
methods: a Read operation or a Read instruction.

Read Operation.

can be read with a single Read operation with
specific logic levels applied on A0, A1, A6 and the

level on A9 (see Table 5).

V

ID

Read Instruct ion.

also be read with an instruction composed of 4
operations: 3 specific Write operations and a Read
(see Table 4).

EEPROM block) status and identifiers.

Other

Addresses

V

ID

V

ID

ID

Don’t Care 20h

Don’t Care t.b.d.

Don’t Care

DQ0 - DQ7

64 bytes

user

defined

EF (or EE) and Output Enable

The manufacturer’s identifier can

level (V

ID

The manufacturer’s identifier

The Flash block identifier (t.b.d.)

The Flash block identifier can

ID

6/30

T able 6. Status Bit

EF EE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

M39208

Flash V

EEPROM V

Note:

X = Not guaranteed value, can be read either ’1’ or ’0’.

V

IL

V

IH

Data

IH

Polling

Data

IL

Polling

Toggle

Flag

Toggle

Flag

Read the EEPROM Block Identifier

The EEPROM block identifier (64 bytes, user de­fined) can be read with a single Read operation with
A6 = ’0’ and A9 = V

(see Table 5).

ID

Read the OTP Row

The OTP row is mapped in the EEPROM block

EE = ’0’, EF = ’1’). Read of the OTP row (64 bytes)

(
is by an instruction (see T able 4) composed of three
specific Write operations of data bytes at three
specific memory locations (each location in a dif­ferent page) before reading the OTP row content.

When accessing the OTP row, only the LSB ad­dresses (A6 to A0) are dec oded where A6 mus t be
’0’.

Each Read of the OTP row has to be followed by
the Return instruction (see Table 4).

Read the Flash Sector Protection Status

Reading the Flash sector protection status is by an
instruction similar to the Read Manufacturer iden­tifier instruction, the only difference being the value
of the logic levels applied on A0, A1, A 6, while A16
and A17 define the Flash sector whose protection
has to be verified. Such a read instruction will
output a 01h if the Flash sector is protected and a
00h if the Flash sector is not protected.

The Flash sector protection status can also be
verified with a Read operation (see chapter: Flash
block specific features), with V

on A9.

ID

Read the Status Bits

The M39208 provides several Write operation
status flags which may be used to minimize the
application write (or erase or program) time. These
signals are available on the I/O port bits when
programming (or erasing) are in progress.

Data Polling flag, DQ7.

When Erasing or Pro­gramming into the Flash block (or when Writing into
the EEPROM block), bit DQ7 outputs the comple­ment of the bit being entered for Program­ming/Writing on DQ7. Once the Program
instruction or the Write operation is per formed, the

Error

Flag

XXXXXX

X

Erase

Time-out

XXX

true logic value is read on DQ7 (in a Read opera­tion).

Flash memory block specific features:
– Data Polling is effective after the fourth W pulse

(for programming) or after the sixth W pulse (for
Erase). It must be performed at the address
being programmed or at an address within the
Flash sector being erased.

– During an Erase instruction, DQ7 outputs a ’0’.

After completion of the instruction, DQ7 will out­put the last bit programmed (that is a ’1’ after
erasing).

– if the byte to be programmed is in a protected

Flash sector, the instruction is ignored.

– If all the Flash sectors to be erased are pro-

tected, DQ7 will be set to ’0’ for about 100µs, and
then return to t he previous addressed byte. No
erasure will be performed.

– if all sectors are protected, a Bulk Erase instruc-

tion is ignored.

T oggle flag, DQ6.

The M39208 also offers another
way for determining when the EEPROM write or
the Flash memory Program instruction is com­pleted. During the internal Write operation, the DQ6
will toggle from ’0’ to ’1’ and ’1’ to ’0’ on subsequent
attempts to read any byte of the memory, when

G , EE or EF is low.

either
When the internal cycle is completed the toggling

will stop and the data read on DQ0-DQ7 is the
addressed memory byte. The device is now acces­sible for a new Read or Write operation. The opera­tion is completed when two successive reads yield
the same output data.

Flash memory block specific features:
a. the T oggle bit is effective after the fourth

(for programming) or after the sixth

W pulse

W pulse (for

Erase).
b. If the byte to be programmed belongs to a pro-

tected Flash sector, the instruction is ignored and:

7/30

M39208

Figure 4. EEPROM SDP Enable Flowcharts

Page
Write

Instruction

WRITE AAh in

Address 5555h

WRITE 55h in

Address 2AAAh

WRITE A0h in

Address 5555h

SDP is set

SDP ENABLE ALGORITHM

Page
Write

Instruction

SDP

Set

WRITE AAh in

Address 5555h

WRITE 55h in

Address 2AAAh

WRITE A0h in

Address 5555h

WRITE Data to

be Written in
any Address

Write

in Memory

SDP

not Set

WRITE
is enabled

Write Data

+

SDP Set

after tWC

AI01698B

– if all the Flash sectors selected for erasure

are protected, DQ6 will toggle to ’0’ for about
100µs, and then return to the previous ad­dressed byte.

– if all sectors are protected, the Bulk Erase in-

struction is ignored.

Error flag, DQ5 (F lash block only).

This bit is set
to ’1’ when there is a failure during either a Flash
byte programming or a Sector erase or the Bulk
Erase.

In case of error in Flash sector erase or byte
program, the Flash sector in which the error oc­curred or to which the programmed byte belongs,
must not be used any longer (other Flash sectors
may still be used). The Error bit resets after Reset
instruction.

During a correct Program or Erase, the Error bit will
set to ’0’.

Erase Time-out flag, DQ3 (Flash block only).

The Erase Timer bit reflects the time-out period
allowed between two consecutive Sector Erase
instructions. The Erase timer bit is set to ’0’ after a
Sector Erase instruction for a time period of 100µs

20% unless an additional Sector Erase instruction

±

is decoded. After this time period or when the
additional Sector Erase instruction is decoded,
DQ3 is set to ’1’.

WRITE a BYTE (or a P AGE ) in EEPROM

It should be noticed that writing in the EEPROM
block is an operation, it is not an instruction (as for
Programming a byte in the Flash block).

Write a Byte in EEPROM Block

A write operation is initiated w hen Chip Enable
is Low and Write Enable
Enable
edge of

G High. Addresses are latched on the falling

W, EE whichever occurs last.

W is Low with Output

EE

Once initiated, the write operation is internally
timed until completion, that is during a time t

.

W

The status of the write operation can be found by
reading the Data Polling and Toggle bits (as de­tailed in the READ chapter) or the Ready/Busy
output. This Ready/Busy output is driven low from
the write of the byte being written until the comple­tion of the internal Write sequence.

8/30

T ab le 7. Write the EEPROM Block Identifier

M39208

EF EE G WA6A9

V

IH

Figure 5. SDP disable Flowchart

V

IL

V

IH

V

IL

V

IL

V

period (between two consecutive Write operations)
that is smaller than the t
time exceeds the t
ming cycle will start.

WRITE AAh in

Address 5555h

EEPROM Block Software Data Protection

A protection instruction allows the user to inhibit all

WRITE 55h in

Address 2AAAh

write modes to the EEPROM block: the Software
Data Protection (referenced as SDP in the follow­ing). The SDP feature is useful for protecting the
EEPROM memory from inadvertent write cycles

Page
Write

Instruction

WRITE 80h in

Address 5555h

WRITE AAh in

Address 5555h

that may occur during uncontrolled bus conditions.
The M39208 is shipped as standard in the unpro-

tected state meaning that the EEPROM memory
contents can be changed by the user. After the SDP
enable instruction, the device enters the Protect
Mode where no further write oper ations have any

WRITE 55h in

Address 2AAAh

effect on the EEPROM memory contents.
The device remains in this mode until a valid SDP

disable instruction is received whereby t he device

WRITE 20h in

Address 5555h

Unprotected State

after

tWC (Write Cycle time)

AI01699B

reverts to the unprotected state.
T o enable the Software D ata Protection, the device

has to be written (with a Page Write) with three
specific data bytes at three specific memory loca­tions (each location in a different page) as shown
in Figure 4. This sequence provides an unlock key
to enable the writ e action, and, at t he same time,
SDP continues to be set. Any further Write in
EEPROM when the SDP is set will use this same
sequence of three specific data bytes at three

Write a Page in EEPROM Block

The Page write allows up to 64 bytes within the
same EEPROM page to be consecutively latched
into the memory prior t o initiating a programming
cycle. All bytes must be located in a single pa ge
address, that is A6-A12 must be the same for all
bytes. Once initiated, the Page write operation is
internally timed until completion, that is during a

WC

.

time t
The status of the write operation can be seen by

reading the Data Polling and Toggle bits (as de­tailed in the READ chapter).

A Page write is composed of successive Write
instructions which must be sequenced within a time

specific memory locations followed by the bytes to
write. The first SDP enable sequence can be di­rectly followed by the bytes to written.

Similarly, to disable the Software Data Protection
the user has to write specific data bytes into six
different locations with a Page Write addressing
different bytes in different pages, as shown in Fig­ure 5.

The Software Data Protection state is non-volatile
and is not changed by power on/off sequences. The
SDP enable/disable instructions set/reset an inter­nal non-volatile bit and therefore will require a write
time t
only on the Toggle bit (status bit DQ6).

Other

Addresses

ID

WC

Don’t Care 64 bytes User Defined

WLWL

value, the internal program-

WLWL

, This Write operation can be m onitored

DQ0 - DQ7

value. If this period of

9/30