SGS Thomson Microelectronics M36W832TE, M36W832BE Datasheet
32 Mbit (2Mb x16, Boot Block) Flash Memory
and 8 Mbit (512Kb x16) SRAM, Multiple Memory Product
FEATURES SUMMARY
■ SUPPLY VOLTAGE
–V
–V
–V
■ ACCESS TIMES: 70ns and 85ns
■ LOW POWER CONSUMPTION
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M36W832TE: 88BAh
– Bottom Device Code, M36W832BE: 88BBh
FLASH MEMORY
■ 32 Mbit (2Mb x16) BOOT BLOCK
– 8 x 4 KWord Parameter Blocks (Top or
■ PROGRAMMING TIME
– 10µ s typical
– Double Word Programming Option
– Quadruple Word Programming Option
■ BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
–WPF
■ AUTOMATIC STANDBY MODE
■ PROGRAM and ERASE SUSPEND
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ COMMON FLASH INTERFACE
■ SECURITY
– 128 bit user programmable OTP cells
– 64 bit unique device identifier
= 2.7V to 3.3V
DDF
= V
DDS
= 12V for Fast Program (optional)
PPF
= 2.7V to 3.3V
DDQF
Bottom Location)
for Block Lock-Down
M36W832TE
M36W832B E
Figure 1. Packages
FBGA
Stacked LFBGA66 (ZA)
12 x 8mm
SRAM
■ 8 Mbit (512Kb x 16)
■ ACCESS TIME: 70ns
■ LOW V
■ POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
DATA RETENTION: 1.5V
DDS
1/64May 2003
M36W832TE, M36W832BE
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. LFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Address Inputs (A0-A18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Address Inputs (A19-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Input/Output (DQ0-DQ15).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Write Protect (WPF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM Chip Enable (E1S, E2S).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
SRAM Output Enable (GS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
SRAM Upper Byte Enable (UBS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
Supply Voltage (2.7V to 3.3V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DDF
V
and V
DDQF
Program Supply Voltage.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
PPF
V
and V
SSF
Supply Voltage (2.7V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DDS
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SSS
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
Flash Memory Componen t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Flash Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Flash Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . 12
SRAM Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. SRAM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
Flash Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Automatic Standby.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Flash Command Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5
Table 3. Flash Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/64
M36W832TE, M36W832BE
Read Electronic Signature Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Program/Erase Suspend Comma nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Protection Register Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Block Lock Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 4. Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 5. Flash Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Flash Read Block Lock Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Flash Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Flash Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . 20
Flash Block Locking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Locked State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1
Lock-Down State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Protection Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Erase Status (Bit 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
V
Status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PPF
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Reserved (Bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. Flash Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
SRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/64
M36W832TE, M36W832BE
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7
Table 13. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 10. Flash Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 16. Flash Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 17. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12. Flash Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 18. Flash Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. Flash Power-Up and Reset AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 19. Flash Power-Up and Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V
Figure 15. SRAM Read AC Waveforms, GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 16. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 17. SRAM Write AC Waveforms, E1S or E2S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 20. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 18. SRAM Write AC Waveforms, WS Controlled, GS High during Write . . . . . . . . . . . . . . . 38
Figure 19. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . . . . 38
Figure 20. SRAM Write Cycle Waveform, UBS and LBS Controlled GS Low, . . . . . . . . . . . . . . . . 39
Table 21. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 21. SRAM Low V
Figure 22. SRAM Low V
Table 22. SRAM Low V
Data Retention AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . 41
DDS
Data Retention AC Waveforms, E2S Controlled . . . . . . . . . . . . . . . . 41
DDS
Data Retention Characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DDS
. . . . . . 36
IL
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 23. Stacked LFBGA66 12x8mm, 8x8 array, 0.8mm pitch, Bottom View Package Outline . . 42
Table 23. Stacked LFBGA66, 12x8mm, 8x8 ball array, 0.8mm pitch, Pa ckage Mechani ca l Data . 42
Figure 24. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package) . 43
Figure 25. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)44
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 25. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
APPENDIX A. FLASH MEMORY BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 26. Top Boot Block Addresses, M36W832TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 27. Bottom Boot Block Addresses, M36W832BE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 28. Query Structure Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 29. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 30. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4/64
M36W832TE, M36W832BE
Table 31. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 32. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 33. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
APPENDIX C. FLASH MEMORY FLOWCHARTS and PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . 53
Figure 26. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 27. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 28. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 29. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 56
Figure 30. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 31. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 32. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 33. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 60
APPENDIX D. FLASH MEMORY COMMAND INTERFACE and PROGRAM/ERASE CONTROLLER
STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 34. Write State Machine Current/Next, sheet 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 35. Write State Machine Current/Next, sheet 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
5/64
M36W832TE, M36W832BE
SUMMARY DESCRIPTION
The M36W832TE is a low voltage Multiple Memory Product which combines two me mory devices;
a 32 Mbit boot block Flash memory and an 8 M bit
SRAM. Recommended operating conditions do
not allow both the F lash and the S RAM t o be active at the same time.
The memory is offered in a Stacked LFBGA66
(12x8mm, 0.8 mm pitch) package and is s upplied
with all the bits erased (set to ‘1’).
Figure 2. Logic Diagram
V
V
DDF
DDQF
V
PPF
V
DDS
Table 1. Signal Names
A0-A18
A19-A20 Address Inputs for Flash Chip only
DQ0-DQ15 Data Input/Output
V
DDF
V
DDQF
V
PPF
V
SSF
V
DDS
Address Inputs common to the Flash
and SRAM chips
Flash Power Supply
Flash Power Supply for I/O Buffers
Flash Optional Supply V oltage for Fast
Program & Erase
Flash Ground
SRAM Power Supply
A0-A20
EF
GF
WF
RPF
WPF
E1S
E2S
GS
WS
UBS
LBS
21
M36W832TE
M36W832BE
V
SSF
V
SSS
16
DQ0-DQ15
AI90161b
V
SSS
NC Not Connected Internally
Flash control functions
EF
GF
WF
RPF
WPF
SRAM control functions
, E2S Chip Enable inputs
E1S
GS
WS
UBS
LBS
SRAM Ground
Chip Enable input
Output Enable input
Write Enable input
Reset input
Write Protect input
Output Enable input
Write Enable input
Upper Byte Enable input
Lower Byte Enable input
6/64
Figure 3. LFBGA Connections (Top view through package)
M36W832TE, M36W832BE
1211109
87654321
NCNC
DDQF
V
SSF
V
A12
A13A11A20NCNC
A15 A14
DQ7
DQ14
WS
DQ15A9A16
DQ5
DQ4
DQ6DQ13NCWF
DDF
V
DDS
V
E2SDQ12V
DQ3DQ2
DQ10
DQ11A19WPF
DQ1DQ0
DQ8DQ9GSLBS
E1SA1
A2A3A6A7A18
NC
NCNCGF
SSF
EFA0A4NCNC
AI90162b
A8 A10
A
B
C
RPF
SSS
D
PPF
V
E
UBS
F
A17
G
A5
NC V
H
7/64
M36W832TE, M36W832BE
Signal Descriptions
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A18). Addresses A0-A18 are common inputs for the Flash an d the SRAM components. The Address Inputs select the cells in the memory array to access during Bu s Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable ( Enable (WF
) signals, while the SRAM is accessed
through two Chip Enable signals (E1S
and the Write Enable signal (WS
EF) and Write
and E2S)
).
Address Inputs (A19-A20). Addresses A19-A20 are inputs for the Flash component only. The Flash memory is acc essed through the Chip E nable (EF
) and Write Enable (WF) signals
Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed durin g a Write Bus operation.
Flash Chip Enable (EF
). The Chip Enable input
activates the Flash memory control logic, input
buffers, decoders and sense amplifiers. When
Chip Enable is at V
is in active mode. When Chip Enable is at V
and Reset is at VIH the device
IL
IH
the
memory is deselected, the outputs are high impedance and the power consumption is reduced to the
standby level.
Flash Output Enable (GF
). The Output Enable
controls the data outputs during the Bus Read operation of the Flash memory.
Flash Write Enable (
WF). The Write Enable
controls the Bus Write operation of the Flash
memory’s Command I nterface. The data and address inputs are latched on the rising edge of Chip
Enable, EF
, or Write Enable, WF, whichever oc-
curs first.
Flash Write Protect (WPF
). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is at V
IL
, the
Lock-Down is enabled and the protection status of
the block cannot be changed. When Write Protect
is at V
, the Lock-Down is disabled and the block
IH
can be locked or unlocked. (refer to T able 6, Read
Protection Register and Protection Register Lock).
Flash Reset (RPF
). The Reset input provides a
hardware reset of the Flash memory. When Reset
is at V
, the memory is in reset mode: the outputs
IL
are high impedance and the current consumption
is minimized. After Reset all blocks are in the
Locked state. When Reset is at V
, the device is
IH
in normal operation. Exiting reset mode the device
enters read array mode, but a negative trans ition
of Chip Enable or a change of the address is required to ensure valid data outputs.
SRAM Chip Enable (E1S
, E2S). The Chip En-
able inputs activate the SRAM memory control
logic, input buffers and decoders. E1S
E2S at V
deselects the memory and reduces the
IL
power consumption to the standby level. E1S
at VIH or
and
E2S can also be used to control writing to the
SRAM memory array, while WS
is not allowed to set EF
at V
at the same time.
IH
SRAM Write Enable (WS
at V
E1S at VIL and E2S
IL,
). The Write Enable in-
remains at V
IL.
It
put controls writing to the SRAM memory array.
is active low.
WS
SRAM Output Enable (GS)
. The Output Enable
gates the outputs through the data buffers during
a read operation of t he SRAM memory. GS
is ac-
tive lo w .
SRAM Upper Byte Enable (UBS)
. The Upper
Byte Enable enables the upper bytes for SRAM
(DQ8-DQ15). UBS
SRAM Lower Byte Enable (LBS
is active low.
). The Lower
Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LBS
Supply Voltage (2.7V to 3.3V). V
V
DDF
is active low.
DDF
provides the power supply to the internal core of the
Flash Memory device. It is the main power s upply
for all operations (Read, Program and Erase).
and V
V
DDQF
provides the power supply for the Flash
V
DDQF
memory I/O pins and V
supply for
Supply Voltage (2.7V to 3.3V).
DDS
provides the power
DDS
the SRAM control pi ns. This allows all
Outputs to be powered independently of the Flash
core power supply, V
V
DDS
V
Program Su pp ly V ol t age. V
PPF
DDF
. V
can be tied to
DDQF
PPF
is both a
control input and a power suppl y pin for t he F lash
memory. The two functions are selected by the
voltage range applied to the pin. The S uppl y Voltage V
and the Program Supply Vol tage V
DDF
PPF
can be applied in any order.
If V
V
age lower than V
against program or erase, while V
is kept in a low voltage range (0V to 3.6V)
PPF
is seen as a control input. In this case a volt-
PPF
gives an absolute protection
PPLK
PPF
> V
PP1
enables these functions (see Table 15, DC Characteristics for the relevant values). V
PPF
is only
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect on Program or Erase,
however for Double or Q uadruple Word Program
the results are uncertain.
If V
power supply pin. In this con dition V
is in the range 11.4V to 12.6V it acts as a
PPF
PPF
must be
stable until the Program/Erase algorit hm is completed (see Table 17 and 18).
8/64
M36W832TE, M36W832BE
V
SSF
and V
Ground. V
SSS
SSF
and V
SSS
are the
ground reference for all voltage measurements in
the Flash and SRAM chips, respectively.
Note: Each device in a system should have V
DF
, V
DDQF
and V
decoupled with a 0.1µF ca-
PPF
D-
FUNCTIONAL DESCRIPTION
The Flash and SRAM components have separate
power supplies and grounds and are distinguished
by three chip enable inputs: EF
ory and, E1S
and E2S for the SRAM.
for the Flash mem-
Recommended operating conditions do not allow
both the Flash and the SRAM to be in active mode
at the same time. The most common example is
Figure 4. Funct i on a l Bl ock D i agram
V
DDF
EF
GF
WF
RPF
WPF
Flash Memory
32 Mbit (x16)
pacitor close to the pin. See Figure 9, AC
Measurement Load Circuit. The PCB trace
widths should be sufficient to carry the required V
program and erase currents.
PPF
simultaneous read operations on the Flash and
the SRAM which would resul t in a data bus contention. Therefore it is recommended to put the
SRAM in the h igh impedance state whe n reading
the Flash and vice versa (see Table 2 Main Operation Modes for details).
V
DDQF
V
PPF
A19-A20
A0-A18
E1S
E2S
GS
WS
UBS
LBS
V
DDS
SRAM
8 Mbit (x16)
V
SSS
V
SSF
DQ0-DQ15
AI90163
9/64
M36W832TE, M36W832BE
Table 2. Main Operation Modes
Operation
Mode
Read
Write
Block
Locking
Standby
Flash Memory
Reset X X X
Output
Disable
Read Flash must be disabled
Write Flash must be disabled
Standby/
SRAM
Power
Down
Data
Retention
Output
Disable
Note: X = VIL or VIH, V
EF
GF WF RPF WPF
V
ILVILVIHVIH
V
ILVIHVILVIH
V
XX
IL
V
XX
IH
V
ILVIHVIHVIH
V
IH
V
IH
V
IL
Any Flash mode is allowable
Any Flash mode is allowable
Any Flash mode is allowable
= 12V ± 5%.
PPFH
V
E1S E2S WS GS UBS LBS DQ15-D Q8 DQ7-DQ0
PPF
X Don’t care SRAM must be disabled Data Output
V
or
DDF
X
V
PPFH
V
Don’t care SRAM must be disabled X
IL
SRAM must be disabled Data Input
X Don’t care Any SRAM mode is allowed Hi-Z
X Don’t care Any SRAM mode is allowed Hi-Z
X Don’t care Any SRAM mode is allowed Hi-Z
XXV
V
ILVIHVIHVILVIHVIL
V
ILVIHVIHVILVILVIH
V
ILVIHVIL
V
ILVIHVIL
V
ILVIHVIL
V
IH
X
V
IH
X
V
ILVIHVIHVIH
IHVILVIL
X
X
X
X X X X X Hi-Z
V
XX
IL
X X X X X Hi-Z
V
X X X X Hi-Z
IL
V
IL
Data out
Hi-Z Data out
Data out Hi-Z
V
IL
V
IHVIL
V
ILVIH
V
IHVIH
V
IL
Data in
Hi-Z Data in
Data in Hi-Z
Hi-Z
X X Hi-Z
10/64
M36W832TE, M36W832BE
Flash Memory Componen t
The Flash Memory is a 32 Mbit (2 Mbit x 16) device
that can be erased electrically at block level and
programmed in-system on a Word-by-Word basis.
These operations can be performed using a single
low voltage (2.7 to 3.6V) supply. V
DDQF
allows to
drive the I/O pin down to 1.65V. An optional 12V
V
power supply is provided to speed up cus-
PPF
tomer programming.
The device features an asymmetrical blocked ar-
chitecture with an array of 71 blocks: 8 Parameter
Blocks of 4 KWords and 63 Main Blocks of 32
KWords. The M36W832TE has the Parameter
Blocks at the top of the memory address space
while the M36W832BE locates the Parameter
Blocks starting from the bottom. The memory
maps are shown in Figure 5, Block Addresses.
The Flash Memory features an instant, individual
block locking scheme that allo ws any block to be
locked or unlocked with no latency, enabling instant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any accidental programming or erasure. There is an additional
hardware protection against program and erase.
When V
PPF
≤ V
all blocks are protected
PPLK
against program or erase. All blocks are locked at
Power Up.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be s uspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
The device includes a Protection Register to increase the pro tection of a syste m design. The Protection Register is divided into two segments, t he
first is a 64 bit area which contains a unique device
number written by ST, while the second is a 128 bit
area, one-time-programmable by the user. The
user programmable segment can be permanent ly
protected. Figure 6, shows the Flash Security
Block and Protection Register Memory Map.
Program and Erase command s are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the timings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
Figure 5. Flash Block Addresses
Top Boot Block Addresses
1FFFFF
1FF000
1F8FFF
1F8000
1F7FFF
1F0000
00FFFF
008000
007FFF
000000
4 KWords
4 KWords
32 KWords
32 KWords
32 KWords
Total of 8
4 KWord Blocks
Total of 63
32 KWord Blocks
Bottom Boot Block Addresses
1FFFFF
1F8000
1F7FFF
1F0000
00FFFF
008000
007FFF
007000
000FFF
000000
32 KWords
32 KWords
32 KWords
4 KWords
4 KWords
Total of 63
32 KWord Blocks
Total of 8
4 KWord Blocks
Note: Also see Appendix A, Tab l es 26 and 27 for a ful l l is t i ng of the Flash B l ock Address es.
AI90164
11/64
M36W832TE, M36W832BE
Figure 6. Flash Security Block and Protection Registe r Memory Ma p
PROTECTION REGISTER
8Ch
User Programmable OTP
85h
84h
81h
80h
Note: 1. Bit 2 of the Protection Registe r Lock must no t be program m ed to 0.
Unique device number
Protection Register Lock 2
(1)
10
AI90165b
12/64
M36W832TE, M36W832BE
SRAM C o m pone nt
The SRAM is an 8 Mbit asynchronous random access memory which features a super lo w voltage
operation and low current consumption with an ac-
Figure 7. SRAM Block Diagram
DATA IN DRIVERS
A0-A10
ROW DECODER
512Kb x 16
RAM Array
2048 x 4096
COLUMN DECODER
A11-A18
cess time of 70ns in all conditions. The memory
operations can be performed using a single low
voltage supply, 2.7V to 3.3V, which is the same as
the Flash voltage supply.
DQ0-DQ7
SENSE AMPS
DQ8-DQ15
UBS
WS
GS
LBS
E2S
E1S
POWER-DOWN
CIRCUIT
UBS
LBS
E2S
E1S
AI07964
13/64
M36W832TE, M36W832BE
OPERATING MODES
Flash Bus Operations
There are six standard bus operations that control
the device. These are Bus Read, Bus Wri te, Output Disable, Standby, Automatic Standby and Reset. See Table 2, Main Operation Modes, for a
summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Read. Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable in put should be us ed to enable the device. Out put E nable shoul d be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figure 10, Flash Read Mode AC Waveforms, and Table 16, Flash Read AC Cha racteristics, for details of when the output becomes valid.
Read mode is the default state of the device when
exiting Reset or after power-up.
Write. Bus Write operations write Commands to the memory or latch Input Data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at V V
. Commands, Input Data and Addresses are
IH
latched on the rising edge of Write Enable or Chip
Enable, whichever occurs first.
with Output Enable at
IL
See Figures 11 and 12, Flash Write AC Waveforms, and Tables 17 and 18, Write AC Characteristics, for details of the timing requirements.
Output Disa bl e . The data outputs are high impedance when the Output Enable is at V
.
IH
Standby. Stan dby disables most of the inte rnal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable is at V
and the device is in
IH
read mode. The power consumption is reduced to
the stand-by level and the o utputs are set to high
impedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
V
during a program or erase operation, t he de-
IH
vice enters Standby mode when finished. Automatic Standby. Automatic Standby pro-
vides a low power consumption state during Read
mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity even if Chip Enable is Low, V
current is reduced to I
. The data I nputs/Out-
DD1
, and the supply
IL
puts will still output data if a bus Read operation is
in progress.
Reset. During Reset mode when Output Enable is Low, V
, the memory is deselected and the out-
IL
puts are high impedance. The memory is in Reset
mode when Reset is at V
. The power consump-
IL
tion is reduced to the Standby level, independently
from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled t o V
during a Pro-
SSF
gram or Erase, this operation is aborted and the
memory content is no longer valid.
14/64
Flash Command Interface
All Bus Write operations t o the me mory are in terpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution
of the Program and Erase commands. The Program/Erase Controller provides a S tatus Register
whose output may be read at any time during, to
monitor the progress of the operation, or the P rogram/Erase states. See Table 4, Command
Codes, for a summary o f the c ommands and see
Appendix 31, Table 34, Write State Machine Current/Next, for a summa ry of the Command Interface.
The Command Interface is reset to Read mode
when power is first applied, when exiting from Reset or whenever V
is lower than V
DDF
LKO
. Command sequences must be followed exactly. Any
invalid combination of commands will reset the device to Read mode . Refe r to Table 3, Flas h Com mand Codes, in conjunction with the following text
descriptions.
Table 3. Flash Command Codes
Hex Code Command
01h
10h Program
20h Erase
2Fh
30h
40h Program
50h Clear Status Register
55h Reserved
56h
60h
70h Read Status Register
90h Read Electronic Signature
98h Read CFI Query
B0h Program/Erase Suspend
C0h Protection Register Program
D0h
FFh Read Memory Array
Block Lock confirm
Block Lock-Down confirm
Double Word Program
Quadruple Word Program
Block Lock, Block Unlock, Block Lock-
Down
Program/Erase Resume, Block Unlock
confirm
M36W832TE, M36W832BE
Read Memory Array Command. The Read
command returns the memory to its Read mode.
One Bus Write cycle is required to issue the Read
Memory Array command and return the memory to
Read mode. Subsequent read operations will read
the addressed location and output the data. When
a device Reset occurs, the memory defaults to
Read mode.
Read Status Register Command. The Status
Register indicates when a program or erase operation is complete and the success or failure of the
operation itself. Issue a Read Status Register
command to read the Status Register’s cont ents.
Subsequent Bus Read operations read the Status
Register at any address, until another command is
issued. See Table 11, Status Register Bits, for details on the definitions of the bits.
The Read Status Register comm and may be issued at any time, even during a Program/Erase
operation. Any Read attempt during a Program/
Erase operation will automatically output the content of the Status Register.
Read Electronic Signature Command. The
Read Electronic Signature command reads the
Manufacturer and Device Codes and the Block
Locking Status, or the Protection Register.
The Read Electronic Signature command consists
of one write cycle, a subsequent read will output
the Manufacturer Code, the Device Code, the
Block Lock and Lock-Down Status, or the Protection and Lock Register. See Tables 5, 6 and 7 for
the valid address.
Read CFI Query Command. The Read Query
Command is used to read data from the Common
Flash Interface (CFI) Memory Area, allowing programming equipment or applications to automatically match their interface to the characteristics of
the device. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequ ent Bus Read operations
read from the Common Flash Interface Memory
Area. See Appendix B, Common Flash Interface,
Tables 28, 29, 30, 31, 32 and 33 for details on the
information contained in the Common Flash Interface memory area.
Block Erase Command. The Block Erase command can be used to erase a bloc k. It set s all t he
bits within the selected block to ’1’. All previous
data in the block is lost. If the block is protected
then the Erase operation will abort, the data in the
block will not be changed and the S tatus Regi ster
will output the e rr o r.
Two Bus Write cycles are required to issue the
command.
■ The first bus cycle sets up the Erase command.
15/64
M36W832TE, M36W832BE
■ The second latches the block address in the
internal state machine and starts the Program/
Erase Controller.
If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits b4 and b5 a re s et and
the command aborts.
Erase aborts if Reset turns to V
. As data integrity
IL
cannot be guaranteed when the Erase operation is
aborted, the block must be erased again.
During Erase operations the memory will accept
the Read Status Re gister com mand and the P rogram/Erase Suspend command, all other commands will be ignored. Typical Erase times are
given in Table 8, Flash Program, Erase Times and
Program/Erase Endurance Cycles.
See Appendix C, Figure 30 , Erase Flowchart and
Pseudo Code, for a suggested flowchart for using
the Erase command.
Program Command. T he memory array can be
programmed word-by-word. Two bus write cycles
are required to issue the Program Command.
■ The first bus cycle sets up the Program
command.
■ The second latches the Address and the Data to
be written and starts the Program/Erase
Controller.
During Program operations the memory will accept the Read Status Register command and the
Program/Erase Suspend command. Typical Program times are given in Table 8, Flash Program,
Erase Times and Program/Erase Endurance Cycles .
Programming aborts if Reset goe s to V
. As data
IL
integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and reprogrammed.
See Appendix C, Figure 26, Program Flowchart
and Pseudo Code, for the f lowchart for using the
Program command.
Doubl e Word Program Comm a nd. This feature
is offered to improve the programming throughput,
writing a page of two adjacent words in parallel.The two words mus t di ffer on ly f or the address
A0. Programming should n ot be attempted when
V
is not at V
PPF
PPH
.
Three bus write cycles are necessary to issue the
Double Word Program command.
■ The first bus cycle sets up the Double Word
Program Command.
■ The second bus cycle latches the Address and
the Data of the first word to be written.
■ The third bus cycle latches the Address and the
Data of the second word to be written and starts
the Program/Erase Controller.
Read operations output the Status Register content after the programming has s tarted. Programming aborts if Reset goes to V
. As data integrity
IL
cannot be guaranteed when the program operation is aborted, the block containing the memory
location must be erased and reprogrammed.
See Appendix C, Figure 27, Double Word Program Flowchart and Pseudo Code, for the flowchart for using the Double Word Program
command.
Quadruple Word Program Command. This
feature is offered to improve the programming
throughput, writing a page of four adjacent words
in parallel.The four words must differ only for the
addresses A0 and A1. Programming should not be
attempted when
is not at V
PPF
PPH
.
V
Five bus write cycles are necessary to issue the
Quadruple Word Program command.
■ The first bus cycle sets up the Quadruple Word
Program Command.
■ The second bus cycle latches the Address and
the Data of the first word to be written.
■ The third bus cycle latches the Address and the
Data of the second word to be written.
■ The fourth bus cycle latches the Address and
the Data of the third word to be written.
■ The fifth bus cycl e latches the Addres s and th e
Data of the fourth word to be written and starts
the Program/Erase Controller.
Read operations output the Status Register content after the programming has s tarted. Programming aborts if Reset goes to V
. As data integrity
IL
cannot be guaranteed when the program operation is aborted, the block containing the memory
location must be erased and reprogrammed.
See Appendix C, Figure 28, Quadruple Word Program Flowchart and Pseudo Code, for the flowchart for using the Quadruple Word Program
command.
Clear Status Register Command. The Clear
Status Register command can be used to reset
bits 1, 3, 4 and 5 in the Status Register to ‘0’. One
bus write cycle is required to issue the Clear Status Register command.
The bits in the Status Register do not automatically return to ‘0’ when a new Program or Erase command is issued. The error bits in the Status
Register should be cleared before attempting a
new Program or Erase command.
Program/Erase Suspend Command. The Program/Erase Suspend comm and is used to pause
a Program or Erase operation. One bus write cycle
is required to issue the Program/Erase c ommand
and pause the Program/Erase controller.
During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume,
16/64
M36W832TE, M36W832BE
Read Array, Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then
the Program, Double Word Program, Quadruple
Word Program, Block Lock, Block Lock -Down or
Protection Program commands will also be accepted. The block being erased may be protected
by issuing the Block Protect, Block Lock or Protection Program commands. When the Program/
Erase Resume com mand is issued the operation
will complete. Only the blocks not being erased
may be read or programmed correctly.
During a Program/Erase Suspend, the device can
be placed in a pseudo-standby mode by taking
Chip Ena ble to V
Reset turns to V
. Program/Erase is aborted if
IH
.
IL
See Appendix C, Figure 2 9, Program or Doub le
Word Program Suspend & Resume Flowchart and
Pseudo Code, an d Figure 31, Erase Sus pend &
Resume Flowchart and Pseudo Code for flowcharts for using the Program/Erase Suspend command.
Program/Erase Resume Command. The Program/Erase Resume command can be used to restart the Program/Erase Controller after a
Program/Erase Suspend operat ion h as paused it.
One Bus Write cycle is required to issue the command. Once the command is issued subsequent
Bus Read operations read the Status Register.
See Appendix C, Figure 2 9, Program or Doub le
Word Program Suspend & Resume Flowchart and
Pseudo Code, an d Figure 31, Erase Sus pend &
Resume Flowchart and Pseudo Code for flowcharts for using the Program/Erase Resume command.
Protection Regist er Program Command. The
Protection Register Program c omm and is used to
Program the 128 bit user One-Time-Programmable (OTP) segment of the Protection Register. The
segment is programmed 16 bits at a time. When
shipped all bits in the segment are set to ‘1’. The
user can only program the bits to ‘0’.
Two write cycles are required to issue the Protection Register Program command.
■ The first bus cycle sets up the Protection
Register Program command.
■ The second latches the Address and the Data to
be written to the Protection Register and starts
the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
The segment can be protected by programming bit
1 of the Protection Lock Register (see Figure 6,
Flash Security Block and Protection Register
Memory Map). Attempting to program a previously
protected Protection Register will result in a Status
Register error. The protection of the Protection
Register is not reversible.
The Protection Register Program cannot be suspended.
Block Lock Command. The Block Lock command is used to lock a block and prevent Program
or Erase operations from changing the data i n it.
All blocks are locked at power-up or reset.
Two Bus Write cycles are required to issue the
Block Lock command.
■ The first bus cycle sets up the Block Lock
command.
■ The second Bus Write cycle latc hes the block
address.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table. 10 shows the protection status after issuing
a Block Lock command.
The Block Lock bits are vo latile, once set they remain set until a hardware reset or power-down/
power-up. They are cleared by a Blocks Unlock
command. Refer to the section, Block Locking, for
a detailed explanation.
Block Unlock Command. The Blocks Unlock
command is used to unlock a block, allowing the
block to be programmed or erased. Two Bus Write
cycles are required to issue the Blocks Unlock
command.
■ The first bus cycle sets up the Block Unlock
command.
■ The second Bus Write cycle latc hes the block
address.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table. 10 shows the protection status after issuing
a Block Unlock command. Refer to the “Flash
Block Locking” section, for a detailed explanation.
Block Lock-Down Command. A locked block
cannot be Programmed or Erased, or have its protection status changed when WPF
When WPF
is high, V
the Lock-Down function is
IH,
is low, VIL.
disabled and the locked blocks can be individually
unlocked by the Block Unlock command.
Two Bus Write cycles are required to issue the
Block Lock-Down command.
■ The first bus cycle sets up the Block Lock
command.
■ The second Bus Write cycle latc hes the block
address.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Locked-Down blocks revert to the locked (and not
locked-down) state when the device is reset on
power-down. Table. 10 sho ws the protection status after issuing a Block Lock-Down command.
17/64
M36W832TE, M36W832BE
Refer to the “Flash Block Locking” section for a detailed explanation.
Table 4. Flash Commands
Bus Write Operations
Commands
Read Memory
Array
Read Status
Register
Read Electronic
Signature
Read CFI Query 1+ Write X 98h Read QA QD
Erase 2 Write X 20h Write BA D0h
Program 2 Write X
Double Word
Program
Quadruple Word
Program
Clear Status
Register
Program/Erase
Suspend
Program/Erase
Resume
Block Loc k 2 Write X 60h Write
Block Unlock 2 Write X 60h Write
Block Loc k-Down 2 Write X 60h Write
Protection
Register Program
Note: X = Don’t Care.
(3)
(4)
1. The signature a ddresses are l i st ed in Tables 5, 6 and 7.
2. Addr 1 and Addr 2 must be consecu tive Addresses differi ng only for A0.
3. Program Addres ses 1 and 2 must be consecutive Addresses differing onl y for A0.
4. Program Addres ses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
5. 55h is reserved.
6. To be characterized.
1+ Write X FFh
1+ Write X 70h Read X SRD
1+ Write X 90h Read
1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle
Cycles
Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data
RA RD
Read
(2)
IDh
SA
40h
or
Write PA PD
10h
3 Write X 30h Write PA1 PD1 Write PA2 PD2
5Write X
1 Write X 50h
1Write X B0h
1Write X D0h
(6)
Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4
56h
BA 01h
D0h
BA
BA 2Fh
2 Write X C0h Write
PRA
PRD
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M36W832TE, M36W832BE
Table 5. Flash Read Electronic Signature
Code Device EF GF WF A0 A1 A2-A7 A8-A11 A12-A20 DQ0-DQ7 DQ8-DQ15
Manufacture
Code
Device
Code
Note: RPF = VIH.
M36W832TE
M36W832BE
Table 6. Flash Read Block Lock Signature
Block Status EF GF WF A0 A1 A2-A7 A8-A20 A12-A20 DQ0 DQ1 DQ2-DQ15
Locked Block
Unlocked Block
Locked-Down
Block
Note: 1. A Locked Block can be protected "DQ0 = 1" or unprotected "DQ0 = 0" ; see Block Locking section.
Table 7. Flash Read Protection Register and Lock Register
Word EF
Lock
Unique ID 0
Unique ID 1
Unique ID 2
Unique ID 3
OTP 0
OTP 1
OTP 2
OTP 3
GF WF A0-A7 A8-A20 DQ0 DQ1 DQ2 DQ3-DQ7 DQ8-DQ15
V
ILVILVIH
V
ILVILVIH
V
ILVILVIH
V
ILVILVIH
V
ILVILVIH
V
ILVILVIH
V
ILVILVIH
V
ILVILVIH
V
ILVILVIH
V
ILVILVIHVILVIL
V
ILVILVIHVIHVIL
V
ILVILVIHVIHVIL
V
ILVILVIHVILVIH
V
ILVILVIHVILVIH
V
ILVILVIHVILVIH
80h Don’t Care Don’t Care
81h Don’t Care ID data ID data ID data ID data ID data
82h Don’t Care ID data ID data ID data ID data ID data
83h Don’t Care ID data ID data ID data ID data ID data
84h Don’t Care ID data ID data ID data ID data ID data
85h Don’t Care OTP data OTP data OTP data OTP data OTP data
86h Don’t Care OTP data OTP data OTP data OTP data OTP data
87h Don’t Care OTP data OTP data OTP data OTP data OTP data
88h Don’t Care OTP data OTP data OTP data OTP data OTP data
0 Don’t Care 20h 00h
0 Don’t Care BAh 88h
0 Don’t Care BBh 88h
0 Don’t Care Block Address 1 0 00h
0 Don’t Care Block Address 0 0 00h
0 Don’t Care Block Address
OTP Prot.
data
Don’t Care
See note (1)
X
(1)
1 00h
Don’t
Care
Don’t Care
V
IL
V
IL
V
IL
19/64
M36W832TE, M36W832BE
Table 8. Flash Program, Erase Times and Program /Era se Endu ranc e Cycles
Parameter Test Conditions
Min Typ Max
V
Word Program
Double Word Program
Quadruple Word Program
Main Block Program
Parameter Block Program
Main Block Erase
Parameter Block Erase
= V
PPF
V
= 12V ±5%
PPF
V
= 12V ±5%
PPF
V
= 12V ±5%
PPF
= V
V
PPF
= 12V ±5%
V
PPF
= V
V
PPF
= 12V ±5%
V
PPF
= VDDV
V
PPF
V
= 12V ±5%
PPF
V
= V
PPF
DDF
DDF
DDF
DDF
DDF
Program/Erase Cycles (per Block) 100,000 cycles
Note: 1. Typical time to program a Main or Parameter Block using the Double Word Program and the Quadruple Word Program commands
respectively.
Flash Device
10 200 µs
10 200 µs
10 200 µs
0.16/0.08
(1)
5s
0.32 5 s
0.02/0.01
(1)
4s
0.04 4 s
110s
110s
0.4 10 s
0.4 10 s
Unit
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