SGS Thomson Microelectronics M36W432T, M36W432B Datasheet

32 Mbit (2Mb x16, Boot Block) Flash Memory

and 4 Mbit (256K x16) SRAM, Multiple Me mory Product

FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V –V –V

■ ACCE SS TIME: 70,85ns

■ LOW POWE R CONSUMPT ION

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h – Top Device Code, M36W432T: 88BAh – Bottom Device Code, M36W432B: 88BBh

FLASH MEMORY

■ 32 Mbit (2Mb x16) BOOT BLOCK

– 8 x 4 KWord Parameter Blocks (Top or

■ PROGRAMMING TIME

– 10µs typical – Double Word Programming Option

■ BL OCK LOCKING

– All blocks locked at Power up – Any combination of blocks can be locked –WPF

■ AUTOMATIC STAND-BY MODE

■ PROGRAM and ERASE SUSPEND

■ COMMON FLASH INTERFACE

– 64 bit Security Code

■ SECURITY

– 64 bit user programmable OTP cells – 64 bit unique device identifier – One parameter block permanently lockable

=2.7Vto3.3V

DDF DDS=VDDQF

= 12V for Fast Program (optional)

PPF

=2.7Vto3.3V

Bottom Location)

for Block Lock-Down

M36W432T

M36W432B

PRODUCT PREVIEW

SRAM

■ 4 Mbit (256K x 16 bit)

■ ACCE SS TIME: 70ns

■ LOW V

■ POWER DOWN FEATURES USING TWO

CHIP ENABLE INPUTS

Figure 1. Packages

DATA RETENTION: 1.5V

DDS

FBGA

Stacked LFBGA66 (ZA)

8 x 8 ball array

February 2002

This is preliminary information on a new product now in development. Details are subject to change without notice.

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M36W432T, M36W432B

TABLE OF CONTENTS

SUMMARYDESCRIPTION...........................................................5

Figure2.LogicDiagram ..........................................................5

Table 1. Signal Names . . . ........................................................5

Figure 3. LFBGA Connections (Top view through package). ..............................6

SIGNALDESCRIPTIONS............................................................6

FUNCTIONAL DESCRIPTION ........................................................8

Figure 4. Functional Block Diagram .................................................8

Table2.MainOperationModes ....................................................9

FlashMemoryComponent......................................................10

Figure5.FlashBlockAddresses...................................................11

Figure6.FlashSecurityBlockMemoryMap..........................................11

SRAMComponent.............................................................11

OPERATINGMODES..............................................................12

FlashBusOperations..........................................................12

FlashCommandInterface.......................................................12

Table3.Commands ............................................................15

Table4.ReadElectronicSignature.................................................16

Table5.ReadBlockSignature....................................................16

Table6.ReadProtectionRegisterandLockRegister ..................................16

Table7.Program,EraseTimesandProgram/EraseEnduranceCycles ....................17

FlashBlockLocking...........................................................17

Table8.BlockLockStatus .......................................................18

Table9.LockStatus............................................................18

FlashStatusRegister ...........................................................19

Table10.StatusRegisterBits.....................................................20

SRAMOperations .............................................................20

MAXIMUMRATING................................................................21

Table11.AbsoluteMaximumRatings...............................................21

DCandACPARAMETERS .........................................................22

Table 12. Operating and AC Measurement Conditions..................................22

Figure7.ACMeasurementI/OWaveform...........................................22

Figure 8. AC Measurement Load Circuit. . . ..........................................22

Table 13. Device Capacitance.....................................................22

Table14.DCCharacteristics......................................................23

Figure9.FlashReadACWaveforms...............................................24

Table15.FlashReadACCharacteristics............................................24

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M36W432T, M36W432B

Figure10.FlashWriteACWaveforms,WriteEnableControlled..........................26

Table16.FlashWriteACCharacteristics,WriteEnableControlled........................27

Figure 11. Flash Write AC Waveforms, Chip Enable Controlled...........................28

Table 17. Flash Write AC Characteristics, Chip Enable Controlled. . .......................29

Figure12.FlashPower-UpandResetACWaveforms..................................30

Table18.FlashPower-UpandResetACCharacteristics................................30

Figure 13. SRAM Read AC Waveforms, Address Controlled with UBS = LBS = V

Figure14.SRAMReadACWaveforms,E1S,E2SorGSControlled.......................31

Figure 15. SRAM Standby AC Waveforms . ..........................................32

Table19.SRAMReadACCharacteristics...........................................32

Figure16.SRAMWriteACWaveforms,WSControlledwithGSLow ......................33

Figure17.SRAMWriteACWaveforms,WSControlledwithGSHigh......................33

Figure18.SRAMWriteACWaveforms,UBSandLBSControlled.........................34

Figure19.SRAMWriteACWaveforms,E1SControlled ................................34

Table20.SRAMWriteACCharacteristics ...........................................35

Figure 20. SRAM Low V Figure 21. SRAM Low V Table 21. SRAM Low V

DataRetentionACWaveforms,E1SControlled................36

DDS

DataRetentionACWaveforms,E2SControlled................36

DDS

DataRetentionCharacteristic...............................36

DDS

PACKAGE MECHANICAL . . . .......................................................37

...........31

Figure22.StackedLFBGA66-8x8ballarray,0.8mmpitch,BottomViewPackageOutline....37

Table 22. Stacked LFBGA66 - 8 x 8 ball array, 0.8 mm pitch, Package Mechanical Data . . . ....37

Figure 23. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through pack age) . 38 Figure 24. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package)39

PARTNUMBERING ...............................................................40

Table23.OrderingInformationScheme.............................................40

Table24.DaisyChainOrderingScheme ............................................40

REVISIONHISTORY...............................................................41

Table25.DocumentRevisionHistory...............................................41

APPENDIXA.FLASHMEMORYBLOCKADDRESSTABLES .............................42

Table 26. Top Boot Block Addresses, M36W432T . ....................................42

Table27.BottomBootBlockAddresses,M36W432B ..................................43

APPENDIXB.COMMONFLASHINTERFACE(CFI) .....................................44

Table28.QueryStructureOverview................................................44

Table 29. CFI Query Identification String . . ..........................................44

Table30.CFIQuerySystemInterfaceInformation.....................................45

Table31.DeviceGeometryDefinition...............................................46

Table 32. Primary Algorithm-Specific Extended Query Table .............................47

Table33.SecurityCodeArea.....................................................48

APPENDIXC.FLASHMEMORYFLOWCHARTSandPSEUDOCODES.....................49

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M36W432T, M36W432B

Figure 25. Program Flowchart and Pseudo Code . . ....................................49

Figure 26. Double Word Program Flowchart and Pseudo Code ...........................50

Figure 27. Program Suspend & Resume Flowchart and Pseudo Code .....................51

Figure 28. Erase Flowchart and Pseudo Code ........................................52

Figure 29. Erase Suspend & Resume Flowchart and Pseudo Code. .......................53

Figure 30. Locking Operations Flowchart and Pseudo Code .............................54

APPENDIX D. FLASH MEMORY COMMAND INTERFACE and PROGRAM/ERASE CONTROLLER

STATE..........................................................................55

Table34.WriteStateMachineCurrent/Next,sheet1of2...............................55

Table35.WriteStateMachineCurrent/Next,sheet2of2...............................56

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SUMMARY DESCRIPTION

The M36W432 is a low voltage M ultiple Memory Product which combines two memory devices; a 32 Mbit boot block F lash memory and a 4 Mbit SRAM. Rec ommended operating condit ions do not allow both the Flash and the SRAM to be active at the same time.

The memory is offered ina StackedLFBGA66 (0.8 mm pitch) pack age and is supplied wi th all the bits erased (set to ‘1’).

M36W432T, M36W432B

Table 1. Signal Names

A0-A17 Address Inputs A18-A20 Address Inputs for Flash Chip only DQ0-DQ15 Data Input/Output V V

DDF

DDQF

Flash Power Supply Flash Power Supply for I/O Buffers

Figure 2. Logic Diagram

DDQF

M36W432T M36W432B

A0-A20

RPF

WPF

E1S E2S

UBS

LBS

DDF

PPF

DDS

DQ0-DQ15

PPF

SSF

DDS

SSS

NC Not Connected Internally

Flash control functions

EF GF WF RPF WPF

SRAM control functions

, E2S Chip Enable inputs

E1S GS WS UBS LBS

Flash Optional Supply Voltage for Fast Program & Erase

Flash Ground SRAM Power Supply SRAM Ground

Chip Enable input Output Enable input Write Enable input Reset input Write Protect input

Output Enable input Write Enable input Upper Byte Enable input Lower Byte Enable input

SSF

SSS

AI05200

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M36W432T, M36W432B

Figure 3. LFBGA Connections (Top view throu gh p ackage)

654321#2#1

A8 A10

RPF

SSS

PPF

UBS

A17

NC V

A15 A14

DQ11A19WPF

A13A11A20NC

DQ9GSLBS

EFA0A4NC

A12

WSDQ15A9A16

DQ6DQ13NCWF

E2SDQ12V

DQ10

DQ8

A2A3A6A7A18

SSF

SSFVDDQF

DQ14

DQ4

DDS

DQ7

DQ5

DQ3DQ2

DQ1DQ0

E1SA1

DDF

NCNCGF

#4#387

NCNC

SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram and Table 1,Signal Names, for abrief overview of the signals connected to this device.

Address Inputs (A0-A17). Addresses A0-A17 are common inputs for the Flash an d the SRAM components. The Address Inputs select the cells in the mem ory array to acces s during Bus Read operations. During Bus Write operations they control thecommands sent to the Command Interface ofthe internalstate machine.The Flashmemory is accessed through the Chip Enable ( Enable (WF

) signals, while the SRAM is accessed through two Chip Enab le signals (E1S and the Write Enable signal (WS

EF)andWrite

and E2S)

Address Inputs (A18-A20). A ddres s es A18-A20 are in puts for the Flash component only. The Flash memory is acces s ed through the Chip Enable (EF

) and Write Enable (WF) signals

Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at t he s elected address

AI05201

during a Bus Read operationor inputsa command orthedatatobeprogrammedduringaWriteBus operation.

Flash Chip Enable (EF

). The Chip En able input

activates the Flash memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at V is in active mode. When Chip Enable is at V

andResetisatVIHthe device

the

memory is deselected,the outputsare high impedance an d the power consumption isreduced tothe standby level.

Flash Output Enable (GF

). The Output Enable

controls the data outputs during the Bus R ead operation of the Flash memory.

Flash Write Enable (

WF). The Write Enable

controls the Bus Write operation of the Flash memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable, EF

, or Write Enable, WF, whichever oc-

curs first.

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M36W432T, M36W432B

Flash Write Protect (WPF). Write Protect is an

input that gives an additional hardware protection for each block. When Write Protect is at V

,the

Lock-Down is enabled and the protection status of the block cannot be changed. When Write Protect is at V

, the Lock-Down is disabled and the block

can be locked or unlocked. (refer to Table 6, Read Protection Registerand Protection Register Lock).

Flash Reset (RPF

). The Res et input provides a

hardware reset of the Flash memory. When Res et is at V

, the m emory is in reset mode: the outputs

are high impedance and the c urrent consumption is minimized. After R es et all blocks are i n the Locked state. When Reset is at V

, the device is

in norm al operation. Exiting resetmode the device enters read array mode, but a negative transition of Chip Enable or a change of the address is required to ensure valid data outputs.

SRAM Chip Enable (E1S

,E2S). TheChipEn-

able inputs activate the SRAM memory control logic, input buffers and decoders. E1S E2S at V

deselects the memory and reduces the

power consumption to the standby level. E1S

at VIHor

and E2S can also be used to control writing to the SRAM memory array, while WS is not allowed to set EF at V

at the same time.

at V

SRAMWriteEnable(WS

remains at V

E1S at VILandE2S

IL,

IL.

). The Write Enable in-

put cont rols writing to the SR AM memory array.

is active low.

SRAM Output Enable (GS)

. The Ou tput Enable

gates the outputs through the data buffers during a read operation of the SRAM memory. GS

is ac-

tive low.

SRAM Upper Byte Enable (UBS)

. The Upper

Byte Enable enables the upper bytes for SRAM (DQ8-DQ15). UBS

SRAM Lower Byte Enable (LBS

is active low.

). The Lower Byte Enable enables t he lower bytes for SRAM (DQ0-DQ7). LBS

is active low.

Supply Voltage (2.7V to 3.3V). V

DDF

vides the power supply to the internal core of the Flash Memory device. It is the main power supply for all operations (Read, Program and Erase).

and V

DDQF

provides the power supply for the Flash

DDQF

memory I/O pins and V

Supply Voltage (2.7V to 3.3V).

DDS

provides the power

DDS

supply for the SRAM control pins. This allows all Outputs to be powered independently from the Flash core power supply,V to V

DDS

Program Supply Voltage. V

PPF

DDF.VDDQF

control input and a power supply pin for the Flash memory. The two functions are s elect ed by the voltage range applied to the pin. The S upply Voltage V

and the Program Supply Voltage V

DDF

can be applied in any order. If V

V age lower than V against program or erase, while V

is kept in a low voltage range (0V to 3.6V)

PPF

is seen as a control input. In this case a volt-

PPF

gives anabsolute protection

PPLK

PPF>VPPLK

ables these functions (see Table 14, DC Charac teristics for the rele va nt values ). V sampled at the beginning of a program or erase; a

change in its value after the operation has started does not haveany effect and programor eraseoperations continue.

If V

is in the range 11.4V to 12.6V it acts as a

PPF

power supply pin. In this condition V stable until the Program/Erase algorithm is completed (see Table 16 and 17).

SSF

and V

Ground. V

SSS

SSF

and V ground reference for all voltage measurements in the Flash and SRAM chips, respectively.

Note: E ach device in a system should have V

DDQF

and V

decoupled with a 0.1µF ca-

PPF

pacitor clos e to the pin. See Figure 9, AC Measurement Load Circuit. The PCB trace widths should be sufficient to carry the required V

program and erase currents.

PPF

DDF

canbetied

is both a

PPF

must be

PPF

SSS

pro-

PPF

en-

is only

are the

D-

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M36W432T, M36W432B

FUNCTIONAL DESCRIPTION

The Flash and SRAM components have separate power supplies and grounds and are distinguished by three chip ena ble inputs: EF ory and, E1S

and E2S for the SRAM.

Recommended operating conditions do not allow both theFlash and the SRAM to be in active mode at the same time. The mos t common example is

Figure 4. Functional Block Diagram

for the Flash mem-

simultaneous rea d operations on the Flash and the SRAM which would result in a data bus contention. Therefore it is recommended to put the SRAM in the high impedance state when reading theFlashandviceversa(seeTable2MainOperation Modes for details).

EF GF

WF WF

RPF RPF

WPF WPF

A18-A20 A18-A20

A0-A17 A0-A17

E1S

E2S

GS WS

UBS

LBS

DDF

Flash Memory Flash Memory

32 Mbit (x16) 32 Mbit (x16)

DDS

DDQF

SRAM SRAM

4 Mbit (x16)

PPF PPF

SSF SSF

DQ0-DQ15 DQ0-DQ15

8/57

V V

SSS SSS

AI05202 AI05202

Table 2. Main Operation Modes

Operation

Mode

Read

Write

Block Locking

Standby

Flash Memory

Reset X X X

Output Disable

Read Flash must be disabled

Write Flash must be disabled

Standby/ Power Down

SRAM

Data Retention

Output Disable

Note: X = VILor VIH,V

1. If UBS

and LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBS and LBS separately.

GF WF RPF WPF

ILVILVIHVIH

ILVIHVILVIH

V V

ILVIHVIHVIH

Any Flash mode is allowable

=12V±5%.

PPFH

M36W432T, M36W432B

PPF

X Don't care SRAM must be disabled

X Don't care Any SRAM mode is allowed Hi-Z

DDF

PPFH

Don't care SRAM must be disabled X

X Don't care Any SRAM mode is allowed Hi-Z

E1S E2S GS WS

SRAM must be disabled Data Input

ILVIHVILVIH

ILVIHVIHVIL

XXX X Hi-Z

XXXX

XXX X Hi-Z

XXXX

ILVIHVIHVIH

UBS,LBS

X X X Hi-Z

X Hi-Z

(1)

DQ15-DQ0

Data

Output

Data out

Word Read

Data in

Word Write

Hi-Z

9/57

M36W432T, M36W432B

Flash Memory Component

TheFlashMemoryisa32Mbit(2Mbitx16)device that can be erased electrically at th e block level and progra m m ed in-system on a Word-byWord basis. These operations can be performed using a single low voltage (2.7 to 3.3V) supply and t he V same voltage range. An optional 12V V

for de vice I/0operation feature the

DDQF

PPF

power supply is provided to speed up customer programming.

The dev ice features an asymmetrical blocked architecture with an array of 71 blocks: 8 Parameter Blocksof4KWordand63MainBlocksof32 KWord. The M36W432T device has the Flash Memory Parameter Blocks at the top of the memoryaddress spacewhile theM36W432B devicelocates the Parameter Blocks s tarting from the bottom. The memory m aps are shown in Figure 5, Block Addresses.

The Flash Memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be lock ed and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When V

PPF

≤ V

all blocks are protected

PPLK

against program or erase. All blocks are locked at Power Up.

Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles.

The device includes a 128 bit Protec tion Register and a Securit y Block to increase the prote ction of a system design. The Protection Register is divided into two 64 bit segments, the first one contains a unique device number written by ST, whi le the second one is one-time-programmable by the user. The user programmable segment can be permanently protected. The Sec urity Block, parameter block 0, can be permanently p ro tected by the user. Figure 6, shows the Flash Security Block Memory Map.

Program a nd Erase commands are written to the Command Interface of the memory. An on-c hip Program/Erase Control ler takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

10/57

Figure 5. Flash Block Addresses

M36W432T, M36W432B

Top Boot Block Addresses

1FFFFF

1FF000

1F8FFF

1F8000

1F7FFF

1F0000

00FFFF

008000

007FFF

000000

Note: Also see Appendix A, Tables 26 and 27 for a full listing of the Flash Block Addresses.

4 KWords

Total of 8

4 KWord Blocks

4 KWords

32 KWords

Total of 63

32 KWord Blocks

32 KWords

Bottom Boot Block Addresses

1FFFFF

1F8000

1F7FFF

1F0000

00FFFF

008000

007FFF

007000

000FFF

000000

32 KWords

Total of 63

32 KWord Blocks

32 KWords

4 KWords

Total of 8

4 KWord Blocks

4 KWords

AI05203

Figure 6. Flash Security Block Memory Map

88h

85h 84h

Parameter Block # 0

81h 80h

SRAM Component

The SRAM is an 4 Mbit asynchronous random access mem ory which features a super low voltage operation and low current consumption withan ac -

User Programmable OTP

Unique device number

Protection Register Lock 2 1 0

AI05204

cess time of 70 ns in all conditions. The memory operations can be performed using a single low voltage supply, 2.7V to 3.3V, whic h is the same as the Flash voltage supply.

11/57

M36W432T, M36W432B

OPERATING MODES Flash Bus Operations

There are six stand ard bus operations that control the device. These are B us Read, Bus Write, Ou tput Disable, Standby, Automatic Standby and Reset. See Table 2, Main Operation Modes, for a summary.

Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.

Read. Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Comm on Flash Interface. Both Chip Enable and Output EnablemustbeatV

in order to perform a read op-

eration. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figure 9, Read Mode AC Waveforms , and Table 15, Flash Read AC Cha r acteristics, for details of when the output becomes valid.

Read mode isthe default state of the device when exiting Reset or after power-up.

Write. B us Write operations write Commands to the memory orlatch InputData to beprogrammed. A write operation is initiated when Chip Enable and Write Enable are at V V

. Commands, Input Data and Addresses are

with Output Enable at

latched on the rising edge of Write Enable or Chip Enable, whichever occurs first.

See Figures 10 and 11, Write AC Waveforms, and Tables 16 and 17, Flash Write AC Chara cteristics, for details of the timing requirements.

Output Disable. The data ou tpu ts are high im pedance when the Output Enable is at V

Standby. Standby disables most o f the internal circuitryallowing asubstantial reduc t ion ofthe current consumption. The memory is in stand-by when Chip Enable is at V

andthedeviceisin

read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently f rom the Output Enable or Write Enable inputs. If Chip Enable switches to

during a program or erase operat ion, the de-

vice enters Standby mode when finished. Automatic Standby. Automatic Standby pro-

vides a low power consumption state during Read mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity even if Chip Enable is Low, V current is reduced to I

. The data I nputs/Out-

DD1

, and the supply

puts will s till output data if abus Read operation is in progress.

Reset. During Reset mode when O ut put Enable is Low, V

, the memory is des elected and the out-

puts are high impedance. The memory is in R eset mode when Reset is at V

. The power consump-

tion is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset ispulled to V

during aPro-

SSF

gram or Erase, this operation is aborted and the memory content is no longer valid.

Flash Command Interface

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles a ll timings and verifies the correct execution of the Program and Erase commands. The Pr ogram/Erase Controller provides a Status Register whose output may be read at any time during, to monitor the progress of the operation, or the Program/Erase states. See Appendix 29, Table 34, Write State Machine Current/Next, for a summary of the Command Interface.

The Command Interface is res et to Read mode when power is f irst applied, when exiting from Reset or whenever V

is lower than V

DDF

LKO

.Command sequences must be followed exactly. Any invalid combination of com mands will reset the device to Read mode. Refer to Table 3, Commands, in conjunction with the text descriptions below.

Read Memory Ar ray Command. The Read command returns the memory to its Read mode. One Bus Write cycle is required to issue t he Read Memory Array command and returnthe memory to Read mode. Subsequent read operations willread the addressed location and output the data. When a device Reset occurs, the memory defaults to Read mode.

Read Status Register Command. The Status Register indicates when a program or eras e operation is complete and the success or failure of the operation itself. Issue a Read Status Register command to read the Status Register’s contents. Subsequent Bus Read operations read the Status Register at any address, untilanother command is issued. See Table 10, S tatus Register Bits, for details on the definitions of the bits.

The R ead Status Register command may be issued at any time , even during a Program/Erase operation. Any Read atte mpt during a Program/ Erase operation will automatically output the content of the Status Register.

12/57

M36W432T, M36W432B

Read Electronic Signature Command. The

Read Electronic Signature command reads the Manufacturer and Dev ice Codes and the Block Locking Status, or the Protection Register.

The Read Electronic Signature command consists of one write cycle, a subsequent read will output the Manufacturer Code, the Device Code, the Block Lock and Lock-Down Status, o r t he Protection and Lock R egister. See Tables 4, 5 and 6 for the valid address.

Read CFI Query Command. The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area , allowing programming equipment or applications to automatically match their interface to the characteristics of thedevice.OneBusWritecycleisrequiredtoissue the Read Query C ommand. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See Appendix B, Common Flash Interface, Tables 28, 29, 30, 31, 32 and 33 f or details on the information contained in the Common Flash Interface memory area.

Block Erase Command. TheBlockErasecommandcanbeusedtoeraseablock.Itsetsallthe bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operat ion will abort, the data in the block will not be changed and the Status Register will output the error.

Two Bus Write cycles are required to issue the command.

■ Th e first bus cycle s ets up the Erasecommand.

■ Th e second la tches the block address in the

internal state machine and starts the Program/ Erase Controller.

If the seco nd bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts.

Erase abortsif Reset turns to V

. As data integrity

cannot be guaranteed when the Erase operation is aborted, the block must be erased again.

During Erase operations the memory will accept the Read Status Register command and the Program/Erase Suspen d command, all other commands will be ignored. Typical Erase times are given in Table 7, Program, E ras e Times and P r ogram/Erase Endurance Cycles.

See Appendix C, Figure 28, Erase Fl owc hart and Pseudo Code, for a suggested flowchart fo r using the Erase command.

Program Command. The memory array can be programmed word-by-word. Two bus write cycles are required to issue the Program Command.

■ Th e first bus cycle sets up the Program

command.

■ Th e secondlatchesthe Addres s andtheData to

be written and starts the Program/Erase Controller.

During Program operations the memory will accept the Read Status Regist er command and the Program/Erase S us pend command. Typical Program times are given in Table 7, Program, Erase Times and Program/Erase Endurance Cycles.

Programming aborts if Reset goes to V

. As data

integrity cannot be guaranteed when the program operation is aborted , the block containing the memory location must be erased and reprogrammed.

See Appendix C, Figure 25 , Program Flowchart and Pseudo Code, for the flowchart for using the Program command.

Double Word Program Command. This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the addres s A0. Programming should n ot be attempted when V

PPF

ed if V

is not at V

is below V

PPF

.The command canbeexecut-

PPH

but the res ult is not guar-

PPH

anteed. Three bus write cycles are necessary to issue the

Double Word Program command.

■ Th e first bus cycle sets up the Double Word

Program Command.

■ The second bus cyclelatches the A ddress and

theDataofthefirstwordtobewritten.

■ The third bus cycle la tches the A ddres s and the

Data of thesecond wordto b e written and starts the Program/Erase Controller.

Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to V

. As data integrity

cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed.

See Appendix C, Figure 26, Double Word Program Flowchart and Pseudo Code, for the flowchart for using the Double Word Program command.

Clear Status Register Command. The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One bus write cycle is required to issue the Clear Status Register command.

The bits in the Status Register do not automatically ret urn to ‘0’ when a new P rogram or Erase command is issued. The error bits in the Status Register should be c leared before attempting a new Program or Erase command.

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M36W432T, M36W432B

Program/Erase Suspend Command. The Pro-

gram/Erase Suspend c ommand is u sed to pause a Program orErase operation.One bus writecycle is required t o issue the Program/Erase c ommand and pause the Program/Erase controller.

During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array, ReadStatus Register,Read Electronic Signature and Read CFI Query commands. Additionally, if the s uspend operation was Erase then the Program, Block Lock, Block Lock-Down or Protection Program commands will also be accepted. The block being erased may be protected by issuing the B lock Protect, BlockLock or Protection Program commands. When the Program/ Erase Resume command is issued the operation will complete. Only the blocks not being erased may be read or programmed correctly.

During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by taking Chip Enable to V Reset turns to V

. Program/Erase i s aborted if

See Appendix C, Figure 27, Program or Double Word P rogram Suspend &Resume Flowchart and Pseudo Code, and Figure 29, Erase Suspend & Resume Flowchart and P s eudo Code for flowcharts for using theProgram/Erase Suspend command.

Program/Erase Resume Command. The Pro- gram/Erase Resume command can be used torestart the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the command. Once the command is issued subsequent Bus Read operations read the Status Register.

Protection Register Program Command. The Protection Register Program command is used to Program the 64 bit user One-Time-Programmable (OTP) segment of the Protection Register. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’.

Two write cycles are required to issue the Protection Register Program command.

■ Th e first bus cycle sets up the Protection

■ Th e secondlatchesthe Addres s andtheData to

be written to the Protection Register and starts the Program/Erase Controller.

Read operations output the Status Register content after the programming has started.

The segment can beprotected byprogramming bit 1 of the Protection Lock R egister. Bit 1 of t he Protection Lock Register protects bit 2 of t he Protection Lock Re gister. Programming b it 2 of the Protection Lock Registerwill result in a permanent protection of the Security Block (see Figure 6, Flash Security Block Memory Map). Attempting to program a previously protec t ed Protection Register wil l result in a Status Register error. The protection of the Protection Register and/or the Security Block is not reversible.

The Protection Register Program cannot be suspended.

Block Lock Command. The Block Lock command is used to lock a block and prevent Pr ogram or Erase operations from changing the data in it. All blocks are locked at power-up or reset.

Two Bus Write cycles are required to issue the Block Lock command.

■ Th e first bus cycle sets up the Block Lock

command.

■ The second Bus Write cycle latches the block

address.

The Lock Status can be monitored for each block using the Read Block Signature command. Table. 9 shows the Lock Status afterissuing a Block Loc k command.

The Block Lock bits are volatile, once set they remain set u ntil reset or power-down/power-up. They are c leared by a Blocks Unlock command. Refer to the section, Block Locking, for a detailed explanation.

Block Unlock Command. The Blocks Unlock command is used to unlock a block, allowing the block to be programmed orerased. Two Bus Write cycles are required to issue the Blocks Unlock command.

■ Th e first bus cycle sets up the Block Unlock

command.

■ The second Bus Write cycle latches the block

address.

The Lock Status can be monitored for each block using the Read Block Signature command. Table. 9 shows the Lock Status afterissuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation.

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M36W432T, M36W432B

Block Lock-Down Command. A locked block

cannot be Programmed or Erased, or have its Lock status changed when WP WP

is high, V

the Lock-Down function is dis-

IH,

is low, VIL. When

abled and thelocked blocks can beindividually unlocked by the Block Unlock command.

Two Bus Write cycles are required to issue the Block Lock command.

■ Th e first bus cycle sets up the Block Lock

■ The second Bus Write cycle latches the block

address.

The Lock Status can be monitored for each block using the Read B lock Signature command. Locked blocks revert to the protected (and not locked) state w hen the device is reset on powerdown. Table. 9shows the LockStatus af terissuing a Block Lock-Down comma nd. Refer to the section, Block Locking, for a detailed explanation.

command.

Table 3. Commands

Bus Write Operations

(2)

No. of

Cycles

3 Write X 30h Write Addr 1 Data Input Write Addr 2

2 Write X C0h Write

Commands

Read Memory Array 1+ Write X FFh

Read StatusRegister 1+ Write X 70h Read X

Read Electronic Signature 1+ Write X 90h Read

Read CFI Query 1+ Write 55h 98h Read CFI Addr Query

Erase 2 Write X 20h Write

Program 2 Write X

Double Word Program

Clear Status Register 1 Write X 50h Program/Erase Suspend 1 Write X B0h Program/Erase Resume 1 Write X D0h

Block Lock 2 Write X 60h Write

Block Unlock 2 Write X 60h Write

Block Lock-Down 2 Write X 60h Write

Protection Register Program

Note: X = Don't Care.

1. The signature addresses are listed in Tables 4, 5 and 6.

2. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.

1st Cycle 2nd Cycle 3nd Cycle

Bus

Op.

Addr Data

40h or

10h

Bus

Op.

Read

Write Addr Data Input

Addr Data

Read

Addr

Signature

Addr

Block

Addr

(1)

Signature

Block

Address

Block

Address

Block

Address

Data Input

Data

Status

D0h

01h

D0h

2Fh

Bus

Op.

Addr Data

Data Input

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M36W432T, M36W432B

Table 4. Read Electronic Signature

Code Device EF GF WF A0 A1 A2-A7 A8-A11 A12-A20 DQ0-DQ7 DQ8-DQ15

Manufacture Code

Device Code

Note: RPF =VIH.

M36W432T M36W432B

ILVILVIHVILVIL

ILVILVIHVIHVIL

0 Don't Care Don't Care 20h 00h

0 Don't Care Don't Care xxh 88h 0 Don't Care Don't Care xxh 88h

Table 5. Read Block Signature

Block Status EF

Locked Block Unlocked Block Locked-Down

Block

Note: 1. A Locked Block can be protected "DQ0 = 1" or unprotected "DQ0 = 0"; see Block Locking section.

GF WF A0 A1 A2-A7 A8-A20 A12-A20 DQ0 DQ1 DQ2-DQ15

ILVILVIHVILVIH

VILVILV

ILVILVIHVILVIH

IHVILVIH

0 Don't Care Block Address 1 0 00h 0 Don't Care Block Address 0 0 00h

0 Don't Care Block Address

Table 6. Read Protection Register and Lock Register

Word EF

Lock

Unique ID 0 Unique ID 1 Unique ID 2 Unique ID 3 OTP 0 OTP 1 OTP 2 OTP 3

GF WF A0-A7 A8-A20 DQ0 DQ1 DQ2 DQ3-DQ7 DQ8-DQ15

ILVILVIH

VILVILV V

ILVILVIH

80h Don't Care 0

OTP Prot.

data 81h Don't Care ID data ID data ID data ID data ID data 82h Don't Care ID data ID data ID data ID data ID data

83h Don't Care ID data ID data ID data ID data ID data 84h Don't Care ID data ID data ID data ID data ID data 85h Don't Care OTP data OTP data OTP data OTP data OTP data 86h Don't Care OTP data OTP data OTP data OTP data OTP data 87h Don't Care OTP data OTP data OTP data OTP data OTP data 88h Don't Care OTP data OTP data OTP data OTP data OTP data

Security

prot. data

(1)

00h 00h

1 00h

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M36W432T, M36W432B

Table 7. Program, Erase Times and Program/Erase Endurance Cycles

Parameter Test Conditions

Word Program Double Word Program

Main Block Program

Parameter Block Program

Main Block Erase

Parameter Block Erase

Program/Erase Cycles (per Block) 100,000 cycles

PPF=VDDF

= 12V ±5%

PPF

= 12V ±5%

PPF

PPF=VDDF

= 12V ±5%

PPF

PPF=VDDF

= 12V ±5%

PPF

PPF=VDDF

= 12V ±5%

PPF

PPF=VDDF

Flash Memory

Unit

Min Typ Max

10 200 µs 10 200 µs

0.16 5 s

0.32 5 s

0.02 4 s

0.04 4 s 110 s 110 s

0.8 10 s

Flash Block Locking

The Flash Memory features an instant, individual block locking scheme that allows any block to be lockedorunlockedwithnolatency.Thislocking scheme has three levels of protection.

■ Lock/Unlock - this first level allows softwa r e-

only control of block locking.

■ Lock-Down - this second level requires

hardware interaction before locking can be changed.

■ V

PPF

≤ V

- the third level offers a comp let e

PPLK

hardware protection againstprogram and erase on all blocks.

The locking status of each block can be set to Locked, Unlocked, and Lock-Down. The following sections explain t he operation of the locking system. Table 7, defines all of the poss ible loc king states (WP

, DQ1, DQ0), and Appendix C, Figure

30, shows a flowchart for the locking operations. Locked State. The default status of all blocks on

power-up or reset is Locked (states (0,0,1) or (1,0,1)). L oc ked blocks are fully protected from any prog ram or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be chang ed to Unlocked or Lock-Down using the appropriate software commands.An Unlockedblockcan beLockedby issuing the Lock command.

Unlocked State. Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state when the device is reset or powered-dow n. The status of an unlocked bloc k can be changed to Locked or Locked-Down using the appropriate s oftware commands. A locked block can be unlocked by issuing the Unlock command.

Lock-Down State. Blocks that are Locked-Down (state (0,1,1))are protected from program and erase operations (as for Locked blocks) but their Lock status cannot be changed using software commands alone. A Lockedor U nlock ed block can be Locked-Down by issuing the Lock-Down command. Locked-Down bloc ks revert to the Locked state when the device is reset or powered-down.

The Lock- Down function is dependent on the WPF input pin. When WPF=0 (VIL), the blocks in the Lock-Down state (0, 1,1) are protected from program, erase and lock status changes. When

=1 (VIH) the Lock- Down f unc t ion is disabled

WPF (1,1,1) and Locked-Down blocks can be individually unlocked to t he (1,1,0) state by issuing the software command , wherethey canbe erased and programmed. These blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while WPF remains high. When WPF is low, blocks that were previously Locked-Down return to the Lock-Down state (0, 1,1) regardless of any changes made while WPF

was high. Device reset or pow er-down resets all blocks, includingthose in Lock-Down, to the Locked state.

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M36W432T, M36W432B

Reading a Block’s Lock Status. The lock status

of every block can be read in the R ead Electronic Signature mode of the device. To enter this mode write90h tothe device. Subsequent reads atBlock Address 00002h wil l output the lo ck status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. it is also automatically set when entering Loc k -Down. DQ1 indicates the Lock-Down status and is s et by the Lock-Down command. It c annot b e cleared by software, only by a device reset or power-down.

Locking Operations During Erase Suspend.

Changes to block lock status c an be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when

To change block locking d uring an erase operation, first write the Erase Suspend command, then check the status register un til it indicates that the erase operation has been suspended. Next write the desired Lock command sequenc e to a block and the lockstatus will be changed. After com pleting any desired lock, read, or program operations, resume the erase operation w ith the Eras e Resume command.

If a blockis locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete.

Locking operations cannot be performed during a program suspend. Refer to Appendix D, Command Interface and Program/E ras e Controller State, for detailed inform ation on which commands are valid during erase suspend.

another block needs to be updated whi le an erase operation is in progress.

Table 8. Block Lock Status

Item Address Data

Block Lock Configuration xx002 LOCK Block is Unlocked DQ0=0 Block is Locked DQ0=1 Block is Locked-Down DQ1=1

Table 9. Lock Status

Current

Lock Status

(WPF,DQ1,DQ0)

Current State

1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0

(2)

1,0,1

1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0

(2)

0,0,1

0,1,1 no 0,1,1 0,1,1 0,1,1

Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read

in the Read Electronic Signature command with A1 = V

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WPF

3. A WPF

transition to VIHon a locked block will restore the previous DQ0 value, giving a 111 or 110.

(1)

Program/Erase

Allowed

no 1,0,1 1,0,0 1,1,1 0,0,1

no 0,0,1 0,0,0 0,1,1 1,0,1

After

Block Lock

Command

andA0=VIL.

Next Lock Status

(WPF, DQ1, DQ0)

After

Block Unlock

Command

(1)

After Block Lock-Down

Command

status.

After

transition

WPF

1,1,1 or 1,1,0

(3)

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