SGS Thomson Microelectronics M29W800AT90N6T, M29W800AT90N6, M29W800AT90N1T, M29W800AB90N1T, M29W800AB90N1 Datasheet

...

1/33March 2000

M29W800AT

M29W800AB

8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Low Voltage Single Supply Flash Memory

■ 2.7V to 3.6V SUPPLY VOLTAGEfor

PROGRAM, ERASE and READ OPERATIONS

■ ACCESS TIME: 80ns

■ PROGRAMMING TIME: 10µs typical

■ PROGRAM/ERASE CONTROLLER(P/E.C.)

– Program Byte-by-Byte or Word-by-Word – Status Register bits and Ready/Busy Output

■ SECURITY PROTECTION MEMORY AREA

■ INSTRUCTION ADDRESS CODING: 3 digits

■ MEMORY BLOCKS

– Boot Block (Top or Bottomlocation) – Parameter andMain blocks

■ BLOCK, MULTI-BLOCK and CHIP ERASE

■ MULTI BLOCK PROTECTION/TEMPORARY

UNPROTECTION MODES

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■ LOW POWER CONSUMPTION

– Stand-by and Automatic Stand-by

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ 20 YEARS DATA RETENTION

– Defectivity below 1ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code:20h – Top Device Code, M29W800AT: D7h – Bottom Device Code, M29W800AB: 5Bh

Figure 1. Logic Diagram

AI02599

A0-A18

DQ0-DQ14

M29W800AT M29W800AB

DQ15A–1 BYTE RB

FBGA

TSOP48(N)

12 x 20mm

SO44 (M)

LFBGA48 (ZA)

8 x 6 solder balls

M29W800AT, M29W800AB

2/33

Figure 2. TSOP Connections

DQ3

DQ9

DQ2

DQ0

DQ6

DQ13

A17

A10 DQ14

DQ12

DQ10

DQ15A–1

DQ4

DQ5

DQ7

NC NC

AI02179

M29W800T M29W800B

24 25

DQ8

A18

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15 A14

E A0

Figure 3. SO Connections

G DQ0 DQ8

A2 A1

A13

A14 A15

DQ7

A12

A16 BYTE

DQ15A–1

DQ5DQ2

DQ3

DQ11

DQ4

DQ14

AI02181

M29W800

M29W800B

2 3 4 5 6 7

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 2322

17DQ1

DQ9

A6 A5

DQ6 DQ13

39 38 37 36 35 34 33

A11

A10

DQ10

DQ12

42 41

A17 A8

A18

Table 1. Signal Names

A0-A18 Address Inputs DQ0-DQ7 Data Input/Outputs, Command Inputs DQ8-DQ14 Data Input/Outputs DQ15A–1 Data Input/Output or Address Input E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect RB Ready/Busy Output BYTE Byte/Word Organization V

Supply Voltage

Ground NC Not Connected Internally DU Don’t Use as Internally Connected

DESCRIPTION

TheM29W800A isa non-volatile memory that may be erased electrically at the blockor chiplevel and programmed in-system on a Byte-by-Byte or Word-by-Word basis using only a single 2.7V to

3.6V VCCsupply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers.

The array matrix organisation allowseach block to be erased and reprogrammed without affecting other blocks. Blocks can be protected against programing and erase on programming equipment, and temporarily unprotected to make changes in the application. Each block can be programmed and erased over 100,000 cycles.

Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection status, Programming, Block and Chip Erase, Erase Suspend and Resume are written to the device in cycles of commands to a Command Interface using standardmicroprocessor write timings.

The device is offered in TSOP48 (12 x 20mm), SO44 and LFBGA48 0.8 mm ball pitch packages.

3/33

M29W800AT, M29W800AB

Figure 4. LFBGA Connections (Top view through package)

AI00656

87654321

DQ15

A–1

A15A14A12A13

DQ3DQ11DQ10A18DURB

DQ1DQ9DQ8DQ0A6A17A7

GEA0 A4A3

DQ2

DQ6DQ13DQ14A10A8A9

DQ4V

DQ12DQ5DUDURPW

A11 DQ7

A1 A2 V

A16

BYTE

Memory Blocks

The devices featureasymmetrically blocked architecture providing system memoryintegration. Both M29W800AT and M29W800AB devices have an array of19blocks, one Boot Blockof 16KBytes or 8 KWords, two Parameter Blocks of 8 KBytes or 4 KWords, one Main Block of 32 KBytes or 16 KWords and fifteen Main Blocks of 64 KBytes or 32 KWords. The M29W800AT has the Boot Block at the top of the memory address space and the M29W800AB locates the Boot Block startingat the bottom. The memory maps are showed in Figure

5. Each block can be erased separately, any combi-

nation of blocks can be specified for multi-block erase or theentirechip maybe erased. The Erase operations are managed automatically by the P/ E.C. The block erase operation canbe suspended in order to read from or program to any block not being erased,and then resumed.

Block protection provides additional data security. Each block can be separately protected or unprotected against Program or Erase on programming equipment. All previously protected blocks can be temporarily unprotected in the application.

Organisation

The M29W800A is organised as 1M x8 or 512K x16 bits selectable by the BYTE signal. When BYTE is Low the Byte-wide x8 organisation is selected and the address lines are DQ15A–1 and A0-A18. The Data Input/Output signal DQ15A–1 acts as address line A–1 which selects the lower or upper Byte of the memory word for output on DQ0-DQ7, DQ8-DQ14remain at High impedance. When BYTE isHigh the memory uses the address inputs A0-A18 and the Data Input/Outputs DQ0DQ15. Memorycontrol isprovided by ChipEnable E, Output Enable G and Write Enable W inputs.

A Reset/Block Temporary Unprotection RP tri-level input provides a hardware reset when pulled Low, and when held High (at VID) temporarily unprotects blocks previously protected allowingthem to be programed and erased. Erase and Program operations are controlled by an internal Program/ Erase Controller (P/E.C.). Status Register data output onDQ7 providesa Data Polling signal, and DQ6 and DQ2 provide Toggle signals to indicate the state of the P/E.C operations. A Ready/Busy RB output indicates the completion of the internal algorithms.

M29W800AT, M29W800AB

4/33

Bus Operations

The following operations can be performed using the appropriate buscycles: Read (Array, Electronic Signature, Block Protection Status), Write command, Output Disable, Stan-by, Reset, Block Protection, Unprotection,Protection Verify, Unprotection Verify and Block Temporary Unprotection. See Tables 5and 6.

Command Interface

Instructions, made up of commands written in cycles, can begiven to the Program/Erase Controller through a Command Interface (C.I.). For added data protection,program orerase execution starts after 4 or 6 cycles. The first, second, fourth and fifth cycles are used to input Coded cycles to the C.I. This Coded sequence is the same for all Program/Erase Controller instructions. The ’Command’ itself and its confirmation,when applicable, are given on the third, fourth or sixth cycles. Any incorrect commandor anyimproper command sequence will reset the device to Read Array mode.

Instructions

Seven instructions are defined to perform Read Array, Auto Select (to read the Electronic Signature or Block Protection Status), Program, Block Erase, ChipErase, Erase Suspend and EraseResume.

The internal P/E.C. automatically handles all timing and verification of the Program and Erase operations. The Status Register Data Polling, Toggle, Error bits and the RB output may be read at any time, during programmingor erase, tomonitor the progress of the operation.

Instructions are composed of up to six cycles. The first two cycles input a Coded sequence to the Command Interface which is common to all instructions (see Table 9).

The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signatureor Block Protection Status for Read operations. Inorder to give additional data protection, the instructions for Program and Block or Chip Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (Block or Chip), the fourth and fifth cycles input a further Coded sequence before the Erase confirm command on the sixth cycle. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. When power is first applied or if VCCfalls below V

LKO

, the command in-

terface is reset to Read Array.

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions forextended periods mayaffect device reliability. Referalso to theSTMicroelectronics SURE Program and other relevantquality documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

3. Depends on range.

Symbol Parameter Value Unit

Ambient Operating Temperature

(3)

–40 to 85 °C

BIAS

Temperature Under Bias –50 to 125 °C

STG

Storage Temperature –65 to 150 °C

(2)

Input or Output Voltage –0.6 to 5 V

Supply Voltage –0.6 to 5 V

(A9, E, G, RP)

(2)

A9, E, G, RP Voltage –0.6 to 13.5 V

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M29W800AT, M29W800AB

Table 3. Top Boot Block Addresses, M29W800AT

Size

(Kbytes)

Address Range

(x8)

Address Range

(x16)

18 16 FC000h-FFFFFh 7E000h-7FFFFh 17 8 FA000h-FBFFFh 7D000h-7DFFFh 16 8 F8000h-F9FFFh 7C000h-7CFFFh 15 32 F0000h-F7FFFh 78000h-7BFFFh 14 64 E0000h-EFFFFh 70000h-77FFFh 13 64 D0000h-DFFFFh 68000h-6FFFFh 12 64 C0000h-CFFFFh 60000h-67FFFh 11 64 B0000h-BFFFFh 58000h-5FFFFh 10 64 A0000h-AFFFFh 50000h-57FFFh

9 64 90000h-9FFFFh 48000h-4FFFFh 8 64 80000h-8FFFFh 40000h-47FFFh 7 64 70000h-7FFFFh 38000h-3FFFFh 6 64 60000h-6FFFFh 30000h-37FFFh 5 64 50000h-5FFFFh 28000h-2FFFFh 4 64 40000h-4FFFFh 20000h-27FFFh 3 64 30000h-3FFFFh 18000h-1FFFFh 2 64 20000h-2FFFFh 10000h-17FFFh 1 64 10000h-1FFFFh 08000h-0FFFFh 0 64 00000h-0FFFFh 00000h-07FFFh

Table 4. Bottom Boot Block Addresses, M29W800AB

Size

(Kbytes)

Address Range

(x8)

Address Range

(x16)

18 64 F0000h-FFFFFh 78000h-7FFFFh 17 64 E0000h-EFFFFh 70000h-77FFFh 16 64 D0000h-DFFFFh 68000h-6FFFFh 15 64 C0000h-CFFFFh 60000h-67FFFh 14 64 B0000h-BFFFFh 58000h-5FFFFh 13 64 A0000h-AFFFFh 50000h-57FFFh 12 64 90000h-9FFFFh 48000h-4FFFFh 11 64 80000h-8FFFFh 40000h-47FFFh 10 64 70000h-7FFFFh 38000h-3FFFFh

9 64 60000h-6FFFFh 30000h-37FFFh 8 64 50000h-5FFFFh 28000h-2FFFFh 7 64 40000h-4FFFFh 20000h-27FFFh 6 64 30000h-3FFFFh 18000h-1FFFFh 5 64 20000h-2FFFFh 10000h-17FFFh 4 64 10000h-1FFFFh 08000h-0FFFFh 3 32 08000h-0FFFFh 04000h-07FFFh 2 8 06000h-07FFFh 03000h-03FFFh 1 8 04000h-05FFFh 02000h-02FFFh 0 16 00000h-03FFFh 00000h-01FFFh

M29W800AT, M29W800AB

6/33

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1. Address Inputs (A0-A18). The address inputs

for thememory arrayarelatched duringa writeoperation on the falling edge at Chip Enable E or Write Enable W. In Word-wide organisation the address lines are A0-A18, in Byte-wide organisation DQ15A–1 acts as an additional LSB address line. WhenA9 is raised to VID, eithera Read Electronic Signature Manufacturer or Device Code, Block Protection Status ora Write BlockProtection or BlockUnprotection isenableddepending on the combination oflevels on A0, A1,A6, A12andA15.

Data Input/Outputs (DQ0-DQ7). These Inputs/ Outputs are used in theByte-wide and Word-wide organisations. Theinput isdata to beprogrammed in the memory array ora command tobe written to the C.I.Both are latched onthe rising edge ofChip Enable E or Write Enable W. The output is data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 ortheErase Timer bitDQ3. Outputs arevalid when Chip Enable E andOutput Enable G are active. The output is high impedance when the chip is deselected or the outputs are disabled and when RP isat a Low level.

Data Input/Outputs (DQ8-DQ14 and DQ15A–

1). These Inputs/Outputs are additionally used in

the Word-wide organisation. When BYTE is High DQ8-DQ14 and DQ15A–1 act as the MSB of the Data Input or Output, functioning as described for DQ0-DQ7 above, and DQ8-DQ15 are ’don’t care’ for command inputs or status outputs. When BYTE is Low, DQ0-DQ14 are high impedance, DQ15A–1 is the Address A–1 input.

Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders andsense amplifiers.E Highdeselects the memory and reduces the power consumption to the stan-by level. E can also be used to control writing to the command register and to the memory array, while W remains at a low level. The Chip Enable must be forcedto VIDduring the Block Unprotection operation.

Output Enable (G). The Output Enable gates the outputs through the data buffersduring a read operation. When G is High the outputs are High impedance. G must be forced to VIDlevel during Block Protection and Unprotection operations.

Write Enable (W). This input controls writing to the Command Register and Address and Data latches.

Byte/WordOrganizationSelect (BYTE). The BYTE input selects the output configuration for the device: Byte-wide (x8) mode or Word-wide (x16) mode. When BYTE is Low, the Byte-wide mode is selected andthe data is read and programmed on DQ0-DQ7. In this mode, DQ8-DQ14 are at high impedance and DQ15A–1 is the LSB address. When BYTE is High, the Word-wide mode is selected and the data is read and programmed on DQ0-DQ15.

Ready/Busy Output (RB). Ready/Busy is an open-drain output and gives the internal state of the P/E.C. of thedevice. When RB is Low, the device is Busy with a Program or Erase operation and it will not accept any additional program or erase instructions except the Erase Suspend instruction. WhenRB is High,the deviceis ready for any Read, Program or Erase operation. The RB will also be Highwhen the memory is put in Erase Suspend or Stan-by modes.

Reset/Block Temporary Unprotect Input (RP).

The RP Input provides hardware reset and protected block(s) temporary unprotection functions. Reset of the memory is achieved by pulling RP to VILfor at least t

PLPX

. When the reset pulse is given, if the memory is in Read or Stan-by modes, it will be available for new operations in t

PHEL

after the rising edge of RP. If the memory is in Erase, Erase Suspend or Program modes the reset will take t

PLYH

during which the RB signal will be held at VIL. Theend of thememory reset will be indicated by the rising edge of RB. A hardware reset during an Erase or Program operation will corrupt the data being programmed or the sector(s) being erased. See Tables 15, 16, and Figure 11.

Temporary block unprotection is made by holding RP at VID. In this condition previously protected blocks can be programmed or erased. The transition of RP from VIHto VIDmust slower than t

PH-

PHH

. See Tables 17, 18, and Figure 11. When RP is returned from VIDto VIHall blocks temporarily unprotected will be again protected.

VCCSupply Voltage. The power supply for all operations (Read, Program and Erase).

VSSGround. VSSis the reference for all voltage measurements.

7/33

M29W800AT, M29W800AB

DEVICE OPERATIONS

See Tables 5, 6 and 7. Read. Read operations are used to output the

contents of the Memory Array, the Electronic Signature, theStatus Register or the BlockProtection Status. Both Chip Enable E and Output Enable G must below in ordertoread theoutput of the memory. A new operation is initiated either on the following edge of Chip Enable E or on any address transition with E at VIL.

Write. Write operations are used to give Instruction Commands to the memory or to latch input data to be programmed. A write operation is initiated whenChip Enable E isLow and Write Enable W is Low with Output Enable G High. Addresses are latchedon the falling edgeof W orEwhichever occurs last. Commands and Input Data are latched onthe rising edgeof Wor Ewhicheveroccurs first.

Output Disable. The data outputs are high impedance when the Output Enable G is High with Write Enable W High.

Stan-by. The memory is in stan-by when Chip Enable E isHigh and the P/E.C. is idle. The power consumption is reduced to the stan-by level and the outputs are high impedance, independent of the Output Enable G or Write Enable Winputs.

Automatic Stan-by. After 150ns of bus inactivity (no addresstransition, CE=VIL) andwhen CMOS levels aredriving theaddresses, the chip automatically enters a pseudo-stan-by mode where consumption is reduced to the CMOS stan-by value, while outputs stilldrive the bus (if G = VIL).

Electronic Signature. Two codes identifying the manufacturer andthe devicecan beread from the memory. The manufacturer’s code for STMicroelectronics is 20h, the device code is D7h for the M29W800AT (Top Boot) and 5Bh for the M29W800AB (Bottom Boot). These codes allow programming equipment or applications to automatically match their interface to the characteristics ofthe M29W800A. TheElectronic Signature is output by a Read operation when the voltage applied to A9 is at VIDandaddress inputs A1 isLow. The manufacturer code is output when the Address input A0 is Low and the device code when this input is High. Other Address inputs are ignored. The codes are output on DQ0-DQ7.

The Electronic Signature canalso be read, without raising A9 to VID, by giving the memory the Instruction AS. If the Byte-wide configuration is selected the codes are output on DQ0-DQ7 with DQ8-DQ14 at High impedance; if the Word-wide configuration is selected the codes are output on DQ0-DQ7 withDQ8-DQ15 at 00h.

Block Protection. Each block can be separately protected against Program or Erase on programming equipment. Block protection provides additional data security, as it disables all program or erase operations. This mode is activated when both A9 and G are raised to VIDand anaddress in the block is applied on A12-A18. Block protection is initiated on theedge ofW fallingto VIL. Then after a delay of 100µs, the edge of W rising to V

ends the protection operations. Block protection verify is achieved by bringing G, E, A0 and A6 to VILand A1 to VIH, while W is at VIHand A9 at VID. Under these conditions, reading the data output will yield 01h if the block defined by the inputs on A12-A18 is protected. Any attempt to program or erase a protected block will be ignored by the device.

Block Temporary Unprotection. Any previously protected block can be temporarily unprotected in order to change stored data. The temporary unprotection mode isactivatedby bringing RP toVID. During the temporary unprotection mode the previously protected blocks are unprotected. A block can beselected and data can bemodified by executing the Erase or Program instruction with the RP signal held at VID. When RP is returned toVIH, all the previously protected blocks are again protected.

Block Unprotection. All protected blocks can be unprotected on programming equipment to allow updating of bit contents. All blocks must first be protected before theunprotection operation. Block unprotection is activated when A9,G and E are at VIDand A12, A15 at VIH. Unprotection is initiated by the edge of W falling to VIL. After a delay of 10ms, the unprotection operation will end. Unprotection verify is achieved by bringing G and E to VILwhileA0 is at VIL, A6and A1are at VIHandA9 remains at VID. In these conditions, reading the output data willyield 00hif the block definedbythe inputs A12-A18 has been successfully unprotected. Each block must be separately verified by giving its address in order to ensure that it has been unprotected.

M29W800AT, M29W800AB

8/33

Table 5. User Bus Operations

(1)

Note: 1. X = VILor VIH.

2. Block Address must be given an A12-A18 bits.

3. See Table 7.

4. Operation performed on programming equipment.

Table 6. Read Electronic Signature (following AS instruction or with A9 = VID)

Table 7. Read Block Protection with AS Instruction

Operation E G W RP BYTE A0 A1 A6 A9 A12 A15

DQ0-

DQ7

DQ8-

DQ14

DQ15

A–1

Read Word

ILVIL

IHVIH

A0 A1 A6 A9 A12 A15

Data

Output

Data

Output

Data

Output

Read Byte

ILVIL

A0 A1 A6 A9 A12 A15

Data

Output

Hi-Z

Address

Input

Write Word

ILVIH

IHVIH

A0 A1 A6 A9 A12 A15

Data

Input

Data

Input

Data Input

Write Byte

ILVIH

A0 A1 A6 A9 A12 A15

Data

Input

Hi-Z

Address

Input

Output Disable

ILVIH

X XXXX X X Hi-Z Hi-Z Hi-Z

Stan-by

X XXXX X X Hi-Z Hi-Z Hi-Z

Reset X X X

X XXXX X X Hi-Z Hi-Z Hi-Z

Block Protection

(2,4)

VILVIDVILPulse V

X XXX

XX X X X

Blocks Unprotection

(4)

VIDVIDVILPulse V

X XXX

IDVIHVIH

XXX

Block Protection

Verify

(2,4)

VILV

ILVIHVILVID

A12 A15

Block

Protect

Status

(3)

Block Unprotection

Verify

(2,4)

VILV

ILVIHVIHVID

A12 A15

Block

Protect

Status

(3)

Block Temporary Unprotection

XX X

X XXXX X X X X X

Org. Code Device E G W BYTE A0 A1

Other

Addresses

DQ0-

DQ7

DQ8-

DQ14

DQ15

A–1

Word-

wide

Manufact.

Code

Don’t Care 20h 00h 0

Device

Code

M29W800AT

Don’t Care D7h 00h 0

M29W800AB

Don’t Care 5Bh 00h 0

Code E G W A0 A1 A12-A18

Other

Addresses

DQ0-DQ7

Protected Block

Block Address Don’t Care 01h

Unprotected Block

Block Address Don’t Care 00h

9/33

M29W800AT, M29W800AB

Table 8. Commands

Hex Code Command

00h Invalid/Reserved 10h Chip Erase Confirm 20h Reserved 30h Block Erase Resume/Confirm 80h Set-up Erase

90h

Read Electronic Signature/

Block Protection Status A0h Program B0h Erase Suspend F0h Read Array/Reset

INSTRUCTIONS AND COMMANDS

The Command Interface latches commands written to the memory. Instructions are made up from one or more commands to perform Read Memory Array, Read Electronic Signature, ReadBlockProtection, Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made of address and data sequences. The instructions requirefrom 1 to6 cycles,thefirst or first three ofwhich are always write operations used to initiate the instruction. They are followed by either further writecycles to confirm the firstcommand or execute thecommand immediately. Commandsequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The increased number of cycles has been chosentoassuremaximum datasecurity. Instructions are initialised by twoinitialCodedcycles which unlock the Command Interface. In addition, for Erase,instructionconfirmation is again preceded by the two Coded cycles.

Status Register Bits

P/E.C. statusis indicated during executionby Data Polling on DQ7, detection of Toggle on DQ6 and DQ2, or Error on DQ5 and Erase Timer DQ3 bits. Any read attempt during Program or Erase command execution will automatically output these five Status Registerbits. The P/E.C. automatically sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits (DQ0, DQ1 and DQ4) are reserved for future use and should be masked. See Tables10 and11.

Data Polling Bit (DQ7). When Programming operations are in progress, this bit outputs the complement of the bit being programmed on DQ7. During Erase operation, it outputsa ’0’. After completion ofthe operation, DQ7 will outputthebit last programmed or a ’1’ after erasing. Data Polling is valid and only effective during P/E.C. operation, that is after the fourth W pulse for programming or after the sixth W pulse for erase. It must be performed at the address beingprogrammed or at an address within the block being erased. If all the blocks selectedfor erasureare protected, DQ7 will be set to ’0’for about 100µs, and then return to the previous addressed memory data value. See Figure 13for the Data Polling flowchartand Figure 12 for the Data Polling waveforms. DQ7 will also flag the Erase Suspend mode by switching from ’0’ to ’1’ at the start of the Erase Suspend. In order to

monitor DQ7 in the Erase Suspend mode an address within a block being erased must be provided. For a Read Operation in Erase Suspend mode, DQ7 will output ’1’ if the read is attempted on a block being erased and thedata value onother blocks. DuringProgramoperation in EraseSuspend Mode, DQ7 will have the same behavior as in the normal program execution outside of the suspend mode.

Toggle Bit (DQ6). When Programming or Erasing operations are in progress, successive attempts to read DQ6 will output complementary data. DQ6 will togglefollowing toggling ofeither G, or E when G is low. The operation is completed when two successive reads yield the same output data. The next read will output the bit last programmed ora ’1’ after erasing. The toggle bitDQ6 is valid only during P/E.C. operations, that is after the fourth W pulse for programming or after the sixth W pulse for Erase. If the blocks selected for erasure are protected, DQ6 will toggle for about 100µs and then return back to Read. DQ6 will be set to ’1’ if a Read operation is attempted on an Erase Suspend block. When erase is suspended DQ6 will toggle during programming operations in a block differentto the blockin Erase Suspend. Either E or G toggling will cause DQ6 to toggle. See Figure 14 for Toggle Bit flowchart and Figure 15 for Toggle Bit waveforms.

M29W800AT, M29W800AB

10/33

Table 9. Instructions

(1)

Note: 1. Commands not interpreted in this table will default to read array mode.

2. A wait of t

PLYH

is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting anynew

operation (see Tables 15, 16 and Figure 11).

3. X = Don’t Care.

4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the command cycles.

5. Signature Address bits A0, A1, at V

will output Manufacturer code (20h). Address bits A0 at VIHand A1, at VILwilloutput Device

code.

6. Block Protection Address: A0, at V

,A1atVIHand A15-A18 within the Block will output the Block Protection status.

7. For Coded cycles address inputs A11-A18 aredon’t care.

8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout statuscan be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command isentered, read Data Polling or Toggle bit until Erase is completed or suspended.

9. Read Data Polling, Toggle bits or RB until Erase completes.

10. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.

Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.

(2,4)

Read/Reset Memory Array

Addr.

(3,7)

X Read Memory Array until anew write cycle is initiated.

Data F0h

Addr.

(3,7)

Byte AAAh 555h AAAh

Read Memory Array until a new write cycle is initiated.

Word 555h 2AAh 555h

Data AAh 55h F0h

(4)

Auto Select 3+

Addr.

(3,7)

Byte AAAh 555h AAAh

Read Electronic Signature or Block Protection Status until anew write cycle isinitiated. See Note 5 and 6.

Word 555h 2AAh 555h

Data AAh 55h 90h

PG Program 4

Addr.

(3,7)

Byte AAAh 555h AAAh

Program Address

Read Data Polling or ToggleBit until Program completes.

Word 555h 2AAh 555h

Data AAh 55h A0h

Program

Data

BE Block Erase 6

Addr.

(3,7)

Byte AAAh 555h AAAh AAAh 555h

Block

Address

Additional

Block

(8)

Word 555h 2AAh 555h 555h 2AAh

Data AAh 55h 80h AAh 55h 30h 30h

CE Chip Erase 6

Addr.

(3,7)

Byte AAAh 555h AAAh AAAh 555h AAAh

Note 9Word 555h 2AAh 555h 555h 2AAh 555h

Data AAh 55h 80h AAh 55h 10h

(10)

Erase Suspend

Addr.

(3,7)

Read until Togglestops, then read all the data needed from any Block(s) not being erased then Resume Erase.

Data B0h

Erase Resume

Addr.

(3,7)

Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time.

Data 30h

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