SGS Thomson Microelectronics M29W400BT70N6, M29W400BT70N1, M29W400BT70M1, M29W400BT55N1, M29W400BT55M1 Datasheet
...
4 Mbit (512Kb x8 or 256Kb x16, Boot Block)
Low Voltage Single Supply Flash Memory
■ SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
■ ACCESS TIME: 55ns
■ PROGRAMMING TIME
–10µs perByte/Word typical
■ 11 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 8 Main Blocks
■ PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
– Ready/Busy Output Pin
■ ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■ UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
■ TEMPORARY BLOCK UNPROTECTION
MODE
■ LOW POWER CONSUMPTION
– Standby and Automatic Standby
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ 20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29W400BT:00EEh
– Bottom Device Code M29W400BB: 00EFh
M29W400BT
M29W400BB
TSOP48 (N)
12 x 20mm
Figure 1. Logic Diagram
V
CC
18
A0-A17
W
E
G
RP
M29W400BT
M29W400BB
44
1
SO44 (M)
15
DQ0-DQ14
DQ15A–1
BYTE
RB
V
SS
AI02934
1/22April 2000
M29W400BT, M29W400BB
Figure 2. TSOP Connections
A15
A14
A13
A12
A11
A10 DQ14
NC
NC
RP
NC
NC
RB
NC
A17
1
A9
A8
W
12
M29W400BT
M29W400BB
13
A7
A6
A5
A4
A3
A2
24 25
A1
48
37
36
AI02935
A16
BYTE
V
SS
DQ15A–1
DQ7
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V
SS
E
A0
Figure 3. SO Connections
NC RP
A17 A8
V
SS
DQ0
DQ8
DQ9
DQ10
DQ3
DQ11
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
M29W400BT
E
G
M29W400BB
12
13
14
15
16
17DQ1
18
19
20
21
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
2322
AI02936
WRB
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
V
SS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5DQ2
DQ12
DQ4
V
CC
Table 1. Signal Names
A0-A17 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
E Chip Enable
G Output Enable
W Write Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
BYTE Byte/Word Organization Select
V
CC
V
SS
NC Not Connected Internally
2/22
Supply Voltage
Ground
SUMMARY DESCRIPTION
The M29W400B is a 4 Mbit (512Kb x8 or 256Kb
x16) non-volatile memory that can be read,erased
and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM. The M29W400B is fully
backward compatible with the M29W400.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data whileolddata is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands arewritten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process ofprogramming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
M29W400BT, M29W400BB
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
V
ID
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listedin the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extendedperiods may affect device reliability. Refer also to the STMicroelectronics SURE Program andother relevant quality documents.
2. Minimum Voltage mayundershoot to –2V during transition and for less than 20ns during transitions.
Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C
Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C
Temperature Under Bias –50 to 125 °C
Storage Temperature –65 to 150 °C
Input or Output Voltage –0.6 to 4 V
Supply Voltage –0.6 to 4 V
Identification Voltage –0.6 to 13.5 V
Table 3. Top Boot Block Addresses
M29W400BT
Size
#
(Kbytes)
10 16 7C000h-7FFFFh 3E000h-3FFFFh
9 8 7A000h-7BFFFh 3D000h-3DFFFh
8 8 78000h-79FFFh 3C000h-3CFFFh
7 32 70000h-77FFFh 38000h-3BFFFh
6 64 60000h-6FFFFh 30000h-37FFFh
5 64 50000h-5FFFFh 28000h-2FFFFh
4 64 40000h-4FFFFh 20000h-27FFFh
3 64 30000h-3FFFFh 18000h-1FFFFh
2 64 20000h-2FFFFh 10000h-17FFFh
1 64 10000h-1FFFFh 08000h-0FFFFh
0 64 00000h-0FFFFh 00000h-07FFFh
Address Range
(x8)
(1)
Address Range
(x16)
Table 4. Bottom Boot Block Addresses
M29W400BB
Size
#
(Kbytes)
10 64 70000h-7FFFFh 38000h-3FFFFh
9 64 60000h-6FFFFh 30000h-37FFFh
8 64 50000h-5FFFFh 28000h-2FFFFh
7 64 40000h-4FFFFh 20000h-27FFFh
6 64 30000h-3FFFFh 18000h-1FFFFh
5 64 20000h-2FFFFh 10000h-17FFFh
4 64 10000h-1FFFFh 08000h-0FFFFh
3 32 08000h-0FFFFh 04000h-07FFFh
2 8 06000h-07FFFh 03000h-03FFFh
1 8 04000h-05FFFh 02000h-02FFFh
0 16 00000h-03FFFh 00000h-01FFFh
Address Range
(x8)
Address Range
(x16)
The blocks in the memory are asymmetrically arranged, seeTables 3 and4,Block Addresses.The
first or last 64 Kbytes have been divided into four
additional blocks. The 16 KbyteBoot Blockcan be
used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can
be used for parameter storage and the remaining
32K is a small Main Block where the application
may be stored.
Chip Enable, Output Enableand Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm)
and SO44 packages and it is supplied with all the
bits erased (set to ’1’).
3/22
M29W400BT, M29W400BB
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of thesignalsconnected to this device.
Address Inputs (A0-A17). The Address Inputs
select the cells in the memory array to access during BusRead operations. During Bus Write operations they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Readoperation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves asan address
pin; DQ15A–1 Low willselect the LSB of the Word
on the other addresses, DQ15A–1 Highwill select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory,allowing BusRead and Bus Write operations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interface.
Reset /B loc kTe mp orar y Unp rote c t(RP). The Re-
set/Block TemporaryUnprotect pin can be used to
apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
t
. After Reset/Block Temporary Unprotect
PLPX
goes High, VIH, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
t
, whichever occurs last. See the Ready/Busy
RHEL
Output section, Table 17 and Figure 11, Reset/
Temporary Unprotect ACCharacteristics for more
details.
Holding RP at VIDwill temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIHtoVIDmust be slower than
t
PHPHH
.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memoryarray can be read. Ready/Busy
is high-impedance during Readmode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy becomes high-impedance. See Table 17 and Figure
11, Reset/Temporary Unprotect AC Characteristics.
During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to asinglepull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word OrganizationSe lect (BYTE) . The Byte/
Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes ofthe memory. When Byte/Word Organization Select is Low,
VIL, the memory is in 8-bit mode, when it is High,
VIH, the memory is in 16-bit mode.
VCCSupply Voltage. The VCCSupply Voltage
supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
. Thisprevents Bus Write operations from ac-
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the VCCSupply Voltage pin and the VSSGround
pin to decouple the current surges from the power
supply. ThePCB track widths must besufficient to
carry the currents required during program and
erase operations, I
CC3
.
VSSGround. The VSSGroundis thereferencefor
all voltage measurements.
4/22
M29W400BT, M29W400BB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, OutPut Disable, Standby andAutomatic Standby. See
Tables 5 and 6, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or WriteEnableare ignoredby the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 8, Read Mode AC Waveforms,
and Table 14, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Address Inputs. The Address Inputs are latched by
the CommandInterface on the falling edgeof Chip
Table 5. Bus Operations, BYTE = V
Operation E G W
Bus Read
Bus Write
Output Disable X V
Standby
Read Manufacturer
Code
Read Device Code
Note: X = VILor VIH.
V
IL
V
IL
V
IH
V
IL
V
IL
IL
V
IL
V
IH
IH
X X X Hi-Z Hi-Z
V
IL
V
IL
V
Cell Address Hi-Z Data Output
IH
V
Command Address Hi-Z Data Input
IL
V
X Hi-Z Hi-Z
IH
A0 = VIL,A1=VIL,A9=VID,
V
IH
Others V
A0 = VIH,A1=VIL,A9=VID,
V
IH
Others V
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable
or WriteEnable,whichever occurs first.OutputEnable must remain High, VIH, during the whole Bus
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 15 and 16, Write AC
Characteristics, for details of the timing requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the
Standby Supply Current, I
, Chip Enableshould
CC2
be held within VCC± 0.2V. For the Standby current
level see Table 13, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
, forProgramorErase operations un-
CC3
til the operation completes.
Address Inputs
DQ15A–1, A0-A17
or V
IL
IH
or V
IL
IH
Data Inputs/Outpu ts
DQ14-DQ8 DQ7-DQ0
Hi-Z 20h
Hi-Z
EEh (M29W400BT)
EFh (M29W400BB)
Table 6. Bus Operations, BYTE = V
Operation E G W
Bus Read V
Bus Write
Output Disable X
Standby
Read Manufacturer
Code
Read Device Code
Note: X = VILor VIH.
IL
V
IL
V
IH
V
IL
V
IL
V
IL
V
IH
V
IH
X X X Hi-Z
V
IL
V
IL
IH
Address Inputs
A0-A17
V
Cell Address Data Output
IH
V
Command Address Data Input
IL
V
X Hi-Z
IH
A0 = VIL,A1=VIL,A9=VID,
V
IH
Others V
A0 = VIH,A1=VIL,A9=VID,
V
IH
Others V
IL
IL
or V
or V
IH
IH
Data Inputs/Outpu ts
DQ15A–1, DQ14-DQ0
0020h
00EEh (M29W400BT)
00EFh (M29W400BB)
5/22
M29W400BT, M29W400BB
Automatic Standby. If CMOS levels (VCC± 0.2V)
are usedto drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, I
CC2
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications.
They require VIDto be applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 5 and 6, Bus Operations.
BlockProtection andBlocks Unprotection. Each
block can be separately protected against accidental Programor Erase. Protected blocks can be
unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on programming equipment and the other for in-system
use. For further information refer to Application
Note AN1122, Applying Protection and Unprotection to M29 Series Flash.
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operations will result in the memory returning to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-bit or 8bit mode. See either Table 7, or 8, depending on
the configuration that is being used, for a summary of the commands.
Read/Reset Command. The Read/Reset command returnsthe memory to its Read modewhere
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
If the Read/Reset command is issued during a
Block Eraseoperationor following a Programming
or Erase error then the memory will take up to
10µs to abort. Duringthe abort period no valid data
can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will
leave invalid data in the memory.
Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are required to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until another command is issued.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VILandA1 = VIL. The other address bits
may be set to either VILor VIH. The Manufacturer
Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read
operation with A0 = VIHand A1 = VIL. The other
address bits may be set to either VILor VIH. The
Device Code for the M29W400BT is 00EEh and
for the M29W400BB is 00EFh.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL,
A1 = VIH, and A12-A17 specifying the address of
the block. The otheraddress bits may beset to either VILor VIH. If the addressed block is protected
then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to oneaddress in
the memory array at a time. The command requires fourBus Write operations, the final write operation latches theaddress and data in the internal
state machine and starts the Program/Erase Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are givenin Table 9. Bus Read operations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1. One of the Erase Commands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
6/22
M29W400BT, M29W400BB
Table 7. Commands, 16-bit mode, BYTE = V
IH
Bus Write Operations
Command
Read/Reset
1X F0
3 555 AA 2AA 55 X F0
1st 2nd 3rd 4th 5th 6th
Length
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
Program
2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Table 8. Commands, 8-bit mode, BYTE = V
IL
Bus Write Operations
Command
Read/Reset
1X F0
3 AAA AA 555 55 X F0
1st 2nd 3rd 4th 5th 6th
Length
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Auto Select 3 AAA AA 555 55 AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass
Program
2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A17, DQ8-DQ14 and DQ15 are Don’t Care.
DQ15A–1 is A–1 when BYTE is V
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase
Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write
Operations until Timeout Bit is set.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory asnormal until another command is issued.
Erase Suspend. After theErase Suspend command read non-erasing memory blocks asnormal, issue Auto Select and Programcommands
on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode.
or DQ15 when BYTE is VIH.
IL
7/22
M29W400BT, M29W400BB
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memory. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these commands. Three Bus Write operations are required
to issue the UnlockBypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Un-
lock Bypass Program command can be used to
program one address in memory at a time. The
command requires two Bus Write operations, the
final write operation latches the address and data
in the internal state machine and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Program operation using the Program command. A
protected block cannot be programmed; the operation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, which leaves the device in Unlock Bypass Mode.See the Program command for details
on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operationsare required to issue the
Unlock Bypass Reset command.
Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation appears tostart but will terminate within about100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands. It isnot possible to issue any command to abort the operation. Typical chip erase
times are given in Table 9. All Bus Read operations during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.
TheChip Erase Command sets allof the bits in unprotected blocks of thememory to ’1’. All previous
data islost.
Block Erase Command. The Block Erase command can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controllerabout 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks.Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restartswhen an additionalblock is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register for
details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data unchanged.No error condition is given when protected blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
and Read/Reset commands. Typical block erase
times are given in Table 9. All Bus Read operations during the Block Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the BlockErase operation has completedthe
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. Allprevious
data in the selected blocks is lost.
8/22
M29W400BT, M29W400BB
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controller will suspend within
15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has
stopped the memory will be set toRead mode and
the Erasewill be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. Reading from blocks that
are being erased willoutput the Status Register. It
is also possible toenter the Auto Select mode: the
memorywill behave as intheAuto Selectmode on
all blocks until aRead/Reset commandreturnsthe
memory to Erase Suspend mode.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.
Erase is suspended immediately and will start immediately when the Erase Resume Command is
issued. It will not be possible to select any further
blocks for erasure after the Erase Resume.
Table 9. Program, Erase Timesand Program, Erase Endurance Cycles
(TA= 0 to 70°C or –40 to 85°C)
Parameter Min
Chip Erase (All bits in the memory set to ‘0’) 2.5 2.5 sec
Chip Erase 6 6 35 sec
Block Erase (64 Kbytes) 0.8 0.8 6 sec
Program (Byte or Word) 10 10 200 µs
Chip Program (Byte by Byte) 5.5 5.5 30 sec
Chip Program (Word by Word) 2.8 2.8 15 sec
Program/Erase Cycles (per Block) 100,000 cycles
Note: 1. TA=25°C, VCC= 3.3V.
Typ
(1)
Typical after
100k W/E Cycles
(1)
Max Unit
9/22
M29W400BT, M29W400BB
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It isalso readduringEraseSuspend when an address withinablock being erased
is accessed.
The bits in the Status Register are summarized in
Table 10, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its operation or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being programmed to DQ7. After successful completion of
the Program operation the memory returns to
Read mod and Bus Read operations from the address just programmed output DQ7, not its complemente.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase operation the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’to a’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 4, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cellwithin a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 5, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Registerisread.
Note that the Program command cannot change a
bit setat’0’ backto ’1’ and attempting to do so may
or may not set DQ5 at ’1’. In both cases, a succes-
sive Bus Read operation will show the bit isstill ’0’.
One of the Erase commands must be used to set
all the bits in a block or in the whole memory from
’0’ to ’1’.
Table 10. Status Register Bits
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB
Program Any Address DQ7 Toggle 0 – – 0
Program During Erase
Suspend
Program Error Any Address DQ7 Toggle 1 – – 0
Chip Erase Any Address 0 Toggle 0 1 Toggle 0
Block Erase before
timeout
Block Erase
Erase Suspend
Erase Error
Note: Unspecified data bits should be ignored.
Any Address DQ7 Toggle 0 – – 0
Erasing Block 0 Toggle 0 0 Toggle 0
Non-Erasing Block 0 Toggle 0 0 No Toggle 0
Erasing Block 0 Toggle 0 1 Toggle 0
Non-Erasing Block 0 Toggle 0 1 No Toggle 0
Erasing Block 1 No Toggle 0 – Toggle 1
Non-Erasing Block Data read as normal 1
Good Block Address 0 Toggle 1 1 No Toggle 0
Faulty Block Address 0 Toggle 1 1 Toggle 0
10/22
M29W400BT, M29W400BB
Figure 4. Data Polling Flowchart
START
READ DQ5 &
at VALID ADDRESS
NO
READ
at VALID ADDRESS
DQ7
DQ7
DATA
DQ5
DQ7
DATA
FAIL PASS
=
=1
=
NO
YES
DQ7
NO
YES
YES
AI03598
Figure 5. Data Toggle Flowchart
START
READ
DQ5 & DQ6
READ DQ6
DQ6
=
TOGGLE
NO
DQ5
=1
READ
TWICE
DQ6
=
TOGGLE
FAIL PASS
YES
YES
DQ6
YES
NO
NO
AI01370B
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase command. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the
Status Register is read.
During ChipEraseandBlock Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within theblocks being erased. Once theoperation
completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operationthat causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify whichblock or blocks have caused the er-
ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
11/22
M29W400BT, M29W400BB
Table 11. AC Measurement Conditions
Parameter
V
Supply Voltage
CC
M29W400B
55 70 90 / 120
3.0 to 3.6V 2.7 to 3.6V 2.7 to 3.6V
Load Capacitance (C
) 30pF 30pF 100pF
L
Input Rise and Fall Times ≤ 10ns ≤ 10ns ≤ 10ns
Input Pulse Voltages 0 to 3V 0 to 3V 0 to 3V
Input and Output Timing Ref. Voltages 1.5V 1.5V 1.5V
Figure 6. AC Testing Input Output Waveform
3V
1.5V
0V
AI01417
Figure 7. AC Testing Load Circuit
0.8V
1N914
3.3kΩ
DEVICE
UNDER
TEST
CL= 30pF or 100pF
OUT
CLincludes JIG capacitance
Table 12. Capacitance
(TA=25°C, f = 1 MHz)
Symbol Parameter Test Condition Min Max Unit
C
IN
C
OUT
Note: Sampled only, not 100% tested.
Input Capacitance
Output Capacitance V
12/22
V
=0V
IN
=0V 12 pF
OUT
6pF
AI02762
Table 13. DC Characteristics
(TA= 0 to 70°C or –40 to 85°C)
Symbol Parameter Test Condition Min
I
LI
I
LO
I
CC1
I
CC2
(1)
I
CC3
Input Leakage Current
0V ≤ V
Output Leakage Current 0V ≤ V
Supply Current (Read)
Supply Current (Standby)
Supply Current (Program/Erase)
E=V
IL
E=V
RP = V
Program/Erase
Controller active
≤ V
IN
CC
≤ V
OUT
CC
,G=VIH, f = 6MHz
± 0.2V,
CC
± 0.2V
CC
M29W400BT, M29W400BB
(2)
Typ.
410mA
30 100
Max Unit
±1
±1
µA
µA
µA
20 mA
V
V
V
V
V
V
LKO
Note: 1. Sampled only, not 100% tested.
Input Low Voltage –0.5 0.8 V
IL
Input High Voltage
IH
Output Low Voltage
OL
Output High Voltage IOH= –100µAV
OH
Identification Voltage 11.5 12.5 V
ID
I
Identification Current
ID
Program/Erase Lockout Supply
(1)
Voltage
2. T
=25°C, VCC= 3.3V.
A
I
OL
A9 = V
= 1.8mA
ID
0.7V
CC
VCC+ 0.3
0.45 V
– 0.4 V
CC
100 µA
1.8 2.3 V
V
13/22
M29W400BT, M29W400BB
Table 14. Read AC Characteristics
(TA= 0 to 70°C or –40 to 85°C)
Symbol Alt Parameter Test Condition
E=V
,
t
t
AVQV
t
ELQX
AVAV
(1)
t
t
ACC
t
Address Validto Next Address Valid
RC
Address Valid to Output Valid
Chip Enable Low to Output
LZ
Transition
G=V
E=V
G=V
G=V
IL
IL
,
IL
IL
IL
M29W400B
Unit
55 70 90 / 120
Min 55 70 90 ns
Max 55 70 90 ns
Min 0 0 0 ns
t
Chip Enable Low to Output Valid
t
ELQV
(1)
t
GLQX
t
GLQV
(1)
t
EHQZ
(1)
t
GHQZ
t
EHQX
t
GHQX
t
AXQX
t
ELBL
t
ELBH
t
BLQZ
t
BHQV
Note: 1. Sampled only, not 100% tested.
CE
t
OLZ
t
OE
t
HZ
t
DF
t
OH
t
ELFL
t
ELFH
t
FLQZ
t
FHQV
Output Enable Low to Output
Transition
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Chip Enable, Output Enable or
Address Transition to Output
Transition
Chip Enable to BYTE Low or High Max 5 5 5 ns
BYTE Low to Output Hi-Z Max 25 25 30 ns
BYTE High to Output Valid Max 30 30 40 ns
Figure 8. Read Mode AC Waveforms
A0-A17/
A–1
tAVQV tAXQX
tAVAV
VALID
G=V
E=V
E=V
G=V
E=V
Max 55 70 90 ns
IL
Min 0 0 0 ns
IL
Max 30 30 35 ns
IL
Max 20 25 30 ns
IL
Max 20 25 30 ns
IL
Min 0 0 0 ns
14/22
E
G
DQ0-DQ7/
DQ8-DQ15
BYTE
tELQV tEHQX
tELQX tEHQZ
tGLQX tGHQX
tGLQV
tBHQV
tELBL/tELBH tBLQZ
tGHQZ
VALID
AI02907
Table 15. Write AC Characteristics, Write Enable Controlled
(TA= 0 to 70°C or –40 to 85°C)
Symbol Alt Parameter
t
AVAV
t
ELWL
t
WLWH
t
DVWH
t
WHDX
t
WHEH
t
WHWL
t
AVWL
t
WLAX
t
GHWL
t
WHGL
(1)
t
WHRL
t
VCHEL
Note: 1. Sampled only, not 100% tested.
t
WC
t
CS
t
WP
t
DS
t
DH
t
CH
t
WPH
t
AS
t
AH
t
OEH
t
BUSY
t
VCS
Address Valid to Next Address Valid Min 55 70 90 ns
Chip Enable Low to Write Enable Low Min 0 0 0 ns
Write Enable Low to Write Enable High Min 40 45 45 ns
Input Validto Write Enable High Min 25 30 45 ns
Write Enable High to Input Transition Min 0 0 0 ns
Write Enable High to Chip EnableHigh Min 0 0 0 ns
Write Enable High to Write Enable Low Min 30 30 30 ns
Address Valid to Write Enable Low Min 0 0 0 ns
Write Enable Low to Address Transition Min 40 45 45 ns
Output Enable High to Write Enable Low Min 0 0 0 ns
Write Enable High to Output Enable Low Min 0 0 0 ns
Program/Erase Valid to RB Low Max 30 30 35 ns
VCCHigh to Chip Enable Low
M29W400BT, M29W400BB
M29W400B
Unit
55 70 90 / 120
Min 50 50 50 µs
Figure 9. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A17/
A–1
E
G
W
DQ0-DQ7/
DQ8-DQ15
V
CC
RB
tAVWL
tELWL
tVCHEL
VALID
tWLWHtGHWL
tDVWH
tWLAX
tWHEH
tWHGL
tWHWL
tWHDX
VALID
tWHRL
AI01869C
15/22
M29W400BT, M29W400BB
Table 16. Write AC Characteristics, Chip Enable Controlled
(TA= 0 to 70°C or –40 to 85°C)
Symbol Alt Parameter
t
AVAV
t
WLEL
t
ELEH
t
DVEH
t
EHDX
t
EHWH
t
EHEL
t
AVEL
t
ELAX
t
GHEL
t
EHGL
(1)
t
EHRL
t
VCHWL
Note: 1. Sampled only, not 100% tested.
t
WC
t
WS
t
CP
t
DS
t
DH
t
WH
t
CPH
t
AS
t
AH
t
OEH
t
BUSY
t
VCS
Address Valid to Next Address Valid Min 55 70 90 ns
Write Enable Low to Chip Enable Low Min 0 0 0 ns
Chip Enable Low to Chip Enable High Min 40 45 45 ns
Input Validto Chip Enable High Min 25 30 45 ns
Chip Enable High to Input Transition Min 0 0 0 ns
Chip Enable High to Write EnableHigh Min 0 0 0 ns
Chip Enable High to Chip Enable Low Min 30 30 30 ns
Address Valid to Chip Enable Low Min 0 0 0 ns
Chip Enable Low to Address Transition Min 40 45 45 ns
Output Enable High Chip Enable Low Min 0 0 0 ns
Chip Enable High to Output Enable Low Min 0 0 0 ns
Program/Erase Valid to RB Low Max 30 30 35 ns
VCCHigh to Write Enable Low
M29W400B
Unit
55 70 90 / 120
Min 50 50 50 µs
Figure 10. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A17/
A–1
W
G
E
DQ0-DQ7/
DQ8-DQ15
V
CC
RB
tAVEL
tWLEL
tVCHWL
VALID
tELEHtGHEL
tDVEH
VALID
tELAX
tEHWH
tEHGL
tEHEL
tEHDX
16/22
tEHRL
AI01870C
Table 17. Reset/Block Temporary Unprotect AC Characteristics
(TA= 0 to 70°C or –40 to 85°C)
Symbol Alt Parameter
(1)
t
PHWL
t
PHEL
(1)
t
PHGL
(1)
t
RHWL
(1)
t
RHEL
(1)
t
RHGL
t
PLPX
(1)
t
PHPHH
(1)
t
PLYH
Note: 1. Sampled only, not 100% tested.
t
t
t
t
VIDR
t
READY
RP High to WriteEnable Low, Chip Enable
RH
Low, Output Enable Low
RB High to WriteEnable Low, Chip Enable
RB
Low, Output Enable Low
RP Pulse Width Min 500 500 500 ns
RP
RP Rise Time to V
ID
RP Low to Read Mode
Min 50 50 50 ns
Min 0 0 0 ns
Min 500 500 500 ns
Max101010µs
Figure 11. Reset/Block Temporary Unprotect AC Waveforms
M29W400BT, M29W400BB
M29W400B
Unit
55 70 90 / 120
W,
E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
RP
tPLPX
tPHPHH
tPLYH
AI02931
17/22
M29W400BT, M29W400BB
Table 18. OrderingInformation Scheme
Example: M29W400BB 55 N 1 T
Device Type
M29
Operating Voltage
W=V
Device Function
400B = 4 Mbit (512Kb x8 or 256Kb x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
55 = 55 ns
70 = 70 ns
90 = 90 ns
120 = 120 ns
= 2.7 to 3.6V
CC
Package
N = TSOP48: 12 x 20 mm
M = SO44
Temperature Range
1=0to70°C
6=–40to85°C
Option
T = Tape& Reel Packing
Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed
parts, otherwise devices are shipped from the factorywith the memorycontent bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
18/22
Table 19. Revision History
Date Revision Details
July 1999 First Issue
Chip Erase Max. specification added (Table9)
Block Erase Max. specification added (Table 9)
09/21/99
10/04/99
01/21/00 FBGA Package removed (Table 18)
02/01/00 TSOP48 Package mechanical data change (Table20)
03/09/00
04/18/00 Status Register section clarification (Table10)
Program Max. specification added (Table 9)
Chip Program Max. specification added (Table9)
I
Typ.specification added (Table 13)
CC1
Typ.specification added (Table 13)
I
CC2
FBGA Connections change (Table 1)
I
TestCondition change (Table 13)
CC
Document type: from Preliminary Data to Data Sheet
Status Register bit DQ5 clarification
Data Polling Flowchart diagram change (Figure 4)
Data Toggle Flowchart diagram change (Figure 5)
M29W400BT, M29W400BB
19/22
M29W400BT, M29W400BB
Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
Symbol
A 1.20 0.0472
A1 0.05 0.15 0.0020 0.0059
A2 0.95 1.05 0.0374 0.0413
B 0.17 0.27 0.0067 0.0106
C 0.10 0.21 0.0039 0.0083
D 19.80 20.20 0.7795 0.7953
D1 18.30 18.50 0.7205 0.7283
E 11.90 12.10 0.4685 0.4764
e 0.50 – – 0.0197 – –
L 0.50 0.70 0.0197 0.0279
α 0° 5° 0° 5°
N48 48
CP 0.10 0.0039
Typ Min Max Typ Min Max
mm inches
Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
A2
1N
e
E
B
N/2
D1
D
DIE
A
CP
C
TSOP-a
Drawing is notto scale.
LA1 α
20/22
M29W400BT, M29W400BB
Table 21. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
Symbol
Typ Min Max Typ Min Max
A 2.42 2.62 0.0953 0.1031
A1 0.22 0.23 0.0087 0.0091
A2 2.25 2.35 0.0886 0.0925
B 0.50 0.0197
C 0.10 0.25 0.0039 0.0098
D 28.10 28.30 1.1063 1.1142
E 13.20 13.40 0.5197 0.5276
e 1.27 – – 0.0500 – –
H 15.90 16.10 0.6260 0.6339
L 0.80 – – 0.0315 – –
α 3° ––3°––
N44 44
CP 0.10 0.0039
mm inches
Figure 13. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
A2
A
C
B
e
CP
D
N
E
H
1
LA1 α
SO-b
Drawing is notto scale.
21/22
M29W400BT, M29W400BB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use ofsuch information nor for any infringement of patents or other rights of third parties whichmay result from itsuse. No licenseis granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in lifesupport devices or systems without express written approval of STMicroelectronics.
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22/22
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