The M29W400B is a 4 Mbit (512Kb x8 or 256Kb
x16) non-volatile memory that can be read,erased
and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM. The M29W400B is fully
backward compatible with the M29W400.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data whileolddata is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands arewritten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process ofprogramming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
M29W400BT, M29W400BB
Table 2. Absolute Maximum Ratings
SymbolParameterValueUnit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
V
ID
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listedin the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extendedperiods may affect device reliability. Refer also to the STMicroelectronics SURE Program andother relevant quality documents.
2. Minimum Voltage mayundershoot to –2V during transition and for less than 20ns during transitions.
Ambient Operating Temperature (Temperature Range Option 1)0 to 70°C
Ambient Operating Temperature (Temperature Range Option 6)–40 to 85°C
Temperature Under Bias–50 to 125°C
Storage Temperature–65 to 150°C
Input or Output Voltage–0.6 to 4V
Supply Voltage–0.6 to 4V
Identification Voltage–0.6 to 13.5V
The blocks in the memory are asymmetrically arranged, seeTables 3 and4,Block Addresses.The
first or last 64 Kbytes have been divided into four
additional blocks. The 16 KbyteBoot Blockcan be
used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can
be used for parameter storage and the remaining
32K is a small Main Block where the application
may be stored.
Chip Enable, Output Enableand Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm)
and SO44 packages and it is supplied with all the
bits erased (set to ’1’).
3/22
M29W400BT, M29W400BB
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of thesignalsconnected to this device.
Address Inputs (A0-A17). The Address Inputs
select the cells in the memory array to access during BusRead operations. During Bus Write operations they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Readoperation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves asan address
pin; DQ15A–1 Low willselect the LSB of the Word
on the other addresses, DQ15A–1 Highwill select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory,allowing BusRead and Bus Write operations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interface.
Reset /B loc kTe mp orar y Unp rote c t(RP). TheRe-
set/Block TemporaryUnprotect pin can be used to
apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
t
. After Reset/Block Temporary Unprotect
PLPX
goes High, VIH, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
t
, whichever occurs last. See the Ready/Busy
RHEL
Output section, Table 17 and Figure 11, Reset/
Temporary Unprotect ACCharacteristics for more
details.
Holding RP at VIDwill temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIHtoVIDmust be slower than
t
PHPHH
.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memoryarray can be read. Ready/Busy
is high-impedance during Readmode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy becomes high-impedance. See Table 17 and Figure
11, Reset/Temporary Unprotect AC Characteristics.
During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to asinglepull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word OrganizationSe lect (BYTE) . The Byte/
Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes ofthe memory. When Byte/Word Organization Select is Low,
VIL, the memory is in 8-bit mode, when it is High,
VIH, the memory is in 16-bit mode.
VCCSupply Voltage. The VCCSupply Voltage
supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
. Thisprevents Bus Write operations from ac-
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the VCCSupply Voltage pin and the VSSGround
pin to decouple the current surges from the power
supply. ThePCB track widths must besufficient to
carry the currents required during program and
erase operations, I
CC3
.
VSSGround. The VSSGroundis thereferencefor
all voltage measurements.
4/22
M29W400BT, M29W400BB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, OutPut Disable, Standby andAutomatic Standby. See
Tables 5 and 6, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or WriteEnableare ignoredby the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 8, Read Mode AC Waveforms,
and Table 14, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Address Inputs. The Address Inputs are latched by
the CommandInterface on the falling edgeof Chip
Table 5. Bus Operations, BYTE = V
OperationEGW
Bus Read
Bus Write
Output DisableXV
Standby
Read Manufacturer
Code
Read Device Code
Note: X = VILor VIH.
V
IL
V
IL
V
IH
V
IL
V
IL
IL
V
IL
V
IH
IH
XXXHi-ZHi-Z
V
IL
V
IL
V
Cell AddressHi-ZData Output
IH
V
Command AddressHi-ZData Input
IL
V
XHi-ZHi-Z
IH
A0 = VIL,A1=VIL,A9=VID,
V
IH
Others V
A0 = VIH,A1=VIL,A9=VID,
V
IH
Others V
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable
or WriteEnable,whichever occurs first.OutputEnable must remain High, VIH, during the whole Bus
Write operation. See Figures 9 and 10, Write AC
Waveforms, and Tables 15 and 16, Write AC
Characteristics, for details of the timing requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the
Standby Supply Current, I
, Chip Enableshould
CC2
be held within VCC± 0.2V. For the Standby current
level see Table 13, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
, forProgramorErase operations un-
CC3
til the operation completes.
Address Inputs
DQ15A–1, A0-A17
or V
IL
IH
or V
IL
IH
Data Inputs/Outpu ts
DQ14-DQ8DQ7-DQ0
Hi-Z20h
Hi-Z
EEh (M29W400BT)
EFh (M29W400BB)
Table 6. Bus Operations, BYTE = V
OperationEGW
Bus ReadV
Bus Write
Output DisableX
Standby
Read Manufacturer
Code
Read Device Code
Note: X = VILor VIH.
IL
V
IL
V
IH
V
IL
V
IL
V
IL
V
IH
V
IH
XXXHi-Z
V
IL
V
IL
IH
Address Inputs
A0-A17
V
Cell AddressData Output
IH
V
Command AddressData Input
IL
V
XHi-Z
IH
A0 = VIL,A1=VIL,A9=VID,
V
IH
Others V
A0 = VIH,A1=VIL,A9=VID,
V
IH
Others V
IL
IL
or V
or V
IH
IH
Data Inputs/Outpu ts
DQ15A–1, DQ14-DQ0
0020h
00EEh (M29W400BT)
00EFh (M29W400BB)
5/22
M29W400BT, M29W400BB
Automatic Standby. If CMOS levels (VCC± 0.2V)
are usedto drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, I
CC2
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications.
They require VIDto be applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 5 and 6, Bus Operations.
BlockProtection andBlocks Unprotection. Each
block can be separately protected against accidental Programor Erase. Protected blocks can be
unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on programming equipment and the other for in-system
use. For further information refer to Application
Note AN1122, Applying Protection and Unprotection to M29 Series Flash.
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operations will result in the memory returning to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-bit or 8bit mode. See either Table 7, or 8, depending on
the configuration that is being used, for a summary of the commands.
Read/Reset Command. The Read/Reset command returnsthe memory to its Read modewhere
it behaves like a ROM or EPROM. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
If the Read/Reset command is issued during a
Block Eraseoperationor following a Programming
or Erase error then the memory will take up to
10µs to abort. Duringthe abort period no valid data
can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will
leave invalid data in the memory.
Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are required to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until another command is issued.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VILandA1 = VIL. The other address bits
may be set to either VILor VIH. The Manufacturer
Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read
operation with A0 = VIHand A1 = VIL. The other
address bits may be set to either VILor VIH. The
Device Code for the M29W400BT is 00EEh and
for the M29W400BB is 00EFh.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL,
A1 = VIH, and A12-A17 specifying the address of
the block. The otheraddress bits may beset to either VILor VIH. If the addressed block is protected
then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to oneaddress in
the memory array at a time. The command requires fourBus Write operations, the final write operation latches theaddress and data in the internal
state machine and starts the Program/Erase Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are givenin Table 9. Bus Read operations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1. One of the Erase Commands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
6/22
M29W400BT, M29W400BB
Table 7. Commands, 16-bit mode, BYTE = V
IH
Bus Write Operations
Command
Read/Reset
1X F0
3555AA2AA55XF0
1st2nd3rd4th5th6th
Length
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Auto Select3555AA2AA5555590
Program4555AA2AA55555A0PAPD
Unlock Bypass3555AA2AA5555520
Unlock Bypass
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A17, DQ8-DQ14 and DQ15 are Don’t Care.
DQ15A–1 is A–1 when BYTE is V
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase
Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write
Operations until Timeout Bit is set.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory asnormal until another command is issued.
Erase Suspend. After theErase Suspend command read non-erasing memory blocks asnormal, issue Auto Select and Programcommands
on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode.
or DQ15 when BYTE is VIH.
IL
7/22
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