SGS Thomson Microelectronics M29W320DT, M29W320DB Datasheet
32 Mbit (4Mb x8 or 2Mb x16, Boot Block)
FEATURES SUMMARY
■ SUPPLY VOLTAGE
–V
–V
■ ACCESS TIME: 70, 90ns
■ PROGRAMMING TIME
– 10µs per Byte/Word typical
■ 67 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 64 Main Blocks
■ PROGRAM/ERA SE CON T ROL LER
– Embedded Byte/Word Program algorithms
■ ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
■ UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programm ing
■ V
PP
PROTECT
■ TEMPORARY BLOCK UNPROTECTION
MODE
■ COMMON FLASH INTERFACE
– 64 bit Security Code
■ LOW POWER CONSUMPTION
– Standby and Automatic Standby
■ 100,000 PROGRAM/ER ASE CYCL ES per
BLOCK
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29W320DT: 22CAh
– Bottom Device Code M29W320DB: 22CBh
2.7V to 3.6V for Program, Erase and
CC =
Read
=12V for Fast Program (optional)
PP
Erase Suspend
/WP PIN for FAST PROGRAM and W R IT E
M29W32 0DT
M29W320D B
3V Supply Fl ash Mem ory
Figure 1. Packages
TSOP48 (N)
12 x 20mm
FBGA
TFBGA63 (ZA)
63 ball array
1/44May 2003
M29W320DT, M29W320DB
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Inputs/Outputs (DQ8-DQ14 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Input/Output or Address Input (DQ15A–1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
V
Write Protect (V
PP/
Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
V
Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
CC
V
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SS
WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PP/
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 2. Bus Operations, BYTE = V
Table 3. Bus Operations, BYTE = V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
IL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
IH
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2/44
M29W320DT, M29W320DB
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5
Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Erase Suspend Comma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Commands, 16-bit mode, BYTE = V
Table 5. Commands, 8-bit mode, BYTE = V
Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 19
STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
IH
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
IL
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 10. Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4
Figure 11. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. Accelerated Program Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline . 29
Figure 16. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline . 29
Figure 17. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Outline . . . . . . . . . . 30
Table 17. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data . . . 30
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3/44
M29W320DT, M29W320DB
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. Top Boot Block Addresses, M29W320DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20. Bottom Boot Block Addresses, M29W320DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 22. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 23. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 24. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 25. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 26. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
APPENDIX C. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 27. Programmer Technique Bus Operations, BYTE = V
Figure 18. Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 19. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 20. In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 21. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
or VIL . . . . . . . . . . . . . . . . . . . . . 38
IH
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 28. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4/44
SUMMARY DESCRIPTION
The M29W320D is a 32 Mbit (4Mb x8 or 2Mb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is pos sible to pres erve
valid data while old data is erased. Each block can
be protected independently to prev ent accidental
Program or Erase commands from modifying the
memory. Program and Erase com m ands are wri tten to the Command Interface of t he memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase op eration can be de tected
and any error conditions identified. The command
M29W320DT, M29W320DB
set required to control the memory is consistent
with JEDEC standards.
The blocks in the memory are asymmetrically arranged, see Figures 5 and 6 and Tables 19 and
20. The first or last 64 K bytes have been di vided
into four additional blocks. The 16 Kbyte Boot
Block can be u sed for small initialization code to
start the microprocessor, the two 8 Kbyte Parameter Blocks ca n be used f or parameter st orage and
the remaining 32 Kbyte is a small Main Block
where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.
They allow simple conne ction to most microprocessors, often without additional logic.
The memory is offer ed in TSOP48 (12 x 20mm) and
TFBGA63 (7x11mm, 0.8mm pitch) packages. The
memory is supplied with all the bits erased (set to
1).
Figure 2. Logic Diagram Table 1. Signal Names
A0-A20 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
VPP/WP
V
A0-A20
RP
BYTE
W
CC
21
E
G
M29W320DT
M29W320DB
V
SS
15
DQ0-DQ14
DQ15A–1
RB
AI90189B
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
E
G
W
RP
RB
BYTE
V
CC
VPP/WP V
V
SS
NC Not Connected Internally
Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organization Select
Supply Voltage
/Write Protect
PP
Ground
5/44
M29W320DT, M29W320DB
Figure 3. TSOP Connections
A15
1
48
A14
A13
A12
A11
A10 DQ14
A9
A8
A19
A20
W
RP
NC
12
M29W320DT
M29W320DB
13
37
36
VPP/WP
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
24 25
AI90190
A16
BYTE
V
SS
DQ15A–1
DQ7
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V
SS
E
A0
6/44
Figure 4. TFBGA Connections (Top view through package)
M29W320DT, M29W320DB
654321
A
B
NC
NC
(1)
(1)
C
D
E
F
G
H
NC
A3
A4
A2
A1
A0
(1)
A7
A17
A6
RB
V
/
PP
A18
A5 A20
DQ0
E
DQ8
DQ2
DQ10
WP
W
RP
NC
A19
DQ5
DQ12
A9
A8
A10
A11
DQ7
DQ14
NC
NC
A13
A12
A14
A15
A16
BYTE
(1)
(1)
NC
NC
87
(1)
(1)
J
K
L
NC
M
NC
G
V
SS
(1)
NC
(1)
NC
DQ9
DQ1
(1)
(1)
DQ11
DQ3
V
CC
DQ4
Note: 1. Balls ar e shorted toget her via the su bstrate but no t c onnected to the di e.
DQ13
DQ6
DQ15
A–1
V
SS
NC
NC
NC
NC
(1)
(1)
AI05525B
(1)
(1)
7/44
M29W320DT, M29W320DB
Figure 5. Block Addresses (x8)
M29W320DT
Top Boot Block Addresses (x8)
3FFFFFh
3FC000h
3FBFFFh
3FA000h
3F9FFFh
3F8000h
3F7FFFh
3F0000h
3EFFFFh
3E0000h
01FFFFh
010000h
00FFFFh
000000h
16 KByte
8 KByte
8 KByte
32 KByte
64 KByte
64 KByte
64 KByte
Total of 63
64 KByte Blocks
Bottom Boot Block Addresses (x8)
3FFFFFh
3F0000h
3EFFFFh
3E0000h
01FFFFh
010000h
00FFFFh
008000h
007FFFh
006000h
005FFFh
004000h
003FFFh
000000h
M29W320DB
64 KByte
64 KByte
64 KByte
32 KByte
8 KByte
8 KByte
16 KByte
Total of 63
64 KByte Blocks
Note: Also see A ppendix A, Tab l es 19 and 20 for a ful l l isting of the Block Address es.
AI90192
8/44
Figure 6. Block Addresses (x16)
M29W320DT, M29W320DB
Top Boot Block Addresses (x16)
1FFFFFh
1FE000h
1FDFFFh
1FD000h
1FCFFFh
1FC000h
1FBFFFh
1F8000h
1F7FFFh
1F0000h
00FFFFh
008000h
007FFFh
000000h
M29W320DT
8 KWord
4 KWord
4 KWord
16 KWord
32 KWord
32 KWord
32 KWord
Total of 63
32 KWord Blocks
Bottom Boot Block Addresses (x16)
1FFFFFh
1F8000h
1F7FFFh
1F0000h
00FFFFh
008000h
007FFFh
004000h
003FFFh
003000h
002FFFh
002000h
001FFFh
000000h
M29W320DB
32 KWord
32 KWord
32 KWord
16 KWord
4 KWord
4 KWord
8 KWord
Total of 63
32 KWord Blocks
Note: Also see A ppendix A, Tab l es 19 and 20 for a ful l l isting of the Block Address es.
AI90193
9/44
M29W320DT, M29W320DB
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Sign al
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A20). The Address Inputs select the cells i n the memory array to a ccess during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine.
Data Inputs/Outputs (DQ8-DQ14). The Data I/O outputs the data stored at the selected address during a Bus Read operation when B Y TE V
. When BYTE is Low, VIL, these pins are not
IH
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output o r Address Input (DQ15A –1).
When BYTE
is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
is Low, VIL, this pin behaves as an address
BYTE
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE
is High and ref erences to the Address Inputs to include this pin when BYTE
when stated explicitly otherwise.
Chip Enable (E
). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is
High, V
Output Enable (G
, all other pins are ignored.
IH
). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W
). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interf a c e .
V
Write Protect (VPP/WP). The VPP/Write
PP/
Protect
pin provides two functions. The VPP function allo ws the memory to use an exte rnal high
volt age power s upply to r educe th e time requ ired
for Unlock Bypass Program operations. The
Write P ro tec t func ti on pr ov i des a ha rd ware met hod of protecting the 16 Kbyte Boot Block. The
V
/Write Protect pin must not be left floating or
PP
unconnected.
When V
/Write Protect is L ow , VIL, the memory
PP
protects the 16 Kbyte Boot Block; Program and
Erase operations in this block are ignored while
/Write Protect is Low.
V
PP
is High,
is Low except
When V
/Write Protect is High, VIH, the memo r y
PP
reverts to the previous protection status of the 16
Kbyte boot block. Pr ogram and Eras e operations
can now modify the data in the 16 Kbyte Boot
Block unless the block is protected using Block
Protection.
When V
/Write Protect is raised to V
PP
the mem-
PP
ory automatically enters the Unlock Bypass mode.
When V
/Write Protect returns to VIH or VIL nor-
PP
mal operation resumes. During Unlock Bypass
Program operations the memory draws I
PP
from
the pin to supply the programming circuits. See the
description of the Unlock Bypass comm and in the
Command Interface section. The transitions from
V
to VPP and from VPP to VIH must be slower
IH
than t
Never raise V
, see Figure 15.
VHVPP
/Write Protect to VPP from any
PP
mode except Read m ode, otherwise the memory
may be left in an indeterminate state.
A 0.1µF capacitor should be connected between
the V
/Write Protect pin and the VSS Ground pin
PP
to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Unlock Bypass
Program, I
PP
.
Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that hav e b een protected.
Note that if V
/WP is at VIL, then the 16 KByte
PP
outermost boot block will remain protect even if RP
ID
.
is at V
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
t
. After Reset/Block Temporary Unprotect
PLPX
goes High, V
, the memory will be ready for Bus
IH
Read and Bus Write operations after t
t
, whichever occurs last. See the Ready/Busy
RHEL
, for at least
IL
PHEL
or
Output section, Table 15 and Figure 14, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP
at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
t
PHPHH
.
Ready/Busy Output (RB
to VID must be slower than
IH
). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V
. Ready/Busy is high-im-
OL
pedance during Read mode, Auto Select mode
and Erase Suspend mode.
10/44
M29W320DT, M29W320DB
Note that if VPP/WP is at VIL, then the 16 KByte
outermost boot block will remain protect even if RP
is at V
ID
.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy becomes high-impedance. See Tabl e 15 and Figure
14, Reset/Temporary Unprotect AC Ch aracteristics .
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE
). The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 Bus modes of the
memory. When Byte/Word Organizati on Select is
Low, V
High, V
, the memory is in x8 mode, when it is
IL
, the memory is in x16 mode.
IH
V
Supply Voltage (2.7V to 3.6V). VCC pro-
CC
vides the power supply for all operations (Read,
Program and Erase).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the L ockout Voltage,
V
. This prevents Bus Write operations from ac-
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
Supply Voltage pin and the VSS Ground
CC
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
Erase operations, I
Ground. VSS is the reference for all voltage
V
SS
CC3
.
measurements.
11/44
M29W320DT, M29W320DB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Wri te, Output Disable, Standby and Automatic Standby. See
Tables 2 and 3, Bus Operat ions, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low sig nal, V and Output Enable and keeping Write Enable High, V
. The Data Inputs/Outputs will output the
IH
value, see Figure 11, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desire d address on t he Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs a re latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
IH
Write operation. See Figures 12 and 13, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing requirements.
Output Disa bl e . The Data Inputs/Outputs are in the high impedance s tate when Output Enable is High, V
.
IH
Standby. When Chip Enable is High, V memory enters Standby mode and the Data In-
, to Chip Enable
IL
, during the whole Bus
, the
IH
puts/Outputs pins are placed in the high-impedance state. To reduce the S upply Current to the
Standby Supply Current, I
be held within V
± 0.2V. For the Standby current
CC
, Chip Enable should
CC2
level see Table 11, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
, for Program or Erase operations un-
CC3
til the operation completes. Automatic Standby. If CMOS levels (V
± 0.2V)
CC
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, I
CC2
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protec tion. These bus operations are intended for use by programming equipment and are not usually used in applications.
They require V
to be applied to some pins.
ID
Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying t he signals listed in Tables 2 and 3, Bus Operations.
Block Protect and Chip Unprotect.
Each block
can be separately protected against accidental
Program or Erase. T he whole chip can be unprotected to allow the data inside the blocks to be
changed.
Block Protect and Chip Unprote ct operations are
described in Appendix C.
12/44
M29W320DT, M29W320DB
Table 2. Bus Operations, BYTE = V
Operation E G W
Bus Read
Bus Write
Output Disable X
Standby
Read Manufacturer
Code
Read Device Code
Note: X = VIL or VIH.
V
V
V
V
V
V
IL
IL
IH
IL
IL
IL
V
IH
V
IH
X X X Hi-Z Hi-Z
V
IL
V
IL
Table 3. Bus Operations, BYTE = V
Operation E
Bus Read
Bus Write
Output Disable X
Standby
Read Manufacturer
Code
Read Device Code
Note: X = VIL or VIH.
V
V
V
V
V
G W
V
IL
IL
IH
IL
IL
IL
V
IH
V
IH
X X X Hi-Z
V
IL
V
IL
IL
Address Inputs
DQ15A–1, A0-A20
V
Cell Address Hi-Z Data Output
IH
V
Command Address Hi-Z Data Input
IL
V
X Hi-Z Hi-Z
IH
A0 = VIL, A1 = VIL, A9 = VID,
V
IH
Others V
A0 = VIH, A1 = VIL,
V
IH
A9 = V
IH
or V
IL
IH
, Others VIL or V
ID
IH
Address Inputs
A0-A20
V
Cell Address Data Output
IH
V
Command Address Data Input
IL
V
X Hi-Z
IH
A0 = VIL, A1 = VIL, A9 = VID,
V
IH
Others V
A0 = VIH, A1 = VIL, A9 = VID,
V
IH
Others V
IL
IL
or V
or V
IH
IH
Data Inputs/Outputs
DQ14-DQ8 DQ7-DQ0
Hi-Z 20h
Hi-Z
CAh (M29W320DT)
CBh (M29W320DB)
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
0020h
22CAh (M29W320DT)
22CBh (M29W320DB)
13/44
M29W320DT, M29W320DB
COMMAND INTERFACE
All Bus Write operations t o the me mory are in terpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operations will result in the memory returning to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-bit or 8bit mode. See either Table 4, or 5, de pending on
the configuration that is being used, for a summary
of the commands.
Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select comma nd is issued the memory remains in Auto S elect mode until a Read/Reset command is issued. Read CFI Query and Read/ Reset commands are accepted in Auto Select mode, all other commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V
may be set to either V
Code for STMicroelectronics is 0020h.
The Device Code can be read using a B us Read
operation with A0 = V
address bits may be set to e ither V
Device Code for the M29W320DT is 22CAh and
for the M29W320DB is 22CBh.
The Bl ock Protection S tatus o f each block can be
read using a Bus Read operation with A0 = V
A1 = V
the bl ock. The oth er addr ess bit s may b e set t o either V
IL
then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output.
Read CFI Query Command. The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This
and A1 = VIL. The other address bits
IL
, and A 12 -A 20 spec ifyi ng the ad dress of
IH
or VIH. The Manufa cturer
IL
and A1 = VIL. The other
IH
or VIH. The
IL
or VIH. If t h e ad dr ess ed b loc k is pro tec te d
IL
command is valid when the device i s in the Read
Array mode, or when the device is i n Autoselected
mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is issued subsequent Bus Read ope rations read from
the Common Flash Interface Memory Area.
The Read/Reset command m ust be issued to return the device to the previous mode (the Read Array mode or Autoselected mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Autoselected mode.
See Appendix B, Tables 21, 22, 23, 24, 25 and 26
for details on the information contained in the
Common Flash Interface (CFI) memory area.
Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.
If the address falls in a pro tected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operat ion the memo ry will ignore all commands. I t is n ot poss ible t o iss ue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read operations during the program o peration will output
the Status Register on the Data Inputs/Outputs.
See the section on the S tatus Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unle ss an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ bac k to ’1’. One of the E rase Commands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock
,
Bypass Program command to program the memory. When the cycle time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these commands. Three Bus Write operations are requ ired
to issue the Unlock Bypass command.
Once the Unlock Bypas s command has bee n issued the memory will only accept the Unloc k By-
14/44
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