SGS Thomson Microelectronics M29W200BT, M29W200BB Datasheet

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PRELIMINARY DATA

March 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M29W200BT

M29W200BB

2 Mbit (256Kb x8 or 128Kb x16, Boot Block)

Low Voltage Single Supply Flash Memory

■ SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS

■ ACCESS TIME: 55ns

■ PROGRAMMING TIME

–10µs per Byte/Word typical

■ 7 MEMORY BLOCKS

– 1 Boot Block (Top or Bottom Location) – 2 Parameter and 4 Main Blocks

■ PROGRAM/ERASE CONTROLLER

– Embedded Byte/Word Program algorithm – Embedded Multi-Block/Chip Erase algorithm – Status Register Polling and Toggle Bits – Ready/Busy Output Pin

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

■ TEMPORARY BLOCK UNPROTECTION

MODE

■ LOW POWERCONSUMPTION

– Standby and Automatic Standby

■ 100,000 PROGRAM/ERASE CYCLESper

BLOCK

■ 20 YEARS DATA RETENTION

– Defectivity below 1 ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h – Top Device Code M29W200BT: 0051h – Bottom Device Code: M29W200BB 0057h

TSOP48 (N)

12 x 20mm

SO44 (M)

Figure 1. Logic Diagram

AI02948

A0-A16

DQ0-DQ14

M29W200BT M29W200BB

DQ15A–1 BYTE RB

M29W200BT, M29W200BB

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Figure 2. TSOP Connections

DQ3

DQ9

DQ2

DQ0

DQ6

DQ13

A10 DQ14

DQ12

DQ10

DQ15A–1

DQ4

DQ5

DQ7

NC NC

AI02944

M29W200BT M29W200BB

24 25

DQ8

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15 A14

E A0

Figure 3. SO Connections

G DQ0 DQ8

A2 A1

A13

A14 A15

DQ7

A12

A16 BYTE

DQ15A–1

DQ5DQ2

DQ3

DQ11

DQ4

DQ14

WRB

NC RP

AI02945

M29W200BT M29W200BB

2 3 4 5 6 7

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 2322

17DQ1

DQ9

A6 A5

DQ6 DQ13

39 38 37 36 35 34 33

A11

A10

DQ10

DQ12

42 41

NC A8

Table 1. Signal Names

A0-A16 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8-DQ14 Data Inputs/Outputs DQ15A–1 Data Input/Output or Address Input E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect RB Ready/Busy Output BYTE Byte/Word Organization Select V

Supply Voltage

Ground

NC Not Connected Internally

SUMMARY DESCRIPTION

The M29W200B is a 2 Mbit (256Kb x8 or 128Kb x16) non-volatile memorythat canbe read,erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read inthe same way as a ROM or EPROM. The M29W200B is fully backward compatible with the M29W200.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while olddata is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands arewritten to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasingthe memoryby taking care of all of the specialoperations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.

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M29W200BT, M29W200BB

The blocks in the memory are asymmetrically arranged, seeTables 3 and 4,Block Addresses.The first or last 64 Kbytes have been divided into four additional blocks. The16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored.

Chip Enable, Output Enableand Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.

The memory is offered in TSOP48 (12 x 20mm) and SO44 packages and it is supplied with all the bits erased (set to ’1’).

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device atthese or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periodsmay affect device reliability. Referalso tothe STMicroelectronics SUREProgram and other relevant quality documents.

2. Minimum Voltage may undershoot to –2V during transition and for lessthan 20ns during transitions.

Symbol Parameter Value Unit

Ambient Operating Temperature (TemperatureRange Option 1) 0 to 70 °C Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C

BIAS

Temperature Under Bias –50 to 125 °C

STG

Storage Temperature –65 to 150 °C

(2)

Input or Output Voltage –0.6 to 4 V

Supply Voltage –0.6 to 4 V

Identification Voltage –0.6 to 13.5 V

Table 3. Top Boot Block Addresses M29W200BT

Size

(Kbytes)

Address Range

(x8)

Address Range

(x16)

6 16 3C000h-3FFFFh 1E000h-1FFFFh 5 8 3A000h-3BFFFh 1D000h-1DFFFh 4 8 38000h-39FFFh 1C000h-1CFFFh 3 32 30000h-37FFFh 18000h-1BFFFh 2 64 20000h-2FFFFh 10000h-17FFFh 1 64 10000h-1FFFFh 08000h-0FFFFh 0 64 00000h-0FFFFh 00000h-07FFFh

Table 4. Bottom Boot Block Addresses M29W200BB

Size

(Kbytes)

Address Range

(x8)

Address Range

(x16)

6 64 30000h-3FFFFh 18000h-1FFFFh 5 64 20000h-2FFFFh 10000h-17FFFh 4 64 10000h-1FFFFh 08000h-0FFFFh 3 32 08000h-0FFFFh 04000h-07FFFh 2 8 06000h-07FFFh 03000h-03FFFh 1 8 04000h-05FFFh 02000h-02FFFh 0 16 00000h-03FFFh 00000h-01FFFh

M29W200BT, M29W200BB

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SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Signal Names, fora brief overview ofthesignals connected to this device.

Address Inputs (A0-A16). The Address Inputs select the cells in the memoryarray to access during Bus Read operations. During BusWrite operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs outputthe datastored at the selected address during a Bus Readoperation. DuringBus Write operations they represent the commands sent tothe Command Interface of theinternal state machine.

Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs outputthe datastored at the selected address during a Bus Readoperation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and arehigh impedance.During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored.

Data Input/Output or Address Input (DQ15A-1).

When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves asan address pin; DQ15A–1 Low willselect the LSB of the Word on the other addresses, DQ15A–1 Highwill select the MSB. Throughout thetext consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates the memory,allowing BusRead and Bus Writeoperations to be performed. When Chip Enable is High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

Reset/BlockTemporaryUnprotect(RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or totemporarily unprotect all Blocks that have been protected.

A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least t

PLPX

. After Reset/Block Temporary Unprotect goes High,VIH, the memory will be ready for Bus Read and Bus Write operations after t

PHEL

RHEL

, whicheveroccurs last. See the Ready/Busy Output section, Table 17 and Figure 11, Reset/ Temporary Unprotect AC Characteristics for more details.

Holding RP at VIDwill temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition fromVIHtoVIDmustbe slower than t

PHPHH

Ready/Busy Output (RB). The Ready/Busy pin is anopen-drain output that can beused to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode,Auto Select mode and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 17 and Figure 11, Reset/Temporary Unprotect AC Characteristics.

During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode.

The use ofan open-drain output allowsthe Ready/ Busy pins fromseveral memories tobe connected to asingle pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.

Byte/WordOrganizationSelect(BYTE). The Byte/ Word OrganizationSelect pinis used to switch between the 8-bitand 16-bit Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in 8-bit mode, when it is High, VIH, the memory is in 16-bit mode.

VCCSupply Voltage. The VCCSupply Voltage supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabledwhen the V

Supply Voltage is less than the Lockout Voltage, V

LKO

. Thisprevents Bus Write operationsfrom accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming orerasing during this time thenthe operation aborts and the memory contents being altered will be invalid.

A 0.1µF capacitor should be connected between the VCCSupply Voltage pin and the VSSGround pin to decouplethe current surges from the power supply. The PCB track widthsmust be sufficient to carry the currents required during program and erase operations, I

CC3

VSSGround. The VSSGroundis thereference for all voltage measurements.

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M29W200BT, M29W200BB

Table 5. Bus Operations, BYTE = V

Note: X = VILor VIH.

Table 6. Bus Operations, BYTE = V

Note: X = VILor VIH.

Operation E G W

Address Inputs

DQ15A–1, A0-A16

Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Bus Read

Cell Address Hi-Z Data Output

Bus Write

Command Address Hi-Z Data Input

Output Disable X

X Hi-Z Hi-Z

Standby

X X X Hi-Z Hi-Z

Read Manufacturer Code

A0 = VIL,A1=VIL,A9=VID, Others V

or V

Hi-Z 20h

Read Device Code V

A0 = VIH,A1=VIL,A9=VID, Others V

or V

Hi-Z

51h (M29W200BT) 57h (M29W200BB)

Operation E G W

Address Inputs

A0-A16

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Bus Read

Cell Address Data Output

Bus Write

Command Address Data Input

Output Disable X

X Hi-Z

Standby

X X X Hi-Z

Read Manufacturer Code

A0 = VIL,A1=VIL,A9=VID, Others V

or V

0020h

Read Device Code

A0 = VIH,A1=VIL,A9=VID, Others V

or V

0051h (M29W200BT) 0057h (M29W200BB)

BUS OPERATIONS

There are five standardbusoperations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Tables 5 and 6, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or WriteEnable areignored by the memory and do not affect bus operations.

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desiredaddress on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 8, Read Mode AC Waveforms, and Table 14, Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the CommandInterface on the falling edgeof Chip

Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable,whichever occursfirst.OutputEnable must remain High, VIH, during the whole Bus Write operation. See Figures 9 and 10, Write AC Waveforms, and Tables 15 and 16, Write AC Characteristics, for details of the timing requirements.

Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.

Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, I

CC2

, Chip Enable should be held within VCC± 0.2V. For the Standby current level see Table 13, DC Characteristics.

During program or erase operations the memory will continue to use the Program/Erase Supply Current, I

CC3

, for Program orErase operationsun-

til the operation completes.

M29W200BT, M29W200BB

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AutomaticStandby. If CMOSlevels (VCC± 0.2V) are usedto drive thebus and the busis inactivefor 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, I

CC2

. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VIDto be applied to some pins.

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 5 and 6, Bus Operations.

Block Protection andBlocksUnprotection. Each block can be separately protected against accidental Program or Erase.Protected blocks can be unprotected to allow data to be changed.

There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash.

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security.

The address used for the commandschanges depending on whether the memory is in 16-bit or 8bit mode. See either Table 7, or 8, depending on the configurationthat isbeing used, for a summary of the commands.

Read/Reset Command. The Read/Reset command returns the memory toits Read modewhere it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command.

If the Read/Reset command is issued during a Block Eraseoperation or followinga Programming or Eraseerror then the memory will takeup to10µs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.

Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another command is issued.

From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VILandA1 = VIL. The otheraddress bits may be set to either VILor VIH. The Manufacturer Code for STMicroelectronics is 0020h.

The Device Code can be read using a Bus Read operation with A0 = VIHand A1 = VIL. The other address bits may be set to either VILor VIH. The Device Code for the M29W200BT is0051h and for the M29W200BB is 0057h.

The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A16 specifying the address of the block. The other address bits may be set toeither VILor VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations,the final write operation latches theaddress and data inthe internal state machine and starts the Program/Erase Controller.

If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register isnever read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to issue any command to abortor pause the operation. Typical program timesare givenin Table 9. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

Note thatthe Program command cannotchange a bit set at ’0’ back to ’1’. One of the Erase Commands mustbe used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

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M29W200BT, M29W200BB

Table 7. Commands, 16-bit mode, BYTE = V

Table 8. Commands, 8-bit mode, BYTE = V

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A16, DQ8-DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is V

or DQ15when BYTE is VIH.

Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Auto Select. After an Auto Select command, readManufacturer ID, Device ID or Block Protection Status. Program, Unlock Bypass Program, Chip Erase, BlockErase. After these commands read the Status Register until the Program/Erase

Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write Operations until Timeout Bit isset.

Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory asnormal until another command is issued. Erase Suspend. After the EraseSuspend command readnon-erasing memory blocks as normal, issue AutoSelect and Program commands

on non-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/

Erase Controller completes and the memory returns to Read Mode.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset

1X F0

3 555 AA 2AA 55 X F0 Auto Select 3 555 AA 2AA 55 555 90 Program 4 555 AA 2AA 55 555 A0 PA PD Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass

Program

2X A0PAPD Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset

1X F0

3 AAA AA 555 55 X F0 Auto Select 3 AAA AA 555 55 AAA 90 Program 4 AAA AA 555 55 AAA A0 PA PD Unlock Bypass 3 AAA AA 555 55 AAA 20 Unlock Bypass

Program

2X A0PAPD Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30

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