SGS Thomson Microelectronics M27W202-100F6, M27W202-100B6, M27W202-150N6TR, M27W202-150K6TR, M27W202-150F6 Datasheet

1/15April 2000

M27W202

2 Mbit (128Kb x16) Low Voltage UV EPROM and OTP EPROM

■ 2.7V to 3.6V SUPPLY VOLTAGE in READ

OPERATION

■ ACCESS TIME:

–80ns at V

CC

= 3.0V to 3.6V

– 100ns at V

CC

= 2.7V to 3.6V

■ LOW POWER CONSUMPTION:

– Active Current 20mA at 5MHz – Standby Current 15µA

■ PIN COMPATIBLE with M27C202

■ PROGRAMMING TIME: 100µs/word

■ HIGH RELIABILITY CMOS TECHNOLOGY

– 2,000V ESD Protection – 200mA Latchup Protection Immunity

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h – Device Code: 001Ch

DESCRIPTION

The M27W202 is a low voltage 2 Mbit EPROM offered in the two range UV (ultra violet erase) and OTP (one time programmab le). It is ideally suited for microprocessor systems requiring large data or program storage and is organised as 13 1,072 by 16 bits.

The M27W202 operates in the read mode with a supply voltage as low as 2.7V at –40 to 85°C temperature range. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges.

The FDIP40W (window ceramic frit-seal package) has a transparent lid which all ows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure.

For application where the content is programmed only one time and erasure is not required, the M27W201 is offered in PDIP40, PLCC44 and TSOP40 (10 x 14 mm) packages.

Figure 1. Logic Diagram

AI02730

17

A0-A16

P

Q0-Q15

V

PP

V

CC

M27W202

G

E

V

SS

16

1

40

1

40

PDIP40 (B)

PLCC44 (K) TSOP40 (N)

10 x 14 mm

FDIP40W (F)

M27W202

2/15

Figure 2B. LCC Connections

AI02732

A14

A11

A7

A3

23

Q6 Q5 Q4

Q3

Q2

NC

A2

Q12

Q8

V

SS

NC

Q11 Q10

12

A15

A9

1

Q15

V

SS

A12

Q13

A5

44

NC

A16

M27W202

Q14

A13

A4

NC

A6

34

Q1

Q9

A10

A8Q7

Q0

G

A0

A1

VPPE

P

V

CC

Figure 2A. DIP Connections

Q6 Q5 Q4

Q11

Q8

V

SS Q7

Q10

Q9

A12

A8

A11 A10

A6

A13

A9 V

SS

A7

A2Q1

Q0

A0G

A1

A5

A16

PE

Q12

V

PP

V

CC

Q15

AI02731

M27W202

8

1 2 3 4 5 6 7

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 2120

19

18

17

Q3 Q2

Q14 Q13

A4 A3

40 39 38 37 36 35 34 33

A14

A15

Figure 2C. TSOP Connections

DQ6

DQ3

DQ2

DQ13

DQ8

DQ7

DQ10

DQ9

A14

A8

A11

A10

A4

A15

A9

G

A7

A2

DQ1

DQ0

A0

A1

A3

A16

P

E

DQ14

V

PP

V

CC

DQ15

AI02733

M27W202

(Normal)

10

1

11

20 21

30

31

40

V

SS

A12 A6 A13 A5

DQ12 DQ4 DQ11 DQ5

V

SS

Table 1. Signal Names

A0-A16 Address Inputs Q0-Q15 Data Outputs E

Chip Enable

G

Output Enable

P

Program

V

PP

Program Supply

V

CC

Supply Voltage

V

SS

Ground

NC Not Connected Internally

3/15

M27W202

Table 2. Absolute Maximum Ratings

(1)

Note: 1. Except for the ra ting "Oper at i ng Temperat ure Range", stresse s above th ose listed i n t he Table "Absolute M aximum Rat i ngs" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c onditions for extended per iods may aff ect device reliabilit y. Refer also to the STMicroel ectronics SURE Program an d other relevan t qual ity docum en ts .

2. Minimum D C volta ge on Input or O utpu t is –0. 5V with possibl e under shoot t o –2.0V for a period less than 20n s. Maxim um D C

voltage on Output is V

CC

+0.5V with possible overshoot to VCC +2V for a period l ess than 20ns.

3. Depends on range.

Table 3. Operating Modes

Note: X = VIH or VIL, VID = 12V ± 0.5V.

Table 4. Electronic Signature

Note: Output s Q15-Q8 are s et to '0'.

Symbol Parameter Value Unit

T

A

Ambient Operating Temperature

(3)

–40 to 125 °C

T

BIAS

Temperature Under Bias –50 to 125 °C

T

STG

Storage Temperature –65 to 150 °C

V

IO

(2)

Input or Output Voltage (except A9) –2 to 7 V

V

CC

Supply Voltage –2 to 7 V

V

A9

(2)

A9 Voltage –2 to 13.5 V

V

PP

Program Supply Voltage –2 to 14 V

Mode E

G P A9

V

PP

Q15-Q0

Read

V

IL

V

IL

V

IH

X

V

CC

or V

SS

Data Output

Output Disable

V

IL

V

IH

XX

V

CC

or V

SS

Hi-Z

Program

V

IL

X

V

IL

Pulse

X

V

PP

Data Input

Verify

V

IL

V

IL

V

IH

X

V

PP

Data Output

Program Inhibit

V

IH

XXX

V

PP

Hi-Z

Standby

V

IH

XXX

V

CC

or V

SS

Hi-Z

Electronic Signature

V

IL

V

IL

V

IH

V

ID

V

CC

Codes

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code

V

IL

00100000 20h

Device Code

V

IH

00011100 1Ch

M27W202

4/15

Table 5. AC Measurement Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform

AI01822

3V

High Speed

0V

1.5V

2.4V

Standard

0.4V

2.0V

0.8V

Figure 4. AC Testing Load Circuit

AI01823B

1.3V

OUT

CL

CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance

3.3kΩ

1N914

DEVICE UNDER

TEST

Table 6. Capacitance

(1)

(TA = 25 °C, f = 1 MHz)

Note: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

C

IN

Input Capacitance

V

IN

= 0V

6pF

C

OUT

Output Capacitance

V

OUT

= 0V

12 pF

DEVICE OPERATION

The operating modes of the M27W202 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for V

PP

and 12V on A9 for Electronic

Signature.

Read Mode

The M27W202 has two control functions, both of which must be logically ac tive in order to obtain data at the output s. Chip Enable (E

) is the power control and should be used for device selection. Output Enable (G

) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time

(t

AVQV

) is equal to the delay from E to output

(t

ELQV

). Data is available at the output after a delay

of t

OE

from the fallin g e dge of G, assuming that E has been low and the addresses have been stable for at least t

AVQV-tGLQV

.

Standby Mode

The M27W202 has a standby mode which reduces the supply current from 15mA to 15µA with low voltage operation V

CC

â 3.6V, see Read Mode DC

Characteristics table for details. The M27W202 i s placed in t he standby m ode by

applying a TTL high signal to the E

input. When in the standby mode, the outputs are in a high impedance state, independent of the G

input.

5/15

M27W202

Table 7. Read Mode DC Characteristics

(1)

(TA = –40 to 85 °C; VCC = 2.7V to 3.6V; V

PP

= VCC)

Note: 1. VCC must be ap pl i e d simultaneously with or before VPP and removed simultane ously or aft er VPP.

2. Maximum DC voltage on Ou tput is V

CC

+0.5 V.

Symbol Parameter Test Condition Min Max Unit

I

LI

Input Leakage Current

0V ≤ V

IN

≤ V

CC

±10 µA

I

LO

Output Leakage Curren t

0V ≤ V

OUT

≤ V

CC

±10 µA

I

CC

Supply Current

E

= VIL, G = VIL,

I

OUT

= 0mA, f = 5MHz

V

CC

≤ 3.6V

20 mA

I

CC1

Supply Current (Standby) TTL

E

= V

IH

1mA

I

CC2

Supply Current (Standby) CMOS

E

> VCC – 0.2V

V

CC

≤ 3.6V

15 µA

I

PP

Program Current

V

PP

= V

CC

10 µA

V

IL

Input Low Voltage –0.6

0.2 V

CC

V

IH

(2)

Input High Voltage

0.7 V

CC

VCC + 0.5

V

OL

Output Low Voltage

I

OL

= 2.1mA

0.4 V

V

OH

Output High Voltage TTL

I

OH

= –400µA

2.4 V

Two Line Outp ut C ontrol

Because OTP EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows:

a. the lowest possible memory power dissipation, b. comple te assuranc e that output bus contention

will not occur.

For the most efficient use of these two control lines, E

should be decoded and used as the prima-

ry device selecting function, while G

should be made a common connectio n to all devices in the array and connected to the READ

line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.

System Considerations

The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, I

CC

, has three segments that are of interest to the system designe r: the standby current level, the active current level, and transient current peaks that are p roduced by the falling and rising edges of E

. The magnitude of transient current peaks is dependent on the capacitive and induct ive l oading of t he device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling

capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between V

CC

and VSS. This should be a high frequency capac itor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between V

CC

and VSS for every eight devices. The bulk capacitor sho uld be located near the power supply connection point.The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.