The M27W201 is a low voltage 2 Mbit EPROM offered in the two range UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage and is organised as 262,144 by 8
bits.
The M27W201 operates in the read mode with a
supply voltage as low as 2.7V at –40 to 85°C temperature range. The decrease in operating power
allows either a reduction of the size of the battery
or an increase in the time between battery recharges.
The FDIP32W (window ceramic frit-seal package)
has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bitpattern. A new pattern can then be written to the
device by following the programming procedure.
For application where the content is programmed
only one time and erasure is not required, the
M27W201 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
A0-A17
V
18
P
E
G
V
CC
M27W201
V
SS
PP
8
Q0-Q7
AI01359
1/15April 2000
M27W201
Figure 2A. DIP Connections
V
1
PP
2
A15
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
A2
A1
A0
Q0
Q2
SS
M27W201
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AI02675
V
CC
PA16
A17
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5Q1
Q4
Q3V
Figure 2B. LCC Connections
A16
A7
A6
A5
A4
A3
A2
A1
A0
Q0
A12
9
Q1
VPPV
A15
1
32
M27W201
17
Q2
Q3
SS
V
Q4
CC
P
Q5
A17
25
Q6
A14
A13
A8
A9
A11
G
A10
E
Q7
AI01360
Figure 2C. TSOP Connections
A11G
A9
A8
A13
A14
A17
V
CC
V
PP
A16
A15
A12
A7
A6
A5
A4A3
1
P
M27W201
8
(Normal)
9
1617
32
25
24
AI01361
A10
E
Q7
Q6
Q5
Q4
Q3
V
SS
Q2
Q1
Q0
A0
A1
A2
Table 1. Signal Names
A0-A17Address Inputs
Q0-Q7Data Outputs
EChip Enable
GOutput Enable
PProgram
V
PP
V
CC
V
SS
Program Supply
Supply Voltage
Ground
2/15
M27W201
Table 2. Absolute Maximum Ratings
(1)
SymbolParameterValueUnit
T
A
T
BIAS
T
STG
(2)
V
IO
V
CC
(2)
V
A9
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Referalso to the STMicroelectronics SURE Program andother relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Outputis V
3. Depends on range.
Ambient Operating Temperature
Temperature Under Bias–50 to 125°C
Storage Temperature–65 to 150°C
Input or Output Voltage (except A9)–2 to 7V
Supply Voltage–2 to 7V
A9 Voltage–2 to 13.5V
Program Supply Voltage–2 to 14V
+0.5V with possible overshoot to VCC+2V for a period less than 20ns.
CC
(3)
–40 to 125°C
Table 3. Operating Modes
ModeEGPA9
Read
Output DisableV
Program
VerifyV
Program Inhibit
Standby
Electronic Signature
Note: X = VIHor VIL,VID= 12V ± 0.5V.
V
IL
IL
V
IL
IL
V
IH
V
IH
V
IL
V
IL
V
IH
V
IH
V
IL
XX
XXV
VILPulse
V
IH
X
XVPPData Out
XXX
XXX
V
IL
V
IH
V
ID
V
PP
V
or V
CC
SS
or V
CC
SS
V
PP
V
PP
V
or V
CC
SS
V
CC
Q7-Q0
Data Out
Hi-Z
Data In
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
IdentifierA0Q7Q6Q5Q4Q3Q2Q1Q0Hex Data
Manufacturer’s Code
Device Code
V
IL
V
IH
00100000 20h
01100001 61h
3/15
M27W201
Table 5. AC Measurement Conditions
High SpeedStandard
Input Rise and Fall Times≤ 10ns≤ 20ns
Input Pulse Voltages0 to 3V0.4V to 2.4V
Input and Output Timing Ref. Voltages1.5V0.8V and 2V
Figure 3. AC Testing Input Output Waveform
High Speed
3V
1.5V
0V
Standard
2.4V
0.4V
Table 6. Capacitance
SymbolParameterTest ConditionMinMaxUnit
C
IN
C
OUT
Note: 1. Sampled only, not 100% tested.
(1)
(TA=25°C, f = 1 MHz)
Input Capacitance
Output Capacitance
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
DEVICE
UNDER
TEST
CL= 30pFfor High Speed
CL= 100pF for Standard
CLincludes JIG capacitance
V
=0V
IN
V
=0V
OUT
1N914
3.3kΩ
C
L
6pF
12pF
OUT
AI01823B
DEVICE OPERATION
The operating modes of the M27W201 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for VPPand 12V on A9 for Electronic
Signature.
Read Mode
The M27W201 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable(G) is the output control and should
be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time
4/15
(t
) is equal to the delay from E to output
AVQV
(t
). Data is available attheoutputafteradelay
ELQV
of t
from the falling edge of G, assuming that
GLQV
E has been low and the addresses have been stable for at least t
AVQV-tGLQV
.
Standby Mode
The M27W201 has a standby mode which reduces the supply current from 15mA to 15µA with low
voltage operation VCC≤ 3.6V, see Read ModeDC
Characteristics table for details.The M27W201 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
M27W201
Table 7. Read Mode DC Characteristics
(1)
(TA= –40 to 85 °C; VCC= 2.7V to 3.6V; VPP=VCC)
SymbolParameterTest ConditionMinMaxUnit
I
I
I
CC
I
CC
I
CC
I
V
V
IH
V
V
Note: 1. VCCmust be applied simultaneously with or before VPPand removed simultaneously or after VPP.
Input Leakage Current
LI
Output Leakage Current
LO
Supply Current
1
Supply Current (Standby) TTL
2
Supply Current (Standby) CMOS
Program Current
PP
Input Low Voltage–0.6
IL
(2)
Input High Voltage
Output Low Voltage
OL
Output High VoltageTTL
OH
2. Maximum DC voltage on Output is V
CC
+0.5V.
I
OUT
0V ≤ V
0V ≤ V
E=V
E>V
I
≤ V
IN
CC
≤ V
OUT
IL
= 0mA, f = 5MHz
V
CC
E=V
CC
V
CC
V
PP=VCC
I
= 2.1mA
OL
= –400µA
OH
CC
,G=VIL,
≤ 3.6V
IH
– 0.2V
≤ 3.6V
±10µA
±10µA
15mA
1mA
15µA
10µA
0.2 V
CC
0.7 V
CCVCC
2.4V
+ 0.5
0.4V
V
V
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, Eshould be decoded and used as theprimary device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system controlbus. This ensures that all deselected memory devices are intheir low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three segments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising ed ges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between V
CC
and VSS. This should be a high frequency capacitor of low inherent inductance and should be
placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be
used between VCCand VSSfor every eight devices. The bulk capacitor should be located near the
power supply connection point. The purposeofthe
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/15
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