SGS Thomson Microelectronics LNBP21PD-TR, LNBP21PD, LNBP21D2-TR, LNBP21D2 Datasheet

LNBP21
LNBP SUPPLY AND CONTROL IC WITH
STEP-UP CONVERTER AND I
COMPLETE INTERFACE BETWEEN LNB
AND I2CTM BUS
BUILT-IN DC/DC CONTROLLER FOR
SINGLE 12V SUPPLY OPERATION
ACCURATE BUILT-IN 22KHz TONE
OSCILLATOR
SUITS WIDELY ACCEPTED STANDARDS
DiSEqCTM ENCODING
BUILT-IN 22KHz TONE DETECTOR
SUPPORTS BI-DIRECTIONAL DiSEqCTM
LOOP-THROUGH FUNCTION FOR SLAVE
OPERATION
LNB SHORT CIRCUIT PROTECTION AND
DIAGNOSTIC
CABLE LENGTH DIGITAL COMPENSATION
INTERNAL OVER TEMPERATURE
PROTECTION
ESD RATING4KV ON POWER
INPUT-OUTPUT PINS
2
C INTERFACE
SO-20PowerSO-20
DESCRIPTION
Intended for analog and digital satellite STB receivers/SatTV, sets/PC cards, the LNBP21 is a monolithic voltage regulator and interface IC, assembled in SO-20 and PowerSO-20, specifically designed t o provide the power and the 13/18V, 22KHz tone signalling to the LNB
SCHEMATIC DIAGRAM
Gate
Sense
Vup
Vcc
Byp
SDA SCL
ADDR
DSQIN
Preregul.+
U.V.lockout
+P.ON res.
I²C interf.
Step-up
Controller
LNBP21
Feedback
Enable I Select V Select
Linear Post-reg
+Modulator
+Protections
22KHz Oscill.
Diagnostics
Tone
Detector
LT1
LT2
OUT
EXTM
DETIN
DSQOUT
1/20October 2002
LNBP21
downconverter i n the antenna or to the multiswitch box. In this application field, it offers a complete solution with extremely low component count, low power dissipation together with simple design and
2
I
CTM standard interfac-ing. This IC has a built in DC/DC step-up controller that, from a s ingle supply source ranging from 8 to 15V, generates the voltages that let the linear post-regulator to work at a minimum dis sipat ed power. An UnderVoltage Lockout circuit will disable the whole circuit when the supplied V
CC
drops below a fixedthreshold(6.7V typically).The internal 22KHz tone generator is factory t rim med in accordance to the standards, and can be controlled either by the I dedicated pin (DSQIN) that allows immediate DiSEqC
TM
data encoding (*). All t he functions of
this IC are controlled via I
2CTM
2CTM
interface or by a
bus by writing 6 bits on the System Register (SR, 8 bits) . The same register can be read back, and two bits will report the diagnostic status. When the IC is put in Stand-by (EN bit LOW), the power blocks are disabled and the loop-through switch between LT1 and LT2 pins is clos ed, thus leaving all LNB powering and control functions to the Master Receiver (**). When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be 13 or 18 V (typ.) by mean of t he VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC LNBs. Additionally, it is possible to increment by 1V (typ.) the selected voltage value to compen sate for the excess voltage drop along the coaxial cable ( LLC bit HIGH). In order to minimise the power dissipation, the out put voltage of the internal step-up converter is adjusted to allow the linear regulator to work at m inimum dropout. Another bit of the SR is addressed to the remote control of non-DiSEqC LNBs: the TEN (Tone ENable) bit. When it is set to HIGH, a continuous 22K Hz to ne is gene rated regardless of the DSQIN pin logic status. The TEN bit must besetLOWwhentheDSQINpinisusedfor DiSEqC DiSEqC 22KHz tone detector. Its input pin (DETIN) must be AC coupled to the DiSEqC
TM
encoding. The f ully bi-directional
TM
interfacing is c ompleted by the built -in
TM
bus, and the extractedPWKdataareavailableonthe DSQOUT pin (*). In order to improve design flexibility and to allow implementation of newcoming LNB remote control standards, an analogic modulation input pin is available (EXTM). An appropria te DC blocking
(*): External components are needed to comply to bi-directional DiSEqCTMbus hardware require-ments. Full compliance of the whole appli­cation toDiSEqCTMspecifications is not implied by the use of this IC. (**): The current limitation circuit has no effect on the loop-through switch. When EN bit is LOW, the current flowing from LT1 to LT2 must be externally limited.
capaci-tor must be used to couple the modulating signal sour ce to the EX TM pin. When external modulation is not used, the relevant pin can be left open. The cu rrent limitation block has two thresho lds that can be selected by the I
bitoftheSR;the
SEL
lower threshold is between 400 and 550m A (I
=HIGH), while the higher threshold is
SEL
between 500 and 650mA (I
SEL
=LOW). The current protection block is SOA type. This limits the short circuit current (Isc) typically at 200mA with I I
=LOW when the output port is connected to
SEL
=HIGH and at 300mA with
SEL
ground. It is possible to set the Short Circuit Current protection either statically (simple current clamp) or dy-namically by the PCL bit of the SR; when the PCL (Pulsed Current Limiting) bit is set to LOW, the overcurrent protection c ircuit w ork s dynamically: as soon as an overload is detected, the output is shut-down for a time t
, typically
off
900ms. S imultaneously the OLF bit of the System Register is set to HIGH. After this time has elapsed, the output is resumed for a time t 10t
(typ.). At the end of ton, if the overload is still
off
on
=1/
detected, the protection circuit will cycle again through Toff and T on. At the end of a full Ton in which no overload is detected, norm al operation is resumed and the OLF bit is reset to LOW. Typica l Ton+Toff time is 990ms and it is determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start up in most conditions (**) . However, there c ould be some cases in whi ch an highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. T his can be solved by initiating any power start-up in static mode (PCL=HIGH) and then switching t o the dynam ic mode (PCL=LOW) after a chosen amount of time. When in static mode, the OLF bit goes HIGH when the current clamp limit is reached and returns LOW when the overload condition is cleared. This IC is also protect ed against overheating: when the junction temperature exceeds 150°C (typ.), the step-up converter and the linear regulator are shut off, the loop-trough switch is opened, and the OTF bit of the SR is set to HIGH. Normal operation is resumed and the OTF bit is reset to LOW when the junction is cooled down to 140°C (typ.).
2/20
ORDERING CODES
LNBP21
TYPE
SO-20 (Tube)
SO-20
(Tape & Reel)
PowerSO-20
(Tube)
PowerSO-20
(Tape & Reel)
LNBP21 LNBP21D2 LNBP21D2-TR LNBP21PD LNBP21PD-TR
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V V
V
LT1,VLT2
I
V
V
V
DETIN
V
I
V
I
GATE
V
SENSE
V
ADDRESS
T T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
DC Input Voltage
CC
DC Input Voltage
UP
DC Input Voltage Output Current
O
DC Output Pin Voltage
O
Logic Input Voltage (SDA, SCL, DSQIN)
I
Detector Input Signal Amplitude Logic High Output Voltage (DSQOUT)
OH
Bypass Switch ON Current
LT
Bypass Switch OFF Voltage
LT
Gate Current Current Sense Voltage Address Pin Voltage Storage Temperature Range
stg
Operating Junction Temperature Range
op
16 V 25 V 20 V
Internally Limited mA
-0.3 to 22 V
-0.3 to 7 V 2
V
PP
7V
900 mA ±20 V
±400 mA
-0.3 to 1 V
-0.3 to 7 V
-40 to +150 °C
-40 to +125 °C
THERMAL DATA
Symbol Parameter SO-20 PowerSO-20 Unit
R
thj-case
Thermal Resistance Junction-case
15 2 °C/W
PIN CO NFIGUARATION (top view)
SO-20
PowerSO-20
3/20
LNBP21
TABLE A: PIN CONFIGURATIONS
PIN NUMBER
SYMBOL NAME FUNCTION
V
Supply Input 8V to 15V supply. A 220µF bypass capacitor to
CC
GND with a 470nF (ceramic) in parallel is recommended
GATE Exrernal Switch Gate External MOS switch Gate connection of the
step-up converter
SENSE Current Sense Input Current Sense comparator input. Connected to
current sensing resistor
V
Step-up Voltage Input of the linear post-regulator.Thevoltage on this
up
pin is monitored by internal step-ut controller to keep a minimum dropout across the linear pass transistor
OUT Output Port Output of the linear post regulator modulator to the
LNB. See truth table for voltage selections.
SDA Serial Data
SCL Serial Clock
Bidirectional data from/to I Clock from I
2
Cbus.
2
C bus.
DSQIN DiSEqC Input When the TEN bit of the System Register is LOW,
this pin will accept the DiSEqC code from the main µcontroller. The LNBP21 will use this code to modulate the internally generated 22kHz carrier.Set to GND thi pin if not used.
DETIN Detector In 22kHz Tone Detector Input. Must be AC coupled to
the DiSEcQ bus.
DSQOUT DiSEqC Output Open collector output of the tone Detector to the
main µcontroller for DiSEcQ data decoding. It is LOW when tone is detected.
EXTM Extrernal Modulator External Modulation Input. Need DC decoupling to
the AC source. If not used, can be left open.
GND Ground Circuit Ground. It is internally connected to the die
frame for heat dissipation.
BYP Bypass Capacitor Needed for internal preregulator filtering 8 8
LT1 Loop Through Switch In standby mode the power switch between LT1
and LT2 is closed. Max allowed current is 900mA. this pin can be left open if loopthrough function is not needed.
LT2 Loop Through Switch Same as above 2 3
ADDR Address Setting
2
C bus addresses available by setting the
Four I Address Pin level voltage
vs PACKAGE
SO-20 PowerSO-20
19 18
17 17
14 16
20 19
12
11 12 12 13 13 14
99
10 15
45
5,6,15,16 1,10,11,20
34
77
4/20
TYPICAL AP PLICATION CIRCUIT
C2 220µF
C3 470nF
Ceramic
IC1
Vup
D1 1N4001
LT1
Master ST B
C7 10nF
LNBP21
IC2
(Note 3)
STS4DNFS30L
Gate
LNBP21
L1=22µH
Vin
12V
(*) Set to GND if not used (**) filter to be used according to EUTELSAT reccomendation to implement the DiSEqC not implemented (see DiSEqC implementation note) (***) IC2 isa ST Fettky, STS4DNFS30L,thatincludes both the schottkydiode andtheN-Channel Mos-Fet, needed fortheDC/DC converter, in a So-8 package. It can be replaced by a schottky diode (STPS2L3A or similar) and a N-Channel Mos-Fet (STN4NF03L or similar)
R
sc
0.1
ΩΩΩΩ
(Note 4)
C1 220µF
C4 470nF
Ceramic
Sense
Vcc
DSQIN(Note 1) SCL SDA
GND
LT2
Vo
DETIN (Note 1)
Byp
EXTM
ADDRESS
DSQOUT
270µH
C6 10nF
C5 470nF
D2 BAT43
see Note 2
0<Vaddr<V
15 ohm
C8 10nF
TM
2.x, not needed if bidirectional DiSEqCTM2.x is
to LNB
Byp
I2C BUS INTERFACE
Data transmission from main µP to the LNBP21 and viceversa takes place through t he 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected).
DATA VALIDITY As shown in fig. 1, the data on the SDA line must
be stable during the high period of the clock. The HIGH and LOW state of the da ta line can only change when the c lock s ignal on the SCL line is LOW.
ACKNOWLEDGE The mas ter (µP) puts a resistive HIGH level on the
SDA l ine during the acknowledge clock pulse (see fig. 3). The peripheral (LNBP21) that acknowledges has to pull-down (LOW) the SDA line during the acknowled ge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which has been addressed has to generate an ac k nowledge after the reception of each byte, other-wise the SDA line remains at the HIGH l ev el during the ninth clock pulse time. In this case the master transm it ter can generate t he STOP information in order to abort the transfer.
START A ND S TOP CONDITIONS As shown in fig.2 a start condition is a H IG H to
LOW transition of the SDA line while SCL is HIGH.
The LNBP21 won't gen-erate the acknowledge if the Vcc s upply is below the Undervoltage Lockout threshold (6.7V typ.).
The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condi-tions must be sent before each START condition.
TRANSMISSION WITHOUT ACKNOWLEDGE Avoiding to detect the acknowledge of the
LNBP21, th e µP can use a simpler transmission:
BYTE FORMAT Every byte transferred to the SDA line must
contain 8 bits. Each byte must be followed by an ac-knowledge bit. The MSB is transferred first.
simply it waits one clock without checking the slave acknowledging, and sends the new data.
This approach of cou rse is less protected from misworking and decreases the noise immuni ty.
5/20
LNBP21
Figure1 : DATA V ALIDITY ON THE I2CBUS
2
Figure2 : TIMING DIAGRAM ON I
CBUS
Figure3 : ACKNOWLEDGE ON I
6/20
2
CBUS
Loading...
+ 14 hidden pages