SANYO VPC-AZ3EX, VPC-AZ3 CIRCUIT DESCRIPTION
1. OUTLINE OF CIRCUIT DESCRIPTION
1-1. CA1 and A PART OF CA2 CIRCUIT
DESCRIPTIONS
Around CCD block
1. IC Configuration
CA1 board
IC901 (ICX411AQ) CCD imager
CA2 board
IC931 H driver, CDS, AGC and A/D converter
IC934 (CXD3400N) V driver
2. IC901 (CCD imager)
[Structure]
Interline type CCD image sensor
Image size Diagonal 8.293 mm (1/1.8 type)
Pixels in total 2384 (H) x 1734 (V)
Recording pixels 2288 (H) x 1712 (V)
10
11
1B
OUT
V
DD
V
9
12
GND
RG
Ø
TEST
8
13
2
Ø
H
Ø
V
TEST
7
6
Ye
G
Ye
G
Ye
Vertical register
G
Horizontal register
15
14
1
Ø
GND
H
Fig. 1-2. CCD Block Diagram
1A
Ø
Ø
V
V
4
5
Cy
Ye
Mg
G
Cy
Ye
Mg
G
Cy
Ye
Mg
G
17
16
SUB
SUB
C
Ø
(Note) : Photo sensor
3
18
Ø
V
L
V
Cy
Mg
Cy
Mg
Cy
Mg
19
2
3A
Ø
V
1
Ø
H
3B
2
1
(Note)
20
4
Ø
V
2
Ø
H
Pin No.
1
2, 3
4
5, 6
9, 15
10
11
12
13, 20
14, 19
16
17
18
Symbol
4
Vø
Vø
3A, Vø3B
Vø2
Vø1A, Vø1B
GND
OUT
V
VDD
øRG
Hø2
Hø
1
øSUB
CSUB
VL
Pin Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Signal output
Circuit power
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
Substrate clock
Substrate bias
Protection transistor bias
Table 1-1. CCD Pin Description
Waveform
GND
DC
DC
DC
DC
Voltage
-7.5 V, 0 V
-7.5 V, 0 V, 15 V
-7.5 V, 0 V
-7.5 V, 0 V, 15 V
0 V
Aprox. 10 V
15 V
12.5 V, 16 V
0 V, 5 V
0 V, 5 V
Approx. 8 V
Approx. 8 V
(Different from every CCD)
When sensor read-out
– 2 –
3. IC934 (V Driver) and IC931 (H Driver)
An H driver and V driver are necessary in order to generate
the clocks (vertical transfer clock, horizontal transfer clock
and electronic shutter clock) which driver the CCD. IC934 is
V driver. In addition the XV1-XV4 signals which are output
from IC102 are the vertical transfer clocks, and the XSG signal which is output from IC102 is superimposed onto XV1
and XV3 at IC934 in order to generate a ternary pulse. In
addition, the XSUB signal which is output from IC102 is used
as the sweep pulse for the electronic shutter. A H driver is
inside IC931, and H1, H2 and RG clock are generated at
IC931.
4. IC931 (CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to Pin
(29) of IC931. There are inside the sampling hold block, AGC
block and A/D converter block.
The setting of sampling phase and AGC amplifier is carried
out by serial data at Pin (37) of IC911. The video signal is
carried out A/D converter, and is output by 12-bit.
VRB
VRT
VREF
CCDIN
CDS
PxGA
2~36 dB
VGA
ADC
12
DOUT
RG
H1-H4
HORIZONTAL
4
DRIVERS
CLAMP
INTERNAL
CLOCKS
PRECISION
TIMING
CORE
SYNC
GENERATOR
VD
HD
Fig. 1-2. IC931 Block Diagram
CLAMP
INTERNAL
REGISTERS
SL
SCK
CLPOB
CLPDM
PBLK
CLI
SDATA
– 3 –
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