SANYO LC78625E Datasheet

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

Overview

The LC78625E is a CMOS LSI that implements the signal processing and servo control required by compact disc players, laser discs, CD-V, CD-I and related products. The LC78625E provides several types of signal processing, including demodulation of the optical pickup EFM signal, de-interleaving, error detection and correction, and digital filters that can help reduce the cost of CD player units. It also processes a rich set of servo system commands sent from the control microprocessor. It also incorporates an EFM-PLL circuit and a one-bit D/A converter.

This LSI is an improved version of the LC78620E. In addition to supporting low-voltage operation, on/off control of the de-emphasis function and use of the bilingual function have been enabled in certain additional modes.

Functions

• The LC78625E takes an HF signal as input, digitizes (slices) that signal at a precise level, converts that signal to an EFM signal, and generates a PLL clock with an average frequency of 4.3218 MHz by comparing the phases of that signal and an internal VCO.

• A precise reference clock and the necessary internal timings are generated using an external 16.9344 MHz crystal oscillator.

• Disc motor speed control using a frame phase difference signal generated from the playback clock and the reference clock

• Frame synchronization signal detection, protection, and interpolation to assure stable data readout

• EFM signal demodulation and conversion to 8-bit symbol data

• Subcode data separation from the EFM demodulated signal and output of that data to an external microprocessor

• Subcode Q signal output (LSB first) to a microprocessor over the serial interface after performing a CRC error check

• Demodulated EFM signal buffering in internal RAM to handle up to ±4 frames of disc rotational jitter

• Demodulated EFM signal reordering in the prescribed order for data unscrambling and de-interleaving

• Error detection, correction, and flag processing (error correction scheme: dual C1 plus dual C2 correction)

• The LC78625E sets the C2 flags based on the C1 flags and a C2 check, and then performs signal interpolation or muting depending on the C2 flags. The interpolation circuit uses a quadruple interpolation scheme. The output value converges to the muting level when four or more consecutive C2 flags occur.

Package Dimensions

unit: mm

3174-QFP80E

SANYO: QFP80E

[LC78625E]

CMOS LSI

Ordering number : EN5502

22897HA (OT) No. 5502-1/35

LC78625E

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

Compact Disc Player DSP

• Support for command input from a control microprocessor: commands include track jump, focus start, disk motor start/stop, muting on/off and track count (8-bit serial input)

• Built-in digital output circuits.

• Arbitrary track counting to support high-speed data access

• D/A converter outputs with data continuity improved by 8× oversampling digital filters. (These filters function as 4×

oversampling filters during double-speed playback.)

• Built-in ∑∆ D/A converter implemented by a third-order noise shaper circuit (for PWM output)

• Built-in digital attenuator (8 bits - alpha, 239 steps)

• Built-in digital de-emphasis circuit that can be controlled externally in some modes

• Zero-cross muting

• Support for 2×-speed dubbing

• Support for bilingual applications

• General-purpose I/O ports: 4 pins (when the antishock mode is turned off)

Features

• 5 V single-voltage power supply

• Low-voltage operation: Can be operated at 3.3 V ±10% (at normal playback speed)

• 80-pin QFP package

Equivalent Circuit Block Diagram

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Pin Assignment

No. 5502-3/35

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Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

max VSS– 0.3 to +7.0 V

Maximum input voltage V

VSS– 0.3 to VDD+ 0.3 V

Maximum output voltage V

OUT

VSS– 0.3 to VDD+ 0.3 V Allowable power dissipation Pd max 300 mW Operating temperature Topr –20 to +75 °C Storage temperature Tstg –40 to +125 °C

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions

Ratings

Unit

min typ max

(1)

, XVDD, LVDD, RVDD, VVDD:

3.0 5.5 V

Supply voltage

At normal playback speed

(2)

, XVDD, LVDD, RVDD, VVDD:

4.5 5.5 V

At 2× playback speed DEFI, FZD, ASDACK/P0, ASFIN/P1,

(1)

ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL,

0.7 V

Input high-level voltage

TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST5, DEMO, CS

VIH(2) EFMIN 0.6 V

DEFI, FZD, ASDACK/P0, ASFIN/P1,

(1)

ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL,

0 0.3 V

Input low-level voltage

TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST5, DEMO, CS

(2) EFMIN 0 0.4 V

Data setup time t

COIN, RWC : Figure 1 400 ns

Data hold time t

COIN, RWC : Figure 1 400 ns

High-level clock pulse width t

SBCK, CQCK : Figuires 1, 2 and 3 400 ns

Low-level clock pulse width t

SBCK, CQCK : Figuires 1, 2 and 3 400 ns

Data read access time t

RAC

SQOUT, PW : Figuires 2 and 3 0 400 ns

Allowable Operating Ranges at Ta = 25°C, VSS= 0 V

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Continued from preceding page.

Note: For guaranteed operation, the VCO oscillator frequency range adjustment resistor FR must be a 1.20 kΩ ±5.0% tolerance resistor.

Parameter Symbol Conditions

Ratings

Unit

min typ max

Command transfer time t

RWC

RWC : Figure 1 1000 ns

Subcode Q read enable time t

SQE

WRQ: Figure 2, with no RWC signal 11.2 ms

Subcode read cycle t

SFSY : Figure 3 136 µs

Subcode read enable time t

SFSY : Figure 3 400 ns

Port input data setup time t

PSU

ASDACK/P0, ASFIN/P1, ASDEPC/P2,

400 ns

ASLRCK/P3, RWC : Figure 4

Port input data hold time t

PHD

ASDACK/P0, ASFIN/P1, ASDEPC/P2,

400 ns

ASLRCK/P3, RWC : Figure 4

Port input clock setup time t

RCQ

CQCK, RWC : Figure 4 100 ns

Port output data delay time t

PDD

ASDACK/P0, ASFIN/P1, ASDEPC/P2,

1200 ns

ASLRCK/P3, RWC : Figure 5

Input level

(1) EFMIN 1.0 Vp-p

(2) XIN : Capacitor coupled input 1.0 Vp-p

Operating frequency range f

(1) EFMIN 10 MHz

Crystal oscillator frequency f

XIN, XOUT : In 16M mode 16.9344 MHz

Parameter Symbol Conditions

Ratings

Unit

min typ max

Current drain I

30 45 mA

DEFI, EFMIN, FZD, ASDACK/P0, ASFIN/P1,

IIH(1) ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL, 5 µA

Input high-level current

TES, SBCK, RWC, CQCK : V

= 5 V

(2)

TAI, TEST1 to TEST5, DEMO, CS :

25 75 µA

= VDD= 5.5 V

DEFI, EFMIN, FZD, ASDACK/P0, ASFIN/P1,

Input low-level current I

ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL,

–5 µA

TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST5, DEMO, CS : V

= 0 V

EFMO, EFMO, CLV+, CLV–, V/P, FOCS,

VOH(1) PCK, FSEQ, TOFF, TGL, THLD, JP+, JP–, 4 V

EMPH, EFLG, FSX : I

= –1 mA

MUTEL, MUTER, LRCKO, DFORO, DFOLO, DACKO, TST10, ASDACK/P0, ASFIN/P1,

VOH(2)

ASDEPC/P2, ASLRCK/P3, LRSY, CK2,

4 V

Output high-level voltage ROMXA, C2F, SBSY, PW, SFSY, WRQ,

SQOUT, TST11, 16M, 4.2M, CONT : I

= –0.5 mA

(3) LASER : IOH= –1 mA 4.6 V

(4) DOUT : IOH= –12 mA 4.5 V

(5) LCHP, RCHP, LCHN, RCHN : IOH= –1 mA 3.0 4.5 V

EFMO, EFMO, CLV+, CLV–, V/P, FOCS,

VOL(1) PCK, FSEQ, TOFF, TGL, THLD, JP+, JP–, 1 V

EMPH, EFLG, FSX : I

= 1 mA

MUTEL, MUTER, LRCKO, DFORO, DFOLO, DACKO, TST10, ASDACK/P0, ASFIN/P1,

VOL(2)

ASDEPC/P2, ASLRCK/P3, LRSY, CK2,

0.4 V

Output low-level voltage ROMXA, C2F, SBSY, PW, SFSY, WRQ,

SQOUT, TST11, 16M, 4.2M, CONT, LASER : I

= 2 mA

(3) DOUT : IOL= 12 mA 0.5 V

(4) FST : IOL= 5 mA 0.75 V

(5) LCHP, RCHP, LCHN, RCHN : IOL= 1 mA 0.5 2.0 V

OFF

(1)

PDO, CLV+, CLV–, JP+, JP–, FST :

5 µA

Output off leakage current

OUT

= 5 V

OFF

(2) PDO, CLV+, CLV–, JP+, JP–: V

OUT

= 0 V –5 µA

Charge pump output current

PDOH

PDO : RISET = 68 kΩ 100 125 150 µA

PDOL

PDO : RISET = 68 kΩ –150 –125 –100 µA

Electrical Characteristics at Ta = 25°C, VDD= 5 V, VSS= 0 V

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Parameter Symbol Conditions

Ratings

Unit

min typ max

LCHP, RCHP, LCHN, RCHN;

Total harmonic distortion THD + N 1 kHz: 0 dB data input, using the 20 kHz 0.008 0.0010 %

low-pass filter (AD725D built in) LCHP, RCHP, LCHN, RCHN;

Dynamic range DR 1 kHz: –60 dB data input, using the 20 kHz 84 88 dB

low-pass filter and the A filter (AD725D built in) LCHP, RCHP, LCHN, RCHN;

Signal-to-noise ratio S/N 1 kHz: 0 dB data input, using the 20 kHz 98 100 dB

low-pass filter and the A filter (AD725D built in) LCHP, RCHP, LCHN, RCHN;

Crosstalk CT 1 kHz: 0 dB data input, using the 20 kHz 96 98 dB

low-pass filter (AD725D built in)

One-Bit D/A Converter Analog Characteristics at Ta = 25°C, VDD= LVDD= RVDD= 5 V, VSS= LVSS= RVSS= 0 V

Figure 1 Command Input

Figure 2 Subcode Q Output

Figure 3 Subcode Output

Note: Measured with the normal-speed playback mode digital attenuator in the Sanyo one-bit D/A converter block reference circuit.

Figure 4 General-Purpose Port Input Timing

Figure 5 General-Purpose Port Output Timing

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One-Bit D/A Converter Output Block Reference Circuit

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Pin Functions

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Pin No. Symbol I/O Function

1 DEFI I Defect detection signal (DEF) input (This pin must be connected to 0 V if unused.) 2 TAI I Test input. A pull-down resistor is built in. (This pin must be connected to 0 V in normal operation.) 3 PDO O External VCO control phase comparator output 4 VV

PLL pins

Internal VCO ground. (This pin must be connected to 0 V.) 5 ISET AI PDO output current adjustment resistor connection 6 VV

Internal VCO power supply. 7 FR AI VCO frequency range adjustment 8 V

Digital system ground. (This pin must be connected to 0 V.)

9 EFMO O EFM signal inverted output

10 EFMO O Slice level control EFM signal output 11 EFMIN I EFM signal input 12 TEST2 I Test input. A pull-down resistor is built in. This pin must be connected to 0 V in normal operation. 13 CLV

O Spindle servo control output. Acceleration when CLV+ is high, deceleration when CLV- is high.

14 CLV

–

O Three-value output is also possible when specified by microprocessor command.

15 V/P O

Rough servo/phase control automatic switching monitor output. Outputs a high level during rough servo and a low level during

phase control. 16 FOCS O Focus servo on/off output. Focus servo is on when the output is low. 17 FST O Focus start pulse output. This is an open-drain output. 18 FZD I Focus error zero cross signal input. (This pin must be connected to 0 V if unused.) 19 HFL I Track detection signal input. This is a Schmitt input. 20 TES I Tracking error signal input. This is a Schmitt input. 21 PCK O EFM data playback clock monitor. Outputs 4.3218 MHz when the phase is locked.

22 FSEQ O

Synchronization signal detection output. Outputs a high level when the synchronization signal detected from the EFM signal and

the internally generated synchronization signal agree. 23 TOFF O Tracking off output 24 TGL O Tracking gain switching output. Increase the gain when low. 25 THLD O Tracking hold output 26 TEST3 I Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.) 27 V

Digital system power supply. 28 JP

Track jump output. A high level output from JP+ indicates acceleration during an outward jump or deceleration during an inward

jump. 29 JP

–

A high level output from JP- indicates acceleration during an inward jump or deceleration during an outward jump.

Three-value output is also possible when specified by microprocessor command. 30 DEMO I Sound output function input used for end product adjustment manufacturing steps. A pull-down resistor is built in. (This pin must

be connected to 0 V.) 31 TEST4 I Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.) 32 EMPH O De-emphasis monitor pin. A high level indicates playback of a de-emphasis disk. 33 LRCKO O Word clock output 34 DFORO O

Digital filter outputs

Right channel data output 35 DFOLO O Left channel data output 36 DACKO O Bit clock output 37 TST10 O Test output. Leave open. (Normally outputs a low level.)

Continued on next page.

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Continued from preceding page.

Pin No. Symbol I/O Function

38 ASDACK/P0 I/O Bit clock input 39 ASDFIN/P1 I/O Left and right channel data input

40 ASDEPC/P2 I/O

Sets the built-in de-emphasis filter on or off.

(High: on, low: off) 41 ASLRCK/P3 I/O L/R clock input 42 LRSY O L/R clock output

43 CK2 O

Bit clock output Inverted polarity clock output

ROMXA application output signals

(after reset) (during CK2CON mode)

44 ROMXA O

Interpolation data output

ROM data output (during ROMXA mode)

(after reset) 45 C2F O C2 flag output 46 MUTEL O Left channel mute output 47 LV

Left channel power supply 48 LCHP O Left channel P output 49 LCHN O Left channel N output 50 LV

One-bit D/A converter signals

Left channel ground. Must be connected to 0 V. 51 RV

Right channel ground. Must be connected to 0 V. 52 RCHN O Right channel N output 53 RCHP O Right channel P output 54 RV

Right channel power supply 55 MUTER O Right channel mute output 56 DOUT O Digital output 57 SBSY O Subcode block synchronization signal output 58 EFLG O C1, C2, single and double error correction monitor pin 59 PW O Subcode P, Q, R, S, T, U and W output 60 SFSY O Subcode frame synchronization signal output. This signal falls when the subcodes are in the standby state. 61 SBCK I Subcode readout clock input. This is a Schmitt input. (This pin must be connected to 0 V if unused.) 62 FSX O Output for the 7.35 kHz synchronization signal divided from the crystal oscillator 63 WRQ O Subcode Q output standby output 64 RWC I Read/write control input. This is a Schmitt input. 65 SQOUT O Subcode Q output 66 COIN I Command input from the control microprocessor 67 CQCK I Input for the command input acquisition clock or the SQOUT pin subcode readout clock input. This is a Schmitt input. 68 RES I Reset input. This pin must be set low briefly after power is first applied. 69 TST11 O Test output. Leave open. (Normally outputs a low level.) 70 LASER O Laser on/off output. Controlled by serial data commands from the control microprocessor. 71 16M O 16.9344 MHz output 72 4.2M O 4.2336 MHz output 73 CONT O Supplementary control output. Controlled by serial data commands from the control microprocessor. 74 TEST5 I Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.) 75 CS I Chip select input. A pull-down resistor is built in. This pin must be connected to 0 V if unused. 76 XV

Crystal oscillator ground. Must be connected to 0 V.

77 XIN I

Connections for a 16.9344 MHz crystal oscillator

78 XOUT O 79 XV

Crystal oscillator power supply

80 TEST1 I Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.)

• When antishock mode is not used, these pins are used as generalpurpose I/O ports (P0 to P3). They must either be set to input mode and connected to 0 V, or set to output mode and left open, if unused.

The antishock inputs in antishock mode.

Note: All power-supply pins (VDD, VVDD, LVDD, RVDD, and XVDD) must be connected to the same potential.

CD System Block Diagrams

Pin Applications

1. HF signal input circuit; Pin 11: EFMIN, pin 10: EFMO, pin 9: EFMO, pin 1: DEFI, pin 13: CLV

An EFM signal (NRZ) sliced at an optimal level can be acquired by inputting the HF signal to EFMIN.

The LC78625E handles defects as follows. When a high level is input to the DEFI pin (pin 1), the EFMO (pin 9) and EFMO (pin 10) pins (the slice level control outputs) go to the high-impedance state, and the slice level is held. However, note that this function is only valid in CLV phase control mode, that is, when the V/P pin (pin 15) is low. This function can be used in combination with the LA9230/40 series DEF pin.

Note: If the EFMIN and CLV+ signal lines are too close to

each other, unwanted adiation can result in error rate degradation. We recommend laying a ground or V

shield line between these two lines.

2. PLL clock generation circuit; Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK

Since the LC78625E includes a VCO circuit, a PLL circuit can be formed by connecting an external RC circuit. ISET is the charge pump reference current, PDO is the VCO circuit loop filter, and FR is a resistor that determines the VCO frequency range.

(Reference values) R1 = 68 kΩ, C1 = 0.1 µF R2 = 680 kΩ, C2 = 0.1 µF R3 = 1.2 kΩ

Note: We recommend using a ±5.0% tolerance carbon film

resistor for R3.

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No. 5502-11/35

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3. VCO monitor; Pin 21: PCK PCK is a monitor pin that outputs an average frequency of 4.3218 MHz, which is the VCO frequency divided by two.

4. Synchronization detection monitor; Pin 22: FSEQ Pin 22 goes high when the frame synchronization (a positive polarity synchronization signal) from the EFM signal read in by PCK and the timing generated by the counter (the interpolation synchronization signal) agree. This pin is thus a synchronization detection monitor. (It is held high for a single frame.)

5. Servo command function; Pin 64: RWC, pin 66: COIN, pin 67: CQCK Commands can be executed by setting RWC high and inputting commands to the COIN pin in synchronization with the CQCK clock. Note that commands are executed on the falling edge of RWC.

Focus start Track jump Muting control One byte commands Disc motor control Miscellaneous control

Track check Two-byte command (RWC set twice)

Digital attenuator

Two-byte commands (RWC set once)

General-purpose port I/O data setup

• One-byte commands

• Two-byte commands (RWC set twice)

• Two-byte commands (RWC set once)

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