SANYO LC78624E Datasheet

Overview

The LC78624E is a CMOS LSI that implements the signal processing and servo control required by compact disc players. Including an EFM-PLL and text decoder, the LC78624E strictly limits functionality to basic signal processing and servo system operation to achieve the best cost-performance balance for low-end players. As basic functions, the LC78624E provides demodulation of the EFM signal from the optical pickup, de-interleaving, error detection and correction, and processes servo commands sent from the control microcontroller.

Functions

• Input signal processing: The LC78624E takes an HF signal as input, digitizes (slices) that signal at a precise level, converts that signal to an EFM signal, and generates a PLL clock with an average frequency of

4.3218 MHz by comparing the phases of that signal and an internal VCO.

• Precise reference clock and necessary internal timing generation using an external 16.9344 MHz crystal oscillator

• Disk motor speed control using a frame phase difference signal generated from the playback clock and the reference clock

• Frame synchronization signal detection, protection and interpolation to assure stable data readout

• EFM signal demodulation and conversion to 8-bit symbol data

• Subcode data separation from the EFM demodulated signal and output of that data to an external microcontroller

• Subcode Q signal output to a microcontroller over the serial I/O interface after performing a CRC error check (LSB first)

• Serial output to a microcontroller via the text decoder of the song titles and other text data stored in the Subcode R through W channels of the read-in area

• Demodulated EFM signal buffering in internal RAM to handle up to ±4 frames of disk rotational jitter

• Demodulated EFM signal reordering in the prescribed order for data unscrambling and de-interleaving

• Error detection, correction, and flag processing (error correction scheme: dual C1 plus dual C2 correction)

• The LC78624E sets the C2 flags based on the C1 flags and a C2 check, and then performs signal interpolation or muting depending on the C2 flags. The interpolation circuit uses a dual-interpolation scheme. The previous value is held if the C2 flags indicate errors two or more times consecutively.

• Support for command input from a microcontroller: commands include track jump, focus start, disk motor start/stop, muting on/off and track count (8 bit serial input)

• Built-in digital output circuits.

• Arbitrary track counting to support high-speed data access

• Zero cross muting

• Supports the implementation of a double-speed dubbing function.

• Support for bilingual applications.

• General-purpose I/O ports: 5 pins

Features

• 64 pin QFP

• 5 V single-voltage power supply

Package Dimensions

unit: mm

3159-QFP64E

CMOS LSI

20698RM (OT) No. 5811-1/27

SANYO: QIP64E

[LC78624E]

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN

Compact Disc Player DSP

LC78624E

Ordering number : EN5811

Equivalent Circuit Block Diagram

No. 5811-2/27

LC78624E

Pin Assignment

Slice level

control

VCO clock

oscillator clock

control

× 8-bit

RAM

Synchronization

detection EFM

demodulation

CLV digital

servo

Subcode

separation

and CRC checking

Microcontroller

interface

Servo command

General-

purpose ports

C1 and C2 error

detection and correction

flag processing

RAM address

generator

Interpolation

and muting

Bilingual

Digital output

Subcode text

decoder

microcontroller

interface

Crystal oscillation system

timing generator

No. 5811-3/27

LC78624E

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0 V

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

max VSS– 0.3 to VSS+ 7.0 V

Input voltage V

VSS– 0.3 to VDD+ 0.3 V

Output voltage V

OUT

VSS– 0.3 to VDD+ 0.3 V Allowable power dissipation Pd max 300 mW Operating temperature Topr –20 to +75 °C Storage temperature Tstg –40 to +125 °C

Parameter Symbol Conditions

Ratings

Unit

min typ max

(1)

, XVDD, VVDD:

3.0 5.5 V

During normal-speed playback

Supply voltage

(2)

, XVDD, VVDD:

3.0 5.5 V

During double-speed playback

(1)

DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK,

Input high level voltage

TAI, TEST1 to TEST6, CS, CONT1 to CONT5, SCLK

0.7 V

(2) EFMIN 0.6 V

(1)

DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK,

Input low level voltage

TAI, TEST1 to TEST6, CS, CONT1 to CONT5, SCLK

0 0.3 V

VIL(2) EFMIN 0 0.4 V

Data setup time t

COIN, RWC: Figure 1 400 ns

Data hold time t

COIN, RWC: Figure 1 400 ns

High level clock pulse width t

SBCK, CQCK: Figures 1, 2 and 3 400 ns

Low level clock pulse width t

SBCK, CQCK: Figures 1, 2 and 3 400 ns

Data read access time t

RAC

SQOUT, PW: Figures 2 and 3 0 400 ns

Command transfer time t

RWC

RWC: Figure 1 1000 ns

Subcode Q read enable time t

SQE

WRQ: Figure 2, with no RWC signal 11.2 ms

Subcode read cycle time t

SFSY: Figure 3 136 µs

Subcode read enable time t

SFSY: Figure 3 400 ns

Port input data setup time t

CSU

CONT1 to CONT5, RWC: Figure 4 400 ns

Port input data hold time t

CHD

CONT1 to CONT5, RWC: Figure 4 400 ns

Port input clock setup time t

RCQ

RWC, CQCK: Figure 4 100 ns

Port output data delay time t

CDD

CONT1 to CONT5, RWC: Figure 5 1200 ns

Input level

(1) EFMIN: Slice level control 1.0 Vp-p

(2) XIN: Capacitor-coupled input 1.0 Vp-p Operating frequency range fop EFMIN 10 MHz Crystal oscillator frequency f

XIN, X

OUT

16.9344 MHz

Text readout time t

DQSY : Figure 6. 1.5 3.3 3.7 ms

DQSY pulse width t

DQSY : Figure 6. 60 136 150 µs

SCLK “low” level pulse width t

SCLK : Figure 6. 100 ns

SCLK “high” level pulse width t

SCLK : Figure 6. 100 ns

SCLK delay time t

1 SCLK : Figure 6. 100 ns

Text data delay time

2 SRDT : Figure 6. 50 ns

3 SRDT : Figure 6. 50 ns

Reset time t

RES

RES 400 ns

Allowable Operating Ranges at Ta = 25°C, VSS= 0 V

No. 5811-4/27

LC78624E

Parameter Symbol Conditions

Ratings

Unit

min typ max

Current drain I

VDD, XVDD, VV

25 35 mA

DEFI, EFMIN, COIN, RES, HFL, TES, SBCK,

Input high level current

(1)

RWC, CQCK: TEST1, SCLK: V

= V

5 µA

(2) TAI, TEST2 to TEST6, CS: VIN= VDD= 5.5 V 25 75 µA

DEFI, EFMIN, COIN, RES, HFL, TES, SBCK,

Input low level current I

RWC, CQCK: TAI, TEST1 to TEST6, CS, SCLK: VIN= 0 V

–5 µA

EFMO, CLV

, CLV–, V/P, PCK, FSEQ, TOFF,

(1)

TGL, JP

, JP–, EMPH, EFLG, FSX: IOH= –1 mA

4 V

TEST7 to TEST8, DQSY, SRDT, LRSY, CK2, ROMXA,

Output high level voltage

(2) C2F, SBSY, PW, SFSY, WRQ, SQOUT, TST11, 16M, 4 V

4.2M, CONT1 to CONT5: I

= –0.5 mA

(3) DOUT: IOH= –12 mA 4.5 V

EFMO, CLV

, CLV–, V/P, PCK, FSEQ,

(1) TOFF, TGL, JP+, JP–, EMPH, EFLG, FSX: 1 V

= 1 mA

Output low level voltage

TEST7 to TEST8, DQSY, SRDT, LRSY, CK2, ROMXA,

(2)

C2F, SBSY, PW, SFSY, WRQ, SQOUT,

0.4 V

TST11, 16M, 4.2M, CONT1 to CONT5: I

= 2 mA

(3) DOUT: IOL= 12 mA 0.5 V

OFF

(1)

PDO, CLV

, CLV–, JP+, JP–, CONT1 to CONT5:

5 µA

OUT

= V

Output off leakage current

OFF

(2)

PDO, CLV

, CLV–, JP+, JP–, CONT1 to CONT5:

–5 µA

OUT

= 0 V

Charge pump output current

PDOH

PDO: R

ISET

= 68 kΩ 64 80 96 µA

PDOL

PDO: R

ISET

= 68 kΩ –96 –80 –64 µA

Electrical Characteristics at Ta = 25°C, VDD= 5 V, VSS= 0 V

Figure 1 Command Input

No. 5811-5/27

LC78624E

Figure 2 Subcode Q Output

Figure 3 Subcode Output

A09894

A09895

A09896

Figure 4 General-Purpose Port Input Timing

No. 5811-6/27

LC78624E

Figure 5 General-Purpose Port Output Timing

Figure 6 Text Data Output Timing

A09897

A09898

A09899

Pin Functions

No. 5811-7/27

LC78624E

Pin No. Symbol I/O Function

1 DEFI I Defect detection signal (DEF) input. (Must be connected to 0 V when unused.) 2 TAI I Test input. A pull-down resistor is built in. Must be connected to 0 V. 3 PDO O External VCO control phase comparator output 4 VV

–

PLL pins

Internal VCO ground. Must be connected to 0 V. 5 ISET AI PDO output current adjustment resistor connection 6 VV

– Internal VCO power supply 7 FR AI VCO frequency range adjustment 8 V

– Digital system ground. Must be connected to 0 V. 9 EFMO O

Slice level control

EFM signal output 10 EFMIN I EFM signal input 11 TEST2 I Test input. A pull-down resistor is built in. Must be connected to 0 V. 12 CLV

Disc motor control output.

13 CLV

–

O Three-value output is also possible when specified by microcontroller command.

14 V/P O

Rough servo/phase control automatic switching monitor output. Outputs a high level during rough servo and a low level

during phase control. 15 HFL I Track detection signal input. This is a Schmitt input. 16 TES I Tracking error signal input. This is a Schmitt input. 17 TOFF O Tracking off output 18 TGL O Tracking gain switching output. Increase the gain when low. 19 JP

Track jump control output. 20 JP

–

O Three-value output is also possible when specified by microcontroller command.

21 PCK O EFM data playback clock monitor. Outputs 4.3218 MHz when the phase is locked. 22 FSEQ O

Synchronization signal detection output. Outputs a high level when the synchronization signal detected from the EFM

signal and the internally generated synchronization signal agree. 23 V

– Digital system power supply. 24 CONT1 I/O General-purpose I/O pin 1 25 CONT2 I/O General-purpose I/O pin 2

Controlled by serial data commands from the microcontroller. Any of these that are unused

26 CONT3 I/O General-purpose I/O pin 3 must be either set up as input ports and connected to 0 V, or set up as output ports and 27 CONT4 I/O General-purpose I/O pin 4

left open.

28 CONT5 I/O General-purpose I/O pin 5 29 EMPH O De-emphasis monitor pin. A high level indicates playback of a de-emphasis disk. 30 C2F O C2 flag output 31 DOUT O Digital output. (EIAJ format) 32 TEST3 I Test input. A pull-down resistor is built in. Must be connected to 0 V. 33 TEST4 I Test input. A pull-down resistor is built in. Must be connected to 0 V. 34 TEST6 I Test input. A pull-down resistor is built in. Must be connected to 0 V. 35 TEST7 O Test output 36 LRSY O L/R clock output 37 CK2 O

ROMXA output

Bit clock output 38 ROMXA O Interpolated data output, not ROM output 39 SRDT O Text data output 40 DQSY O Text readout enable output 41 SCLK I Text shift clock input 42 TEST8 O Test output 43 XV

– Crystal oscillator power supply.

44 X

OUT

Connections for a 16.9344 crystal oscillator element

45 X

46 XV

– Crystal oscillator ground. Must be connected to 0 V. 47 SBSY O Subcode block synchronization signal output 48 EFLG O C1, C2, single and double error correction monitor pin 49 PW O Subcode P, Q, R, S, T, U, V and W output 50 SFSY O Subcode frame synchronization signal output. This signal falls when the subcodes are in the standby state.

Continued on next page.

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LC78624E

Continued from preceding page.

Pin No. Symbol I/O Function

51 SBCK I Subcode readout clock input. This is a Schmitt input. (Must be connected to 0 V when unused.) 52 FSX O Output for the 7.35 kHz synchronization signal divided from the crystal oscillator 53 WRQ O Subcode Q output standby output 54 RWC I Read/write control input. This is a Schmitt input. 55 SQOUT O Subcode Q output 56 COIN I Command input from the control microcontroller 57 CQCK I Input for both the command input clock and the subcode readout clock. This is a Schmitt input. 58 RES I Chip reset input. This pin must be set low briefly after power is first applied. 59 TST11 O Test output. Leave open. (Normally outputs a low level.) 60 16M O 16.9344 MHz output. 61 4.2M O 4.2336 MHz output 62 TEST5 I Test input. A pull-down resistor is built in. Must be connected to 0 V. 63 CS I Chip select input. A pull-down resistor is built in. Must be connected to 0 V if not controlled. 64 TEST1 I Test input. No pull-down resistor. Must be connected to 0 V.

Note: The same potential must be supplied to all power supply pins, i.e., VDD, VVDDand XVDD.

Pin Applications

1. HF Signal Input Circuit; Pin 10: EFMIN, pin 9: EFMO, pin 1: DEFI, pin 12: CLV

An EFM signal (NRZ) sliced at an optimal level can be acquired by inputting the HF signal to EFMIN. The LC78624E handles defects as follows. When a high level is input to the DEFI pin (pin 1), EFMO (pin 9) pins (the slice level control outputs) go to the high-impedance state, and the slice level is held. However, note that this function is only valid in CLV phase control mode, that is, when the V/P pin (pin 14) is low. This function can be used in combination with the LA9230M, and LA9240M DEF pins. Note: If the EFMIN and CLV+signal lines are too close to

each other, unwanted radiation can result in error rate degradation. We recommend laying a ground or V

shield line between these two lines.

2. PLL Clock Generation Circuit; Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK Since the LC78624E includes a VCO circuit, a PLL circuit can be formed by connecting external R and C (resistors and capacitors). ISET is the charge pump reference current, PDO is the VCO circuit loop filter, and FR is a resistor that determines the VCO frequency range. (Reference values) R1 = 68 kΩ, C1 = 0.1 µF R2 = 680 Ω, C2 = 0.1 µF R3 = 1.2 kΩ

The VCO× 2 command is an auxiliary command for characteristics guarantee in low-voltage operations. This command supports the low-voltage operations at VDD= 3.0 to 3.6 V.

Code COMMAND RES = low

$AC VCO ×2 SET $AD VCO ×1 SET

●●

A09900

A09901

Frequency

phase

comparator

3. 1/2 VCO Monitor; Pin 21: PCK

PCK is a monitor pin that outputs an average frequency of 4.3218 MHz, which is divided by two from the VCO frequency.

4. Synchronization Detection Monitor; Pin 22: FSEQ

Pin 22 goes high when the frame synchronization (a positive polarity synchronization signal) from the EFM signal read in by PCK and the timing generated by the counter (the interpolation synchronization signal) agree. This pin is thus a synchronization detection monitor. (It is held high for a single frame.)

5. Servo Command Function; Pin 54: RWC, pin 56: COIN, pin 57: CQCK

Commands can be executed by setting RWC high and inputting commands to the COIN pin in synchronization with the CQCK clock. Note that commands are executed on the falling edge of RWC.

Focus start Track jump Muting control One-byte commands Disk motor control Miscellaneous control

Track check Two-byte command (RWC set twice)

General-purpose I/O, E/D Two-byte commands (RWC set once)

• One-byte commands

• Two-byte commands (RWC set twice : For track checking)

No. 5811-9/27

LC78624E

A09902

A09903

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