SANYO LC75884W, LC75884E Datasheet

Ordering number : EN6086

22299RM (OT) No. 6086-1/27

Overview

The LC75884E and LC75884W are 1/4 duty LCD display
drivers that can directly drive up to 220 segments and can
control up to four general-purpose output ports. These
products also incorporate a key scan circuit that accepts
input from up to 30 keys to reduce printed circuit board
wiring.

Features

• Key input function for up to 30 keys (A key scan is

performed only when a key is pressed.)

• 1/4duty - 1/2bias and 1/4duty - 1/3bias drive schemes

can be controlled from serial data (up to 220 segments).

• Sleep mode and all segments off functions that are

controlled from serial data.

• Segment output port/general-purpose output port

function switching that is controlled from serial data.

• Serial data I/O supports CCB format communication

with the system controller.

• Direct display of display data without the use of a

decoder provides high generality.

• Independent V

LCD

for the LCD driver block (V

LCD

can

be set to in the range VDD-0.5 to 6.0 volts.)

• Provision of an on-chip voltage-detection type reset

circuit prevents incorrect displays.

• RES pin provided for forcibly initializing the IC internal

circuits.

• RC oscillator circuit.

Package Dimensions

unit: mm

QFP80E

unit: mm

SQFP80

0.15

1.6

14.0

17.2

0.8

124

25

40

41

64
65

80

21.6

0.8

3.0max

1.0

2.7

15.6

0.8

1.6

0.35

23.2

20.0

0.8 0.8

SANYO: QFP80E(QIP80E)

[LC75884E]

14.0

12.0

1.25 1.25

0.5

14.0

12.0

1.25

1.25

0.5

120

21

40

41

60

61

80

0.1

0.5

1.6max

1.4

0.5

0.2

0.135

SANYO: SQFP80

[LC75884W]

LC75884E, LC75884W

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

1/4 Duty LCD Display Drivers with Key Input Function

CMOS IC

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.

No. 6086-2/27

LC75884E, LC75884W

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage

V

DD

max V

DD

–0.3 to +7.0 V

V

LCD

max V

LCD

–0.3 to +7.0

V

IN

1 CE, CL, DI, RES –0.3 to +7.0

Input voltage V

IN

2 OSC,TEST –0.3 to VDD+0.3 V

V

IN

3 V

LCD

1, V

LCD

2, KI1 to KI5 –0.3 to V

LCD

+0.3

V

OUT

1 DO -0.3 to +7.0

Output voltage V

OUT

2 OSC –0.3 to VDD+0.3 V

V

OUT

3 S1 to S55, COM1 to COM4, KS1 to KS6, P1 to P4 –0.3 to V

LCD

+0.3

I

OUT

1 S1 to S55 300 µA

Output current

I

OUT

2 COM1 to COM4 3

I

OUT

3 KS1 to KS6 1 mA

I

OUT

4 P1 to P4 5
Allowable power dissipation Pd max Ta = 85°C 200 mW
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to +125 °C

Specifications

Absolute Maximum Ratings at Ta=25°C, VSS=0V

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage

V

DDVDD

4.5 6.0
V

V

LCDVLCD

VDD– 0.5 6.0

Input voltage

V

LCD

1 V

LCD

1 2/3 V

LCD

V

LCD

V

V

LCD

2 V

LCD

2 1/3 V

LCD

V

LCD

Input high level voltage

V

IH

1 CE, CL, DI, RES 0.8 V

DD

6.0
V

V

IH

2 KI1 to KI5 0.6 V

DD

V

LCD

Input low level voltage V

IL

CE, CL, DI, RES, KI1 to KI5 0 0.2 V

DD

V

Recommended external resistance R

OSC

OSC 43 kΩ

Recommended external capacitance C

OSC

OSC 680 pF

Guaranteed oscillator range f

OSC

OSC 25 50 100 kHz

Data setup time t

ds

CL, DI :Figure 2 160 ns

Data hold time t

dh

CL, DI :Figure 2 160 ns

CE wait time t

cp

CE, CL :Figure 2 160 ns

CE setup time t

cs

CE, CL :Figure 2 160 ns

CE hold time t

ch

CE, CL :Figure 2 160 ns

High level clock pulse width tø

H

CL :Figure 2 160 ns

Low level clock pulse width tø

L

CL :Figure 2 160 ns

Rise time t

r

CE, CL, DI :Figure 2 160 ns

Fall time t

f

CE, CL, DI :Figure 2 160 ns

DO output delay time t

dc

DO RPU=4.7kΩ, CL=10pF *1 :Figure 2 1.5 µs

DO rise time t

dr

DO RPU=4.7kΩ, CL=10pF *1 :Figure 2 1.5 µs

Allowable Operating Ranges at Ta = –40 to +85°C, VSS=0V

Note: *1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPUand the load capacitance CL.

No. 6086-3/27

LC75884E, LC75884W

Parameter Symbol Conditions

Ratings

Unit

min typ max

Hysteresis V

H

CE, CL, DI, RES, KI1 to KI5 0.1 V

DD

V

Power-down detection voltage V

DET

2.5 3.0 3.5 V

Input high level current I

IH

CE, CL, DI, RES: VI= 6.0V 5.0 µA

Input low level current I

IL

CE, CL, DI, RES: VI= 0V –5.0 µA

Input floating voltage V

IF

KI1 to KI5 0.05 V

DD

V

Pull-down resistance R

PD

KI1 to KI5: VDD= 5.0V 50 100 250 kΩ

Output off leakage current I

OFFH

DO: VO = 6.0V 6.0 µA

V

OH

1 KS1 to KS6: IO= –500µA V

LCD

– 1.0 V

LCD

– 0.5 V

LCD

– 0.2

Output high level voltage

V

OH

2 P1 to P4: IO= –1mA V

LCD

– 1.0

V

V

OH

3 S1 to S55: IO= –20µA V

LCD

– 1.0

V

OH

4 COM1 to COM4: IO= –100µA V

LCD

– 1.0

V

OL

1 KS1 to KS6: IO= 25µA 0.2 0.5 1.5

V

OL

2 P1 to P4: IO= 1mA 1.0

Output low level voltage V

OL

3 S1 to S55: IO= 20µA 1.0 V

V

OL

4 COM1 to COM4: IO= 100µA 1.0

V

OL

5 DO: IO= 1mA 0.1 0.5

V

MID

1 COM1 to COM4: 1/2bias, IO= ±100µA

1/2V

LCD

– 1.0 1/2V

LCD

+ 1.0

V

MID

2 S1 to S55: 1/3bias,IO= ±20µA

2/3V

LCD

– 1.0 2/3V

LCD

+ 1.0

Output middle level voltage *2 V

MID

3 S1 to S55: 1/3bias, IO= ±20µA

1/3V

LCD

– 1.0 1/3V

LCD

+ 1.0

V

V

MID

4 COM1 to COM4: 1/3bias,IO= ±100µA

2/3V

LCD

– 1.0 2/3V

LCD

+ 1.0

V

MID

5 COM1 to COM4: 1/3bias,IO= ±100µA

1/3V

LCD

– 1.0 1/3V

LCD

+ 1.0

Oscillator frequency fosc OSC: R

OSC

= 43kΩ, C

OSC

= 680pF 40 50 60 kHz

I

DD

1 VDD:Sleep mode 100

I

DD

2 VDD: VDD= 6.0V, output open,fosc = 50kHz 270 540

Current drain

I

LCD

1 V

LCD

: Sleep mode 5

µA

I

LCD

2

V

LCD

: V

LCD

= 6.0V, output open, 1/2bias,

200 400

fosc = 50kHz

I

LCD

3

V

LCD

: V

LCD

= 6.0V, output open, 1/3bias,

120 240

fosc = 50kHz

Electrical Characteristics for the Allowable Operating Ranges

Nete: *2. Excluding the bias voltage generation divider resistor built into V

LCD

1 and V

LCD

2. (See Figure 1.)

Figure 1

1. When CL is stopped at the low level

Figure 2

No. 6086-4/27

LC75884E, LC75884W

2. When CL is stopped at the high level

Pin Assignment

No. 6086-5/27

LC75884E, LC75884W

Block Diagram

No. 6086-6/27

LC75884E, LC75884W

No. 6086-7/27

LC75884E, LC75884W

Pin

Pin No.

Function Active I/O

Handling

LC75884E LC75884W

when unused

S1/P1 1 79
S2/P2 2 80
S3/P3 3 1 —

●● OPEN

S4/P4 4 2

S5 to S53 5 to 53 3 to 51

COM1 54 52
COM2 55 53

— ●● OPEN

COM3 56 54
COM4 57 55

KS1/S54 58 56
KS2/S55 59 57 — O OPEN

KS3 to KS6 60 to 63 58 to 61

KI1 to KI5 64 to 68 62 to 66 H I GND

OSC 75 73 — I/O V

DD

CE 78 76 H I
CL 79 77 I GND

DI 80 78 — I

DO 77 75 — O OPEN

RES 76 74 L I V

DD

TEST 74 72 This pin must be connected to ground. — I —

V

LCD

1 71 69 — I OPEN

V

LCD

2 72 70 — I OPEN

V

DD

69 67 — — —

V

LCD

70 68 — — —

V

SS

73 71 Power supply connection. Connect to ground. — — —

Pin Functions

Segment outputs for displaying the display data transferred by serial
data input.
The S1/P1 to S4/P4 pins can be used as general-purpose output ports
under serial data control.

Common driver outputs
The frame frequency fo is given by : fo = (f

OSC

/512)Hz.

Key scan outputs
Although normal key scan timing lines require diodes to be inserted in
the timing lines to prevent shorts, since these outputs are unbalanced
CMOS transistor outputs, these outputs will not be damaged by shorting
when these outputs are used to form a key matrix. The KS1/S54 and
KS2/S55 pins can be used as segment outputs when so specified by
the control data.

Key scan inputs
These pins have built-in pull-down resistors.

Oscillator connection
An oscillator circuit is formed by connecting an external resistor and
capacitor at this pin.

Serial data interface connections to the controller. Note that DO, being
an open-drain output, requires a pull-up resistor.
CE :Chip enable
CL :Synchronization clock
DI :Transfer data
DO :Output data

▲

Reset signal input
RES=low •••• Display off

Key scan disabled
All key data is reset to low

RES=high ••• Display on

Key scan enabled

However, serial data can be transferred when RES is low.

Used for applying the LCD drive 2/3 bias voltage externally. Must be
connected to VLCD2 when a 1/2 bias drive scheme is used.

Used for applying the LCD drive 1/3 bias voltage externally. Must be
connected to VLCD1 when a 1/2 bias drive scheme is used.

Logic block power supply connection. Provide a voltage of between 4.5
and 6.0V.

LCD driver block power supply connection. Provide a voltage of
between VDD–0.5 and 6.0V.

Serial Data Input

1. When CL is stopped at the low level

Note: B0 to B3,A0 to A3

........

CCB address

DD

................................

Direction data

No. 6086-8/27

LC75884E, LC75884W

No. 6086-9/27

LC75884E, LC75884W

2. When CL is stopped at the high level

Note: B0 to B3,A0 to A3

........

CCB address

DD

................................

Direction data

CCB address

........

42H

D1 to D220

............

Display data

S0,S1

....................

Sleep control data

K0,K1

....................

Key scan output/segment output selection data

P0 to P2

................

Segment output port/general-purpose output port selection data

SC

........................

Segment on/off control data

DR

........................

1/2 bias or 1/3 bias drive selection data