SANYO LC75863W, LC75863E Datasheet

Ordering number : ENN7135

D2001TN (OT) No. 7135-1/24

Overview

The LC75863E and LC75863W are 1/3 duty LCD display drivers that can directly drive up to 75 segments and can control up to four general-purpose output ports. These products also incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring.

Features

• Key input function for up to 30 keys (A key scan is

performed only when a key is pressed.)

• 1/3duty - 1/2bias and 1/3duty - 1/3bias drive schemes

can be controlled from serial data (up to 75 segments).

• Sleep mode and all segments off functions that are

controlled from serial data.

• Segment output port/general-purpose output port

function switching that is controlled from serial data.

• Serial data I/O supports CCB format communication

with the system controller.

• Direct display of display data without the use of a

decoder provides high generality.

• Independent V

LCD

for the LCD driver block (V

LCD

can

be set to in the range VDD-0.5 to 6.0 volts.)

• Provision of an on-chip voltage-detection type reset

circuit prevents incorrect displays.

• RC oscillator circuit.

Package Dimensions

unit: mm

3156-QIP48E

unit: mm

3163A-SQFP48

14.0

17.2

1.5

1.6

0.15

0.35

0.1

15.6

0.8

1.0

3.0max

2.7

14.0

17.2

1.5

1.6

1.0

SANYO: QIP48E

[LC75863E]

0.5

7.0

9.0

0.15

0.180.75 0.5

0.75

0.5

0.75

0.5

0.1

112

7.0

9.0

1.7max

SANYO: SQFP48

[LC75863W]

LC75863E, 75863W

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

1/3 Duty LCD Display Drivers with Key Input Function

CMOS IC

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

No. 7135-2/24

LC75863E, 75863W

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage

max V

–0.3 to +7.0

LCD

max V

LCD

–0.3 to +7.0

1 CE, CL, DI –0.3 to +7.0

Input voltage V

2 OSC,TEST –0.3 to VDD+0.3 V

3 V

LCD

1, V

LCD

2, KI1 to KI5 –0.3 to V

LCD

+0.3

OUT

1 DO -0.3 to +7.0

Output voltage V

OUT

2 OSC –0.3 to VDD+0.3 V

OUT

3 S1 to S25, COM1 to COM3, KS1 to KS6, P1 to P4 –0.3 to V

LCD

+0.3

OUT

1 S1 to S25 300 µA

Output current

OUT

2 COM1 to COM3 3

OUT

3 KS1 to KS6 1 mA

OUT

4 P1 to P4 5 Allowable power dissipation Pd max Ta = 85°C 150 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C

Specifications

Absolute Maximum Ratings at Ta=25°C, VSS=0V

Pin Assignment

KI3

KI4

VDD S23

COM1

KI5

S22 S21 S20

VLCD VLCD1 VLCD2

VSS

LC75863E (QIP48E)

LC75863W (SQFP48)

TEST

OSC

CE CL

37 24

121

48 DI

KI1

KI2

KS4

KS5

KS6

COM3

KS1/S24

COM2

S11

S12

KS2/S25

KS3

S19 S18 S17 S16 S15 S14 S13

S7S8S9

S10

P3/S3

P4/S4

P1/S1

P2/S2

Top view

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage

4.5 6.0 V

LCDVLCD

VDD– 0.5 6.0

Input voltage

LCD

1 V

LCD

1 2/3 V

LCD

2 V

LCD

2 1/3 V

LCD

Input high level voltage

1 CE, CL, DI 0.8 V

6.0 V

2 KI1 to KI5 0.6 V

LCD

Input low level voltage V

CE, CL, DI, KI1 to KI5 0 0.2 V

Allowable Operating Ranges at Ta = –40 to +85°C, VSS=0V

Continued on next page.

No. 7135-3/24

LC75863E, 75863W

Parameter Symbol Conditions

Ratings

Unit

min typ max

Hysteresis V

CE, CL, DI, KI1 to KI5 0.1 V

Power-down detection voltage V

DET

2.5 3.0 3.5 V

Input high level current I

CE, CL, DI: VI= 6.0V 5.0 µA

Input low level current I

CE, CL, DI: VI= 0V –5.0 µA

Input floating voltage V

KI1 to KI5 0.05 V

Pull-down resistance R

KI1 to KI5: VDD= 5.0V 50 100 250 kΩ

Output off leakage current I

OFFH

DO: VO = 6.0V 6.0 µA

1 KS1 to KS6: IO= –500µA V

LCD

– 1.0 V

LCD

– 0.5 V

LCD

– 0.2

Output high level voltage

2 P1 to P4: IO= –1mA V

LCD

– 1.0

3 S1 to S25: IO= –20µA V

LCD

– 1.0

4 COM1 to COM3: IO= –100µA V

LCD

– 1.0

1 KS1 to KS6: IO= 25µA 0.2 0.5 1.5

2 P1 to P4: IO= 1mA 1.0

Output low level voltage V

3 S1 to S25: IO= 20µA 1.0 V

4 COM1 to COM3: IO= 100µA 1.0

5 DO: IO= 1mA 0.1 0.5

MID

1 COM1 to COM3: 1/2bias, IO= ±100µA

1/2V

LCD

– 1.0 1/2V

LCD

+ 1.0

MID

2 S1 to S25: 1/3bias,IO= ±20µA

2/3V

LCD

– 1.0 2/3V

LCD

+ 1.0

Output middle level voltage *2 V

MID

3 S1 to S25: 1/3bias, IO= ±20µA

1/3V

LCD

– 1.0 1/3V

LCD

+ 1.0

MID

4 COM1 to COM3: 1/3bias,IO= ±100µA

2/3V

LCD

– 1.0 2/3V

LCD

+ 1.0

MID

5 COM1 to COM3: 1/3bias,IO= ±100µA

1/3V

LCD

– 1.0 1/3V

LCD

+ 1.0

Oscillator frequency fosc OSC: R

OSC

= 39kΩ, C

OSC

= 1000pF 30.4 38 45.6 kHz

1 VDD:Sleep mode 100

2 VDD: VDD= 6.0V, output open,fosc = 38kHz 270 540

Current drain

LCD

1 V

LCD

: Sleep mode 5

µA

LCD

: V

LCD

= 6.0V, output open, 1/2bias,

100 200

fosc = 38kHz

LCD

: V

LCD

= 6.0V, output open, 1/3bias,

60 120

fosc = 38kHz

Electrical Characteristics for the Allowable Operating Ranges

Note: *2. Excluding the bias voltage generation divider resistor built into V

LCD

1 and V

LCD

2. (See Figure 1.)

Parameter Symbol Conditions

Ratings

Unit

min typ max

Recommended external resistance R

OSC

OSC 39 kΩ

Recommended external capacitance C

OSC

OSC 1000 pF

Guaranteed oscillator range f

OSC

OSC 19 38 76 kHz

Data setup time t

CL, DI :Figure 2 160 ns

Data hold time t

CL, DI :Figure 2 160 ns

CE wait time t

CE, CL :Figure 2 160 ns

CE setup time t

CE, CL :Figure 2 160 ns

CE hold time t

CE, CL :Figure 2 160 ns

High level clock pulse width tø

CL :Figure 2 160 ns

Low level clock pulse width tø

CL :Figure 2 160 ns

Rise time t

CE, CL, DI :Figure 2 160 ns

Fall time t

CE, CL, DI :Figure 2 160 ns

DO output delay time t

DO RPU=4.7kΩ, CL=10pF *1 :Figure 2 1.5 µs

DO rise time t

DO RPU=4.7kΩ, CL=10pF *1 :Figure 2 1.5 µs

Note: *1. Since DO is an open-drain output, these times depend on the values of the pull-up resistor RPUand the load capacitance CL.

Continued from preceding page.

1. When CL is stopped at the low level

Figure 2

No. 7135-4/24

LC75863E, 75863W

tdh

50%

VIH1

VIL

VIH1

VIL

tdrtdc

tchtcstcp

tds

tøLtøH

D1D0

2. When CL is stopped at the high level

50%

VIH1 VIL

tdh

VIH1 VIL

VIH1

VIL

tdrtdc

tchtcstcp

tds

tøHtøL

D1D0

Figure 1

VLCD

To the common segment driver

Excluding these resistors.

LCD2

VLCD1

Block Diagram

No. 7135-5/24

LC75863E, 75863W

VDET

CCB

INTERFACE

COM1

COM2

COM3

COMMON

DRIVER

CLOCK

GENERATOR

VSS

VLCD2

VLCD1

VLCD

VDD

TEST

OSC

KI5

KI4

KI3

KI2

KI1

KS6

KS5

KS4

KS3

S25/KS2

S24/KS1

KEY SCAN

KEY BUFFER

CONTROL REGISTER

SHIFT REGISTER

SEGMENT DRIVER & LATCH

S1/P1

S3/P3

S2/P2

S4/P4

S23

No. 7135-6/24

LC75863E, 75863W

Pin Pin No. Function Active I/O

Handling

when unused

S1/P1 1 S2/P2 2 S3/P3 3 —

●● OPEN

S4/P4 4

S5 to S23 5 to 23

COM1 24 COM2 25 — ●● OPEN COM3 26

KS1/S24 27 KS2/S25 28

— O OPEN

KS3 to KS6 29 to 32

KI1 to KI5 33 to 37 H I GND

OSC 44 — I/O V

CE 46 H I CL 47 I GND

DI 48 — I

DO 45 — O OPEN

TEST 43 This pin must be connected to ground. — I —

LCD

1 40 — I OPEN

LCD

2 41 — I OPEN

38 — — —

LCD

39 — — —

42 Power supply connection. Connect to ground. — — —

Pin Functions

Segment outputs for displaying the display data transferred by serial data input. The S1/P1 to S4/P4 pins can be used as general-purpose output ports under serial data control.

Common driver outputs The frame frequency fo is given by : fo = (f

OSC

/384)Hz.

Key scan outputs Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. The KS1/S24 and KS2/S25 pins can be used as segment outputs when so specified by the control data.

Key scan inputs These pins have built-in pull-down resistors.

Oscillator connection An oscillator circuit is formed by connecting an external resistor and capacitor at this pin.

Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor. CE :Chip enable CL :Synchronization clock DI :Transfer data DO :Output data

▲

Used for applying the LCD drive 2/3 bias voltage externally. Must be connected to VLCD2 when a 1/2 bias drive scheme is used.

Used for applying the LCD drive 1/3 bias voltage externally. Must be connected to VLCD1 when a 1/2 bias drive scheme is used.

Logic block power supply connection. Provide a voltage of between 4.5 and 6.0V.

LCD driver block power supply connection. Provide a voltage of between VDD–0.5 and

6.0V.

Serial Data Input

1. When CL is stopped at the low level

No. 7135-7/24

LC75863E, 75863W

B3B2B1B0

0DRSCP2P1P0K1K0S1S0D2D1010

Control Data

Display Data

00000

A3A2A1A0

0 000 1

D39D38D37D36D35D34

0 0

B3B2B1B0

10000000000000000000

D75D74D73D41

D40010

Fixed Data

Display Data

A3A2A1A0

0 000 1

A3B3B2B1B0

0DRSCP2P1P0K1K0S1S0

D2D1

Control Data

Display Data

000000

D39D38D37

A2A1 A0

01010 000

D34 D35 D36

A3B3B2B1B0

D74D73 D75

Fixed Data

Display Data

0 0 0 00000

A2A1A0

D40 D41

000 00 1 01 0 0 0 0 0 0 0 0 0 0 0

2. When CL is stopped at the high level

Note: B0 to B3, A0 to A3

......

CCB address

................................

Direction data

Note: B0 to B3, A0 to A3

......

CCB address

................................

Direction data

CCB address

........

42H

D1 to D75

..............

Display data

S0,S1

....................

Sleep control data

K0,K1

....................

Key scan output/segment output selection data

P0 to P2

................

Segment output port/general-purpose output port selection data

........................

Segment on/off control data

........................

1/2 bias or 1/3 bias drive selection data

Control Data Functions

1. S0, S1 : Sleep control data These control data bits switch between normal mode and sleep mode and set the states of the KS1 to KS6 key scan outputs during key scan standby.

Note: This assumes that the KS1/S24 and KS2/S25 output pins are selected for key scan output.

No. 7135-8/24

LC75863E, 75863W

Control data

Mode OSC oscillator

Segment outputs

Output pin states during key scan standby

S0 S1

Common outputs

KS1 KS2 KS3 KS4 KS5 KS6 0 0 Normal Operating Operating H H H H H H 0 1 Sleep Stopped L L L L L L H 1 0 Sleep Stopped L L L L L H H 1 1 Sleep Stopped L H H H H H H

2. K0, K1 : Key scan output /segment output selection data These control data bits switch the functions of the KS1/S24 and KS2/S25 output pins between key scan output and segment output.

X: don’t care Note: KSn(n=1 or 2) : Key scan output

Sn (n=24 or 25): Segment output

Control data Output pin state

Maximum number of

K0 K1 KS1/S24 KS2/S25

input keys

0 0 KS1 KS2 30 0 1 S24 KS2 25 1 X S24 S25 20

3. P0 to P2 : Segment output port/general-purpose output port selection data These control data bits switch the functions of the S1/P1 to S4/P4 output pins between the segment output port and the general-purpose output port.

Note: Sn(n=1 to 4): Segment output port

Pn(n=1 to 4): General-purpose output port

The table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports.

For example, if the S4/P4 output pin is selected to be a general-purpose output port, the S4/P4 output pin will output a high level (V

LCD

) when the display data

D10 is 1, and will output a low level (Vss) when D10 is 0.

Control data Output pin state

P0 P1 P2 S1/P1 S2/P2 S3/P3 S4/P4

0 0 0 S1 S2 S3 S4 0 0 1 P1 S2 S3 S4 0 1 0 P1 P2 S3 S4 0 1 1 P1 P2 P3 S4 1 0 0 P1 P2 P3 P4

Output pin Corresponding display data

S1/P1 D1 S2/P2 D4 S3/P3 D7 S4/P4 D10

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