Sanyo LC75848T Specifications
Ordering number : ENN7160
CMOS IC
LC75848T
1/8 to 1/10 Duty General-Purpose LCD Display Drivers
Overview |
Package Dimensions |
The LC75848T is 1/8 to 1/10 duty general-purpose LCD display drivers used for character and graphics display. These products operate under the control of a microcontroller and can directly drive an LCD with up to 930 segments. They can also control up to 4 generalpurpose output ports.
Features
•1/8duty–1/4bias, 1/9duty–1/4bias, and 1/10duty–1/4bias drive schemes can be controlled from serial data.
1/8duty–1/4bias: up to 760 segments 1/9duty–1/4bias: up to 846 segments 1/10duty–1/4bias: up to 930 segments
•Serial data input supports CCB format communication with the system controller.
•Serial data control of the power-saving mode based backup function and all the segments forced off function.
•The frame frequency of the common and segment output waveforms can be controlled from the serial data.
•Direct display of display data without the use of a decoder provides high generality.
•Built-in display contrast adjustment circuit.
•Up to 4 general-purpose output ports are included.
•Independent LCD driver block power supply VLCD.
unit: mm
3257-TQFP120
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[LC75848T] |
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16.0 |
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0.125 |
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SANYO: TQFP120 |
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•The INH pin is provided. This pin turns off the display and forces the general-purpose output ports to the low level.
•RC oscillator circuit
•CCB is a trademark of SANYO ELECTRIC CO., LTD.
•CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
42202AS (OT) No. 7160 -1/33
LC75848T
Pin Assignment
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S91 |
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S59 |
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S54 |
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COM6 |
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S53 |
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COM5 |
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S52 |
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COM4 |
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S51 |
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COM3 |
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S50 |
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COM2 |
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S49 |
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COM1 |
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LC75848T |
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S48 |
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P1 |
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S47 |
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P2 |
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(TQFP120) |
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S46 |
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P3 |
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S45 |
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P4 |
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S44 |
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VDD |
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S43 |
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VLCD |
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S42 |
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VLCD0 |
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S41 |
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VLCD1 |
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S40 |
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VLCD2 |
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S39 |
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VLCD3 |
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S38 |
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VLCD4 |
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S37 |
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VSS |
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S36 |
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OSC |
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S35 |
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INH |
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S34 |
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CE |
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S33 |
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CL |
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S32 |
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DI |
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S31 |
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120 |
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31 |
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1 |
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30 |
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S1 S2 S3 S4 S5 S6 S7 S8 |
S9 |
S10 |
S11 |
S12 |
S13 |
S14 |
S15 |
S16 |
S17 |
S18 |
S19 |
S20 |
S21 |
S22 |
S23 |
S24 |
S25 |
S26 |
S27 |
S28 |
S29 |
S30 |
||||||||||||||||||||||||||||||||||||||||||
Top view
No. 7160-2/33
LC75848T
Specifications
Absolute Maximum Ratings at Ta=25°C, VSS=0V
Parameter |
Symbol |
|
|
Conditions |
Ratings |
Unit |
|
|
|
|
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|
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|
|
Maximum supply voltage |
VDD max |
VDD |
–0.3 to +7.0 |
V |
|||
VLCD max |
VLCD |
–0.3 to +12.0 |
|||||
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||||||
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VIN1 |
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|||
|
CE, CL, DI, |
INH |
|
–0.3 to +7.0 |
|
||
Input voltage |
VIN2 |
OSC |
–0.3 to VDD +0.3 |
V |
|||
|
VIN3 |
VLCD1, VLCD2, VLCD3, VLCD4 |
–0.3 to VLCD +0.3 |
|
|||
Output voltage |
VOUT1 |
OSC, P1 to P4 |
–0.3 to VDD +0.3 |
V |
|||
VOUT2 |
VLCD0, S1 to S95, COM1 to COM10 |
–0.3 to VLCD +0.3 |
|||||
|
|
||||||
|
IOUT1 |
S1 to S95 |
300 |
µA |
|||
Output current |
IOUT2 |
COM1 to COM10 |
3 |
mA |
|||
|
IOUT3 |
P1 to P4 |
5 |
||||
|
|
||||||
Allowable power dissipation |
Pd max |
Ta = 85°C |
200 |
mW |
|||
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Operating temperature |
Topr |
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–40 to +85 |
°C |
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Storage temperature |
Tstg |
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–55 to +125 |
°C |
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Allowable Operating Ranges at Ta = –40 to +85°C, VSS=0V
|
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Parameter |
Symbol |
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Conditions |
|
Ratings |
|
Unit |
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min |
typ |
max |
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VDD |
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VDD |
|
2.7 |
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6.0 |
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||
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VLCD, When the display contrast adjustment |
7.0 |
|
11.0 |
|
|||
Supply voltage |
VLCD |
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circuit is used |
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V |
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VLCD, When the display contrast adjustment |
4.5 |
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11.0 |
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circuit is not used |
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Output voltage |
VLCD0 |
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VLCD0 |
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VLCD4 + 4.5 |
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VLCD |
V |
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VLCD1 |
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VLCD1 |
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3/4 |
VLCD0 |
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VLCD2 |
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VLCD2 |
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2/4 |
VLCD0 |
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Input voltage |
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(VLCD0–VLCD4) |
V |
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VLCD3 |
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VLCD3 |
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1/4 |
VLCD0 |
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(VLCD0–VLCD4) |
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VLCD4 |
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VLCD4 |
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0 |
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1.5 |
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Input high level voltage |
VIH |
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CE, CL, DI, |
INH |
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0.8 VDD |
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6.0 |
V |
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Input low level voltage |
VIL |
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CE, CL, DI, |
INH |
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0 |
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0.2 VDD |
V |
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Recommended external resistance |
ROSC |
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OSC |
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43 |
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kΩ |
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Recommended external capacitance |
COSC |
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OSC |
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680 |
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pF |
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Guaranteed oscillation range |
fOSC |
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OSC |
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25 |
50 |
100 |
kHz |
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Data setup time |
tds |
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CL, DI |
:Figure 2 |
160 |
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ns |
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Data hold time |
tdh |
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CL, DI |
:Figure 2 |
160 |
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ns |
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CE wait time |
tcp |
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CE, CL |
:Figure 2 |
160 |
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ns |
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CE setup time |
tcs |
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CE, CL |
:Figure 2 |
160 |
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ns |
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CE hold time |
tch |
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CE, CL |
:Figure 2 |
160 |
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ns |
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High level clock pulse width |
tø H |
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CL |
:Figure 2 |
160 |
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ns |
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Low level clock pulse width |
tø L |
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CL |
:Figure 2 |
160 |
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ns |
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tc |
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:Figures 3, 4, and 5 |
10 |
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µs |
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INH |
switching time |
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INH, |
CE |
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No. 7160-3/33
LC75848T
Electrical Characteristics for the Allowable Operating Ranges
Parameter |
Symbol |
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Conditions |
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Ratings |
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Unit |
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min |
typ |
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max |
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Hysteresis |
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VH |
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CE, CL, DI, INH |
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0.1 VDD |
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V |
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Input high level current |
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IIH |
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CE, CL, DI, INH: VI = 6.0 V |
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5.0 |
µA |
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Input low level current |
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IIL |
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CE, CL, DI, |
INH: |
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VI = 0 V |
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–5.0 |
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µA |
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VOH1 |
S1 to S95: IO = –20 µA |
VLCD0 – 0.6 |
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Output high level voltage |
VOH2 |
COM1 to COM10: IO = –100 µA |
VLCD0 – 0.6 |
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V |
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VOH3 |
P1 to P4: IO = –1 mA |
VDD – 1.0 |
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VOL1 |
S1 to S95: IO = 20 µA |
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VLCD4 + 0.6 |
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Output low level voltage |
VOL2 |
COM1 to COM10: IO = 100 µA |
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VLCD4 + 0.6 |
V |
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VOL3 |
P1 to P4: IO = 1 mA |
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1.0 |
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2/4 |
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2/4 |
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VMID1 |
S1 to S95: IO = ±20 µA |
(VLCD0 – VLCD4) |
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(VLCD0 – VLCD4) |
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–0.6 |
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+0.6 |
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3/4 |
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3/4 |
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Output middle level voltage *1 |
V |
MID |
2 |
COM1 to COM10: I = ±100 µA |
(V |
LCD |
0 – V 4) |
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(V |
LCD |
0 – V 4) |
V |
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O |
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LCD |
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LCD |
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–0.6 |
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+0.6 |
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1/4 |
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1/4 |
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VMID3 |
COM1 to COM10: IO = ±100 µA |
(VLCD0 – VLCD4) |
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(VLCD0 – VLCD4) |
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–0.6 |
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+0.6 |
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Oscillator frequency |
fosc |
OSC: ROSC = 43 kΩ , COSC = 680 pF |
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40 |
50 |
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60 |
kHz |
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IDD1 |
VDD : Power saving mode |
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5 |
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IDD2 |
VDD: VDD = 6.0 V, outputs open, fosc = 50 kHz |
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200 |
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400 |
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ILCD1 |
VLCD : Power saving mode |
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5 |
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VLCD : VLCD = 11.0 V |
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Current drain |
ILCD2 |
Outputs open |
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500 |
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1000 |
µA |
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fosc = 50 kHz |
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When the display contrast adjustment circuit is used. |
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VLCD : VLCD = 11.0 V |
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ILCD3 |
Outputs open |
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250 |
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500 |
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fosc = 50 kHz |
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When the display contrast adjustment circuit is not used. |
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Note: *1. Excluding the bias voltage generation divider resistor built into VLCD0, VLCD1, VLCD2 , VLCD3, and VLCD4. (See Figure 1.)
No. 7160-4/33
LC75848T
VLCD |
CONTRAST
ADJUSTER
VLCD0 |
VLCD1 |
VLCD2 |
VLCD3 
VLCD4 
To the common and segment drivers
Excluding these resistors
• When CL is stopped at the low level
CE |
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VIH |
tøH |
tø L |
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CL |
50% |
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VIL |
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DI |
VIH |
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VIL |
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tds |
tdh |
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Figure 1
VIH |
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tcp |
tcs |
VIL |
tch |
• When CL is stopped at the high level
CE |
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tø L |
tøH |
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VIH |
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CL |
50% |
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VIL |
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DI |
VIH |
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VIL |
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tds |
tdh |
VIH |
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tcp |
tcs |
VIL |
tch |
Figure 2
No. 7160-5/33
LC75848T
Block Diagram
|
P1 |
P4 |
COM1 |
COM8 |
S95/COM9 |
S94/COM10 S93 |
S1 |
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GENERAL |
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COMMON |
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SEGMENT DRIVER & LATCH |
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PORT |
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DRIVER |
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OSC |
CLOCK |
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CONTROL |
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GENERATOR |
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REGISTER |
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VLCD |
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CONTRAST |
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SHIFT REGISTER |
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ADJUSTER |
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VLCD0 |
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VLCD1 |
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VLCD2 |
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CCB |
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INTERFACE |
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VLCD3 |
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VLCD4 |
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VDD |
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VSS |
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INH |
DI |
CL |
CE |
No. 7160-6/33
LC75848T
Pin Functions
|
Pin |
Pin No. |
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Function |
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Active |
I/O |
Handling |
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when unused |
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S1 to S93 |
1 to 93 |
Segment driver outputs. |
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S94/COM10 |
94 |
The S94/COM10 and S95/COM9 pins can be used as common |
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— |
O |
Open |
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S95/COM9 |
95 |
driver outputs under the control data. |
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COM1 to COM8 |
103 to 96 |
Common driver outputs. |
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— |
O |
Open |
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P1 to P4 |
104 to 107 |
General-purpose output ports. |
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— |
O |
Open |
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Oscillator connection. |
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OSC |
116 |
An oscillator circuit is formed by connecting an external resistor and capacitor at this |
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— |
I/O |
VDD |
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pin. |
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CE |
118 |
Serial data transfer inputs. |
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H |
I |
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These pins are connected to the microcontroller. |
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CE :Chip enable |
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CL |
119 |
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▲ |
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I |
GND |
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CL :Synchronization clock |
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DI |
120 |
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— |
I |
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DI :Transfer data |
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Input that turns the display off and forces the general-purpose output ports low. |
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• When |
INH |
is low (VSS) |
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• Display off |
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S1 to S93 = “L” (V |
4). |
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LCD |
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4) |
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S94/COM10, S95/COM9 = “L” (V |
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LCD |
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COM1 to COM8 = “L” (V |
4). |
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LCD |
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INH |
117 |
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• General-purpose output ports P1 to P4 = low (VSS) |
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L |
I |
GND |
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• When INH is high (VDD) |
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• Display on |
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• The states of the general-purpose output ports can be set by the PC1 to |
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PC4 control data. |
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However, serial data can be transferred when the INH pin is low. |
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LCD drive 4/4 bias voltage (high level) supply pin. The level on this pin can be changed |
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by the display contrast adjustment circuit. |
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VLCD0 |
110 |
However, (VLCD0 – VLCD4) must be greater than or equal to 4.5 V. Also,external power |
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— |
O |
Open |
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must not be applied to this pin since the pin circuit includes the display contrast |
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adjustment circuit. |
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VLCD1 |
111 |
LCD drive 3/4 bias voltage (middle level) supply pin. This pin can be used to supply |
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— |
I |
Open |
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the 3/4 (VLCD0 – VLCD4) voltage level externally. |
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VLCD2 |
112 |
LCD drive 2/4 bias voltage (middle level) supply pin. This pin can be used to supply |
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— |
I |
Open |
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the 2/4 (VLCD0 – VLCD4) voltage level externally. |
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VLCD3 |
113 |
LCD drive 1/4 bias voltage (middle level) supply pin. This pin can be used to supply |
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— |
I |
Open |
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the 1/4 (VLCD0 – VLCD4) voltage level externally. |
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LCD drive 0/4 bias voltage (low level) supply pin. Fine adjustment of the display |
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VLCD4 |
114 |
contrast can be implemented by connecting an external variable resistor to this pin. |
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— |
I |
GND |
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However, (VLCD0 – VLCD4) must be greater than or equal to 4.5 V, and VLCD4 must be |
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in the range 0 V to 1.5 V, inclusive. |
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VDD |
108 |
Logic block power supply connection. Provide a voltage of between 2.7 and 6.0V. |
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LCD driver block power supply connection. Provide a voltage of between 7.0 and 11.0 V |
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VLCD |
109 |
when the display contrast adjustment circuit is used and provide a voltage of between |
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4.5 and 11.0 V when the circuit is not used. |
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VSS |
115 |
Power supply connection. Connect to ground. |
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No. 7160-7/33
LC75848T
Serial Data Transfer Format
1. 1/8 duty
When CL is stopped at the low level
• When the display data is transferred.
CE
CL
DI |
1 |
1 |
0 |
0 |
0 |
0 |
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1 |
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D1 |
D2 |
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D97 |
D98 |
D99 |
D100 |
D101 |
D102 |
D103 |
D104 |
D105 |
D106 |
D107 |
D108 |
D109 |
D110 |
D111 |
D112 |
D113 |
D114 |
D115 |
D116 |
D117 |
D118 |
D119 |
D120 |
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B0 |
B1 |
B2 |
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B3 |
A0 |
A1 |
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A3 |
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CCB |
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Display |
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Fixed |
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DD |
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address |
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data |
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3 bits |
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8 bits |
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120 bits |
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5 bits |
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1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
D121 |
D122 |
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D217 |
D218 |
D219 |
D220 |
D221 |
D222 |
D223 |
D224 |
D225 |
D226 |
D227 |
D228 |
D229 |
D230 |
D231 |
D232 |
D233 |
D234 |
D235 |
D236 |
D237 |
D238 |
D239 |
D240 |
0 |
0 |
0 |
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0 |
0 |
0 |
0 |
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1 |
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B0 |
B1 |
B2 |
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B3 |
A0 |
A1 |
A2 |
A3 |
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CCB |
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Display |
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Fixed |
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DD |
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address |
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data |
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data |
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3 bits |
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8 bits |
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120 bits |
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5 bits |
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1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
D241 |
D242 |
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D337 |
D338 |
D339 |
D340 |
D341 |
D342 |
D343 |
D344 |
D345 |
D346 |
D347 |
D348 |
D349 |
D350 |
D351 |
D352 |
D353 |
D354 |
D355 |
D356 |
D357 |
D358 |
D359 |
D360 |
0 |
0 |
0 |
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0 |
0 |
0 |
1 |
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0 |
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B0 |
B1 |
B2 |
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B3 |
A0 |
A1 |
A2 |
A3 |
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CCB |
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Fixed |
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DD |
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address |
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data |
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3 bits |
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8 bits |
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120 bits |
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5 bits |
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|||||||||||||
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1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
D361 |
D362 |
|
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D457 |
D458 |
D459 |
D460 |
D461 |
D462 |
D463 |
D464 |
D465 |
D466 |
D467 |
D468 |
D469 |
D470 |
D471 |
D472 |
D473 |
D474 |
D475 |
D476 |
D477 |
D478 |
D479 |
D480 |
0 |
0 |
0 |
|
0 |
0 |
0 |
1 |
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1 |
|
||||||||||||||||||||||||||||||||||||||||||||||||||||
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B0 |
B1 |
B2 |
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B3 |
A0 |
A1 |
A2 |
A3 |
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CCB |
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Display |
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Fixed |
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DD |
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address |
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data |
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data |
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3 bits |
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8 bits |
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120 bits |
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5 bits |
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||||||||
|
1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
D481 |
D482 |
|
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|
D577 |
D578 |
D579 |
D580 |
D581 |
D582 |
D583 |
D584 |
D585 |
D586 |
D587 |
D588 |
D589 |
D590 |
D591 |
D592 |
D593 |
D594 |
D595 |
D596 |
D597 |
D598 |
D599 |
D600 |
0 |
0 |
0 |
|
0 |
0 |
1 |
0 |
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0 |
|
||||||||||||||||||||||||||||||||||||||||||||||||||||
|
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B0 |
B1 |
B2 |
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B3 |
A0 |
A1 |
A2 |
A3 |
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|||||||||
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CCB |
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Display |
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Fixed |
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DD |
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||||||||||
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address |
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data |
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data |
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3 bits |
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|||||||||||
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8 bits |
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120 bits |
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5 bits |
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|||||||||
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|||||||||||||
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|||||||||||||
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|||||||||||||
|
1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
D601 |
D602 |
|
|
|
D697 |
D698 |
D699 |
D700 |
D701 |
D702 |
D703 |
D704 |
D705 |
D706 |
D707 |
D708 |
D709 |
D710 |
D711 |
D712 |
D713 |
D714 |
D715 |
D716 |
D717 |
D718 |
D719 |
D720 |
0 |
0 |
0 |
|
0 |
0 |
1 |
0 |
|
1 |
|
||||||||||||||||||||||||||||||||||||||||||||||||||||
|
|
B0 |
B1 |
B2 |
|
B3 |
A0 |
A1 |
A2 |
A3 |
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|||||||||
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CCB |
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Display |
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Fixed |
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DD |
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||||||||||
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address |
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data |
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data |
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3 bits |
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|||||||||||
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8 bits |
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120 bits |
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5 bits |
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|||||||||
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1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
D721 |
D722 |
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D745 |
D746 |
D747 |
D748 |
D749 |
D750 |
D751 |
D752 |
D753 |
D754 |
D755 |
D756 |
D757 |
D758 |
D759 |
D760 |
0 |
0 |
0 |
0 |
0 |
1 |
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1 |
0 |
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B0 |
B1 |
B2 |
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B3 |
A0 |
A1 |
A2 |
A3 |
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CCB |
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Display |
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Fixed |
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DD |
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address |
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data |
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data |
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3 bits |
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8 bits |
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40 bits |
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5 bits |
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|||||||||
• When the control data is transferred.
CE
CL
DI |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
PC1 |
PC2 |
PC3 |
PC4 |
CT0 |
CT1 |
CT2 |
CT3 |
CTC |
SC BU |
FC |
DT1 |
DT2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
|
B0 |
B1 |
B2 |
B3 |
A0 |
A1 |
A2 |
A3 |
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CCB |
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Control |
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DD |
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address |
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data |
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3 bits |
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8 bits |
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21 bits |
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Note: B0 to B3, A0 to A3 ······· CCB address
DD································· Direction data
No. 7160-8/33
LC75848T
When CL is stopped at the high level
• When the display data is transferred.
CE
CL
DI |
1 |
1 |
0 |
|
0 |
0 |
0 |
0 |
1 |
|
D1 |
D2 |
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D97 |
D98 |
D99 |
D100 |
D101 |
D102 |
D103 |
D104 |
D105 |
|
D106 |
D107 |
D108 |
D109 |
D110 |
D111 |
D112 |
D113 |
D114 |
D115 |
D116 |
D117 |
D118 |
D119 |
D120 |
0 |
0 |
0 |
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0 |
0 |
0 |
0 |
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0 |
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|||||||||||||||||||||||||||||||||||||||||||||
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B0 |
B1 |
B2 |
B3 |
A0 |
A1 |
A2 |
A3 |
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CCB |
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Display |
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Fixed |
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DD |
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||||||||||
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address |
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data |
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data |
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3 bits |
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8 bits |
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120 bits |
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5 bits |
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1 |
1 |
0 |
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0 |
0 |
0 |
0 |
1 |
|
D121 |
D122 |
|
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|
D217 |
D218 |
D219 |
D220 |
D221 |
D222 |
D223 |
D224 |
D225 |
|
D226 |
D227 |
D228 |
D229 |
D230 |
D231 |
D232 |
D233 |
D234 |
D235 |
D236 |
D237 |
D238 |
D239 |
D240 |
0 |
0 |
0 |
|
0 |
0 |
0 |
0 |
|
1 |
|
|||||||||||||||||||||||||||||||||||||||||||||
|
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B0 |
B1 |
B2 |
B3 |
A0 |
A1 |
A2 |
A3 |
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||||||||||
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CCB |
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Display |
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Fixed |
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DD |
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||||||||||
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address |
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data |
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data |
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3 bits |
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||||||||||||
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8 bits |
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120 bits |
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5 bits |
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|||||||||||
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1 |
1 |
0 |
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0 |
0 |
0 |
0 |
1 |
|
D241 |
D242 |
|
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D337 |
D338 |
D339 |
D340 |
D341 |
D342 |
D343 |
D344 |
D345 |
|
D346 |
D347 |
D348 |
D349 |
D350 |
D351 |
D352 |
D353 |
D354 |
D355 |
D356 |
D357 |
D358 |
D359 |
D360 |
0 |
0 |
0 |
|
0 |
0 |
0 |
1 |
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0 |
|
|||||||||||||||||||||||||||||||||||||||||||||
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B0 |
B1 |
B2 |
B3 |
A0 |
A1 |
A2 |
A3 |
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CCB |
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Display |
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Fixed |
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DD |
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address |
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data |
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data |
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3 bits |
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8 bits |
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120 bits |
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5 bits |
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1 |
1 |
0 |
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0 |
0 |
0 |
0 |
1 |
|
D361 |
D362 |
|
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|
D457 |
D458 |
D459 |
D460 |
D461 |
D462 |
D463 |
D464 |
D465 |
|
D466 |
D467 |
D468 |
D469 |
D470 |
D471 |
D472 |
D473 |
D474 |
D475 |
D476 |
D477 |
D478 |
D479 |
D480 |
0 |
0 |
0 |
|
0 |
0 |
0 |
1 |
|
1 |
|
|||||||||||||||||||||||||||||||||||||||||||||
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B0 |
B1 |
B2 |
B3 |
A0 |
A1 |
A2 |
A3 |
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||||||||||
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CCB |
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Display |
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Fixed |
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DD |
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|||||||||||
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address |
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data |
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data |
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3 bits |
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||||||||||||
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8 bits |
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120 bits |
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5 bits |
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|||||||||||
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|||||||
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|||||||
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|||||||
|
1 |
1 |
0 |
|
0 |
0 |
0 |
0 |
1 |
|
D481 |
D482 |
|
|
|
D577 |
D578 |
D579 |
D580 |
D581 |
D582 |
D583 |
D584 |
D585 |
|
D586 |
D587 |
D588 |
D589 |
D590 |
D591 |
D592 |
D593 |
D594 |
D595 |
D596 |
D597 |
D598 |
D599 |
D600 |
0 |
0 |
0 |
|
0 |
0 |
1 |
0 |
|
0 |
|
|||||||||||||||||||||||||||||||||||||||||||||
|
|
B0 |
B1 |
B2 |
B3 |
A0 |
A1 |
A2 |
A3 |
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||||||||||
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CCB |
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Display |
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Fixed |
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DD |
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|||||||||||
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address |
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data |
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data |
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3 bits |
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||||||||||||
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8 bits |
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120 bits |
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5 bits |
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|||||||||||
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|||||||
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|||||||
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1 |
1 |
0 |
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0 |
0 |
0 |
0 |
1 |
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D601 |
D602 |
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D697 |
D698 |
D699 |
D700 |
D701 |
D702 |
D703 |
D704 |
D705 |
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D706 |
D707 |
D708 |
D709 |
D710 |
D711 |
D712 |
D713 |
D714 |
D715 |
D716 |
D717 |
D718 |
D719 |
D720 |
0 |
0 |
0 |
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0 |
0 |
1 |
0 |
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1 |
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B0 |
B1 |
B2 |
B3 |
A0 |
A1 |
A2 |
A3 |
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CCB |
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Display |
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Fixed |
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DD |
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address |
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data |
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data |
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3 bits |
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8 bits |
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120 bits |
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5 bits |
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||||
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1 |
1 |
0 |
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0 |
0 |
0 |
0 |
1 |
|
D721 |
D722 |
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D745 |
D746 |
D747 |
D748 |
D749 |
D750 |
D751 |
D752 |
D753 |
|
D754 |
D755 |
D756 |
D757 |
D758 |
D759 |
D760 |
0 |
0 |
0 |
0 |
0 |
1 |
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1 |
0 |
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||||||||||||||||||||||||||||||||||||
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B0 |
B1 |
B2 |
B3 |
A0 |
A1 |
A2 |
A3 |
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||||||||||
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CCB |
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Display |
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Fixed |
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DD |
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|||||||||
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address |
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data |
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data |
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3 bits |
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|||||||
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8 bits |
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40 bits |
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5 bits |
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||||||||
• When the control data is transferred.
CE
CL
DI |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
PC1 PC2 |
PC3 |
PC4 |
CT0 |
CT1 |
CT2 |
CT3 |
CTC |
SC BU |
FC |
DT1 |
DT2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
|
B0 |
B1 |
B2 |
B3 |
A0 |
A1 |
A2 |
A3 |
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CCB |
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Control |
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DD |
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address |
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data |
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3 bits |
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8 bits |
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21 bits |
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Note: B0 to B3, A0 to A3 ······· CCB address
DD································· Direction data
•CCB address: ····83H
•D1 to D760: ········Display data
•PC1 to PC4: ········General-purpose output port state setting data
•CT0 to CT3, CTC: Display contrast setting data
•SC: ·····················Segmenton/off control data
•BU: ·····················Normalmode/power saving mode control data
•FC: ·····················Datathat sets the frame frequency of the common and segment output waveforms
•DT1, DT2: ···········Display technique setting data
No. 7160-9/33
LC75848T
2. 1/9 duty
When CL is stopped at the low level
• When the display data is transferred.
CE
CL
DI |
1 |
1 |
0 |
|
0 |
0 |
0 |
0 |
1 |
|
D1 |
|
D2 |
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D113 |
D114 |
D115 |
D116 |
D117 |
D118 |
D119 |
D120 |
D121 |
D122 |
D123 |
D124 |
D125 |
D126 |
D127 |
D128 |
D129 |
D130 |
D131 |
D132 |
D133 |
D134 |
D135 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
|
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B0 |
B1 |
B2 |
B3 |
A0 |
A1 |
A2 |
A3 |
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||||||||||
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CCB |
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Display |
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Fixed |
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DD |
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|||||||||
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address |
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data |
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data |
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3 bits |
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|||||||||||
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8 bits |
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135 bits |
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6 bits |
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||||||||
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1 |
1 |
0 |
|
0 |
0 |
0 |
0 |
1 |
D136 |
D137 |
|
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|
D248 |
D249 |
D250 |
D251 |
D252 |
D253 |
D254 |
D255 |
D256 |
D257 |
D258 |
D259 |
D260 |
D261 |
D262 |
D263 |
D264 |
D265 |
D266 |
D267 |
D268 |
D269 |
D270 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||
|
B0 |
B1 |
B2 |
B3 |
A0 |
A1 |
A2 |
A3 |
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||||||||||
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CCB |
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Display |
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Fixed |
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DD |
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|||||||||
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address |
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data |
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data |
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3 bits |
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8 bits |
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135 bits |
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6 bits |
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||||||||
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1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
D271 |
D272 |
|
|
|
D383 |
D384 |
D385 |
D386 |
D387 |
D388 |
D389 |
D390 |
D391 |
D392 |
D393 |
D394 |
D395 |
D396 |
D397 |
D398 |
D399 |
D400 |
D401 |
D402 |
D403 |
D404 |
D405 |
0 |
0 |
|
0 |
0 |
|
0 |
0 |
0 |
1 |
|
0 |
|
||||||||||||||||||||||||||||||||||||||||||||||||
|
B0 |
B1 |
B2 |
|
B3 |
A0 |
A1 |
A2 |
A3 |
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|||||||||
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CCB |
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Display |
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Fixed |
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DD |
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||||||||||
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address |
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data |
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data |
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3 bits |
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||||||||||||
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8 bits |
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135 bits |
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6 bits |
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|||||||||
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1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
D406 |
D407 |
|
|
|
|
D518 |
D519 |
D520 |
D521 |
D522 |
D523 |
D524 |
D525 |
D526 |
D527 |
D528 |
D529 |
D530 |
D531 |
D532 |
D533 |
D534 |
D535 |
D536 |
D537 |
D538 |
D539 |
D540 |
0 |
0 |
|
0 |
0 |
|
0 |
0 |
0 |
1 |
|
1 |
|
||||||||||||||||||||||||||||||||||||||||||||||
|
B0 |
B1 |
B2 |
|
B3 |
A0 |
A1 |
A2 |
A3 |
|
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|||||||||
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CCB |
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Display |
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Fixed |
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DD |
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||||||||||
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address |
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data |
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data |
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3 bits |
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||||||||||||
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8 bits |
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135 bits |
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6 bits |
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|||||||||
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|
1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
D541 |
D542 |
|
|
|
D653 |
D654 |
D655 |
D656 |
D657 |
D658 |
D659 |
D660 |
D661 |
D662 |
D663 |
D664 |
D665 |
D666 |
D667 |
D668 |
D669 |
D670 |
D671 |
D672 |
D673 |
D674 |
D675 |
0 |
0 |
|
0 |
0 |
|
0 |
0 |
1 |
0 |
|
0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
|
B0 |
B1 |
B2 |
|
B3 |
A0 |
A1 |
A2 |
A3 |
|
|
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CCB |
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Display |
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Fixed |
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DD |
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address |
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data |
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3 bits |
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8 bits |
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135 bits |
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6 bits |
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1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
D676 |
D677 |
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D788 |
D789 |
D790 |
D791 |
D792 |
D793 |
D794 |
D795 |
D796 |
D797 |
D798 |
D799 |
D800 |
D801 |
D802 |
D803 |
D804 |
D805 |
D806 |
D807 |
D808 |
D809 |
D810 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
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B0 |
B1 |
B2 |
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B3 |
A0 |
A1 |
A2 |
A3 |
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CCB |
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Display |
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Fixed |
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DD |
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address |
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data |
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data |
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3 bits |
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8 bits |
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135 bits |
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6 bits |
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1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
D811 |
D812 |
|
D827 |
D828 |
D829 |
D830 |
D831 |
D832 |
D833 |
D834 |
D835 |
D836 |
D837 |
D838 |
D839 |
D840 |
D841 |
D842 |
D843 |
D844 |
D845 |
D846 |
0 |
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1 |
1 |
0 |
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||
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B0 |
B1 |
B2 |
B3 |
A0 |
A1 |
A2 |
A3 |
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CCB |
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Display |
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DD |
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address |
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data |
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Fixed |
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3 bits |
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8 bits |
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36 bits |
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||||
data 1 bits
• When the control data is transferred.
CE
CL
DI |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
1 |
PC1 |
PC2 |
PC3 |
PC4 |
CT0 |
CT1 |
CT2 |
CT3 |
CTC |
SC |
BU |
FC |
DT1 |
DT2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
|
B0 |
B1 |
B2 |
B3 |
A0 |
A1 |
A2 |
A3 |
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CCB |
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Control |
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DD |
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address |
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data |
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3 bits |
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8 bits |
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21 bits |
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Note: B0 to B3, A0 to A3 ······· CCB address
DD································· Direction data
No. 7160-10/33
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