No. 6144-7/43
LC75817NE, 75817NW
Pin Functions
Pin
Pin No.
Function Active I/O Handling when unused
LC75817NE LC75817NW
Segment driver outputs.
The S60/COM10 pin can be used as common driver output
under the “set display technique” instruction.
OPEN— O
S1 to S59
S60/COM10
3 to 61621 to 59
60
Common driver outputs. OPEN— OCOM1 to COM9 71 to 63 69 to 61
Oscillator connections. An oscillator circuit is formed by
connecting an external resistor and capacitor at these pins.
GND— IOSCI 97 95
Serial data interface connections to the controller. Note that DO,
being an open-drain output, requires a pull-up resistor.
CE : Chip enable
CL : Synchronization clock
DI : Transfer data
DO: Output data
GND
H ICE 100 98
ICL 1 99
— IDI 2 100
OPEN— OOSCO 96 94
Input that turns the display off, disables key scanning, and
forces the general-purpose output ports low.
• When INH is low (V
SS
):
• Display off
S1 to S59 = “L” (V
LCD
4).
S60/COM10 = “L” (V
LCD
4).
COM1 to COM9 = “L” (V
LCD
4).
• General-purpose output ports P1 to P4 = low (V
SS
)
• Key scanning disabled: KS1 to KS6 = low (V
SS
)
• All the key data is reset to low.
• When INH is high (V
DD
):
• Display on
• The state of the general-purpose output ports can
be set by executing a "Set general-purpose output
port state" instruction.
• Key scanning is enabled.
However, serial data can be transferred when the INH pin is
low.
V
DD
L IINH 98 96
LCD drive 3/4 bias voltage (middle level) supply pin. This pin can
be used to supply the 3/4 (V
LCD
0 – V
LCD
4) voltage level externally.
OPEN— I
V
LCD
1
90 88
LCD drive 2/4 bias voltage (middle level) supply pin. This pin can
be used to supply the 2/4 (V
LCD
0 - V
LCD
4) voltage level externally.
OPEN— I
V
LCD
2
91 89
LCD drive 1/4 bias voltage (middle level) supply pin. This pin can
be used to supply the 1/4 (V
LCD
0 – V
LCD
4) voltage level externally.
OPEN— I
V
LCD
3
92 90
Logic block power supply connection. Provide a voltage of
between 4.5 and 6.0 V.
—— —
V
DD
87 85
LCD driver block power supply connection. Provide a voltage of
between 7.0 and 10.0 V when the display contrast adjustment
circuit is used and provide a voltage of between 4.5 and 10.0 V
when the circuit is not used.
—— —
V
LCD
88 86
Power supply connection. Connect to ground.
—— —
V
SS
94 92
Key scan outputs. Although normal key scan timing lines
require diodes to be inserted in the timing lines to prevent
shorts, since these outputs are unbalanced CMOS transistor
outputs, these outputs will not be damaged by shorting when
these outputs are used to form a key matrix.
OPEN— OKS1 to KS6 72 to 77 70 to 75
Key scan inputs.
These pins have built-in pull-down resistors.
GNDH IKI1 to KI5 78 to 82 76 to 80
General-purpose output ports OPEN— OP1 to P4 83 to 86 81 to 84
DO 99 97 — O OPEN
This pin must be connected to ground. —— I
TEST
95 93
LCD drive 4/4 bias voltage (high level) supply pin. The level on
this pin can be changed by the display contrast adjustment circuit.
However, (V
LCD
0 – V
LCD
4) must be greater than or equal to 4.5
V. Also, external power must not be applied to this pin since the
pin circuit includes the display contrast adjustment circuit.
OPEN—
O
V
LCD
0
89 87
LCD drive 0/4 bias voltage (low level) supply pin. Fine
adjustment of the display contrast can be implemented by
connecting an external variable resistor to this pin.
However, (V
LCD
0 – V
LCD
4) must be greater than or equal to 4.5
V, and VLCD4 must be in the range 0 V to 1.5 V, inclusive.
GND— I
V
LCD
4
93 91