SANYO LC74798M, LC74798 Datasheet

Overview
The LC74798 and LC74798M are on-screen display controller CMOS ICs that display characters and patterns on the TV screen under microprocessor control. These ICs include a built-in PDC/VPS/UDT interface circuit.
Features
• Display format: 24 characters by 12 rows (Up to 288 characters)
• Character format: 12 (horizontal) × 18 (vertical) dots
• Character sizes: Three sizes each in the horizontal and vertical directions
• Characters in font: 128
• Initial display positions: 64 horizontal positions and
64 vertical positions
• Blinking: Specifiable in character units
• Blinking types: Two periods supported: 1.0 second and
0.5 second
• Blanking: Over the whole font (12 × 18 dots)
• Background color
— 8 colors (internal synchronization mode): 4fSC — 6 colors (internal synchronization mode): 2fSC — Blue background only: NTSC
• Line background color
— Three lines can be set up. — 8 line background colors (in internal synchronization
mode): 4fSC
— 6 line background colors (in internal synchronization
mode): 2fSC
• External control input: 8-bit serial input format
• On-chip sync separator and AFC circuits
• On-chip PDC/VPS/UDT interface circuit
• Video outputs: PAL and NTSC format composite video
outputs
• Package: DIP30SD (400 mil)
MFP30S (375 mil)
Package Dimensions
unit: mm
3193-DIP30SD
unit: mm
3216-MFP30S
CMOS IC
51898RM (OT) No. 5833-1/32
SANYO: DIP30SD
[LC74798]
SANYO: MFP30S
[LC74798M]
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
On-Screen Display Controller IC
LC74798, 74798M
Ordering number : EN5833
Pin Assignment
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LC74798, 74798M
No. 5833-3/32
LC74798, 74798M
Pin Descriptions
Pin No. Pin name Function Notes
Ground Ground connection (digital system ground)1
VSS1
Crystal oscillator (MUTE input)
These pins are used either to connect the crystal and capacitors used to form an external crystal oscillator circuit to generate the internal synchronizing signals, or to input an external clock signal (2fsc or 4fsc). As a mask option, the Xtal
OUT
pin can be set to function as the MUTE input pin. When this pin is set low, the video output is held at the pedestal level. (A pull-up resistor is built in and the input has hysteresis characteristics.)
Crystal oscillator input switching (CHABLK output)
Switches the mode between external clock input and crystal oscillator operation. A low level selects crystal oscillator operation and a high level selects external clock input. As a mask option, the CTRL1 input pin can be set to function as the CHABLK (character · frame) output. This is a 3-value output.
2
Xtal
IN
3
Xtal
OUT
(MUTE)
4
CTRL1
(CHABLK)
Enable input 2
Enable input for the PDC/VPS data output. Data output is enabled when this input is low. A pull-up resistor is built in and the input has hysteresis characteristics.
5 CS2
Clock input 2
Clock input for the PDC/VPS data output. A pull-up resistor is built in and the input has hysteresis characteristics.
6 SCLK2
Data output
PDC/VPS data output. (This can be either an n-channel open-drain output or a CMOS output.)
7DOUT
External synchronizing signal judgment output
Outputs the state of the external synchronizing signal presence/absence judgment. Outputs a high level when synchronizing signals are present. Outputs the crystal oscillator clock when CS1 and RST are low. (This signal is not output on command resets.)
8
SYNC
JDG
Enable input 1
Enable input for the OSD serial data input. Serial data input is enabled when this pin is low. A pull-up resistor is built in and the input has hysteresis characteristics.
9 CS1
Clock input 1
Serial data input enable pin. A pull-up resistor is built in and the input has hysteresis characteristics.
10 SCLK1
Data input 1 Serial data input. A pull-up resistor is built in and the input has hysteresis characteristics.11 SIN1 Power supply Composite video signal level adjustment power supply (analog system power supply)12
VDD2
Charge pump output Charge pump output. Connect a low-pass filter to this pin.13
CP
OUT
Oscillator control voltage input VCO oscillator control voltage input. (For data slicing)14 VCOIN Ground Ground (VCO ground)15
VSS3
Oscillator range adjustment VCO oscillator range adjustment resistor connection16
VCO
R
Oscillator control voltage input 2 VCO oscillator control voltage input. For character display.17
VCOIN2
Power supply (+5 V) Power supply (+5 V: VCO power supply)18
VDD3
Video signal output Composite video signal output19
CV
OUT
Ground Ground (analog system ground)20
VSS2
Video signal input Composite video signal input21
CV
IN
Video signal input SECAM chrominance signal input22
CV
CR
Power supply (+5 V) Power supply (+5 V: digital system power supply)23
VDD1
Sync separator circuit input Video signal input to the internal sync separator circuit24
SYN
IN
Sync separator circuit adjustment Internal sync separator circuit adjustment25 SEPC
Composite synchronizing signal output
Internal sync separator circuit composite synchronizing signal output. Can be switched to function as a signal (high, low, or ST. pulse) output by the MOD0 setting when SEL0 is high.
26
SEP
OUT
Vertical synchronizing signal input
Inputs the vertical synchronizing signal created by integrating the SEP
OUT
pin output signal. An integration circuit must be connected between this pin and the SEP
OUT
pin. This pin
must be tied to V
DD
1 if unused. This pin is valid when CTL3 is set high.
27
SEP
IN
Background color phase adjustment Background color phase adjustment resistor connection28 CDLR
Reset input
System reset input. A pull-up resistor is built in and the input has hysteresis characteristics.
29 RST
Power supply (+5 V) Power supply (+5 V: digital system power supply)30
VDD1
Note *: A capacitor of at least 2000 pF must be connected between the VDD1 power supply and VSS1.
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LC74798, 74798M
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage V
DD
max VDD1 and VDD2V
SS
– 0.3 to VSS+ 7.0 V
Maximum input voltage V
IN
All input pins VSS– 0.3 to VDD+ 0.3 V
Maximum output voltage V
OUT
D
OUT
, SEP
OUT
, SYNC
JDG
VSS– 0.3 to VDD+ 0.3 V Allowable power dissipation Pd max Ta = 25°C 350 mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –40 to +125 °C
Specifications
Absolute Maximum Ratings
Parameter Symbol Conditions
Ratings
Unit
min typ max
Supply voltage
V
DD
1VDD1 and VDD2 4.5 5.0 5.5 V
V
DD
2VDD2 4.5 5.0 1.27 VDD1V
Input high-level voltage
V
IH
1 RST, CS1, CS2, SIN1, SCLK1, SCLK2, MUTE 0.8 VDD1V
DD
1 + 0.3 V
V
IH
2 CTRL1 0.7 VDD1V
DD
1 + 0.3 V
Input low-level voltage
V
IL
1 RST, CS1, CS2, SIN1, SCLK1, SCLK2, MUTE VSS– 0.3 0.2 VDD1V
V
IL
2 CTRL1 VSS– 0.3 0.3 VDD1V
Pull-up resistance R
PU
RST, CS1, CS2, SIN1, SCLK1, SCLK2, MUTE
25 50 90 k
Applies to pins set up by options. Composite video signal input VIN1CVINand CVCR: VDD1 = 5 V 2.0 Vp-p voltage V
IN
2 SYNIN: VDD1 = 5 V 1.5 2.0 2.5 Vp-p
Input voltage V
IN
3
Xtal
IN
(when used for external clock input)
0.10 5.0 Vp-p
f
IN
= 2fsc or 4fsc: VDD1 = 5 V
Oscillator frequencies F
OSC
1
Xtal
IN
and Xtal
OUT
oscillator pins (2fsc : PAL) 8.867 MHz
Xtal
IN
and Xtal
OUT
oscillator pins (4fsc : PAL) 17.734 MHz
Allowable Operating Ranges
Note: Applications must be especially cautious about noise when using the XtalINinput pin in clock input mode.
Parameter Symbol Conditions
Ratings
Unit
min typ max
Input off leakage current I
leak
1CVINand CV
CR
A
Output off leakage current I
leak
2CV
OUT
A
Output high-level voltage V
OH
1
D
OUT
, SEP
OUT
, CP
OUT
, and SYNC
JDG
3.5 V
V
DD
1 = 4.5 V, IOH= –1.0 mA
Output low-level voltage V
OL
1
D
OUT
, SEP
OUT
, CP
OUT
, and SYNC
JDG
1.0 V
V
DD
1 = 4.5 V, IOL= –1.0 mA
H3.35.0V
Three-value output voltage V
O
CHABLK: VDD1 = 5.0 V M 1.8 2.3 V
L00.8V
I
IH
RST, CS1, CS2, SIN, SCLK1, SCLK2, CTRL1, MUTE,
A
Input current
SEP
IN
, VCOIN, and VCOIN2, VIN= VDD1
I
IL
CTRL1, SEPIN, VCOIN, and VCOIN2, VIN= VSS1–1 µA
I
DD
1
V
DD
1: With all outputs open
40 mA
Operating mode current drain
Xtal : 17.734 MHz, VCO : 27 MHz
IDD2VDD2 : VDD2 = 5 V 20 mA
CV
OUT:VDD
1 = 5.0 V,
(1) 0.80 V
SYNC level V
SN
VDD2 = 5.0 V
(2) 1.00 V (3) 1.40 V
CV
OUT:VDD
1 = 5.0 V,
(1) 1.37 V
Pedestal level V
PD
VDD2 = 5.0 V
(2) 1.57 V (3) 1.97 V
CV
OUT:VDD
1 = 5.0 V,
(1) 1.07 V
Color burst low level V
CBL
VDD2 = 5.0 V
(2) 1.27 V (3) 1.67 V
CV
OUT:VDD
1 = 5.0 V,
(1) 1.67 V
Color burst high level V
CBH
VDD2 = 5.0 V
(2) 1.87 V (3) 2.27 V
Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified.
Continued on next page.
No. 5833-5/32
LC74798, 74798M
Continued from preceding page.
Notes: (1): When the sync level = 0.8 V
(2): When the sync level = 1.0 V (3): When the sync level = 1.4 V The values in parentheses for the background high and low levels are for blue background mode.
Note: The OSD timing applies when the CMOS output circuit type is used.
Parameter Symbol Conditions
Ratings
Unit
min typ max
CV
OUT:VDD
1 = 5.0 V,
(1) 1.23 (1.16) V
Background color low level V
RSL
VDD2 = 5.0 V
(2) 1.43 (1.36) V (3) 1.83 (1.76) V
CV
OUT:VDD
1 = 5.0 V,
(1) 2.37 (2.01) V
Background color high level V
RSH
VDD2 = 5.0 V
(2) 2.57 (2.21) V (3) 2.97 (2.61) V
CV
OUT:VDD
1 = 5.0 V,
(1) 1.50 V
Frame level 0 V
BK
0
V
DD
2 = 5.0 V
(2) 1.70 V (3) 2.10 V
CV
OUT:VDD
1 = 5.0 V,
(1) 2.08 V
Frame level 1 V
BK
1
V
DD
2 = 5.0 V
(2) 2.28 V (3) 2.68 V
CV
OUT:VDD
1 = 5.0 V,
(1) 2.65 V
Character level V
CHA
VDD2 = 5.0 V
(2) 2.85 V (3) 3.25 V
Parameter Symbol Conditions
Ratings
Unit
min typ max
OSD write (See figure 1.)
Minimum input pulse width
t
W (SCLK)
SCLK1 200 ns
t
W (CS1)
CS1 (The period when CS1 is high) 1 µs
Data setup time
t
SU (CS1)
CS1 200 ns
t
SU (SIN)
SIN1 200 ns
Data hold time
t
h (CS1)
CS1 2 µs
t
h (SIN)
SIN1 200 ns
One word write time
t
word
The 8-bit data write time 4.2 µs
t
wt
The RAM data write time 1 µs PDC/VPS write (For the n-channel open-drain output circuit type. See figure 2)
t
CKCY
SCLK2 2 µs
Minimum input pulse width t
CKL
SCLK2 1 µs
t
CKH
SCLK2 1 µs
Setup time t
ICK
SCLK2 10 µs
Output delay time t
CKO
DOUT 0.5 µs
Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ±0.5 V
Figure 1 OSD Serial Data Input Timing
Figure 2 PDC/VPS Serial Output Test Conditions (For the n-channel open-drain output circuit type.)
Note: DOUT goes to the high-impedance state while CS2 is high.
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<Test Load>
System Block Diagram
No. 5833-7/32
LC74798, 74798M
HSYNC peak hold
(HSYNC slicing)
Data output
buffer
Output control
Data peak hold
circuit
(data slicing)
Pedestal clamp
Sync
discrimination
Composite
sync signal
separation
control
Data slicer
Serial
parallel
converter
8-bit
latch
+
command
decoder
Horizontal
character
size
register
Vertical
character
size
Horizontal
size
counter
Vertical
size
counter
Horizontal
dot
counter
Horizontal
display
position
Vertical
display
position
Vertical
dot
counter
Blinking and
reverse
video control
Blinking and
reverse
video control
Display
control
register
RAM write
address
counter
Display RAM
Decoder
Character output
control
Background control
Video output control
Vertical
display
position
Horizontal
display
position
Line
control
counter
Decoder
Font ROM
Shift register
Character
control
counter
Timing generator
Sync signal
generator
AFC circuit
for character
display
AFC circuit
data slicing
Display Control Commands
Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of a command identification code in the first byte and command data in the following bytes. The following commands are supported. 1 COMMAND0: Display memory (VRAM) write address setup command 2 COMMAND1: Display character data write command 3 COMMAND2: Vertical display start position and vertical character size setup command 4 COMMAND3: Horizontal display start position and horizontal character size setup command 5 COMMAND4: Display control setup command 6 COMMAND5: Display control setup command 7 COMMAND6: Synchronizing signal detection setup command 8 COMMAND7 to COMMAND12: Display control setup commands 9 COMMAND13 to COMMAND17: VPS/PDC control commands
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LC74798, 74798M
Display Control Command Table
First byte Second byte
Command
Command identification code
Data Data
7654321076543210 COMMAND0 1000V3V2V1V0000H4H3H2H1H0 (Write address setup) COMMAND1 10010000atc6c5c4c3c2c1c0 (Character write) COMMAND2 (Vertical character size 1010VSVSVSVS0FSVPVPVPVPVPVP and vertical display start position) 21 20 11 10 5 43210 COMMAND3 (Horizontal character size 1011HSHSHSHS00HPHPHPHPHPHP and horizontal display start position) 21 20 11 10 5 43210 COMMAND4 1100TSTRAMOSCSYS0BLKBLKBLKBKBKRVDSP (Display control) MOD ERS STP RST 2 1 0 1 0 ON COMMAND5 1101NP1NP0NONINT0RSHHLFBCLCBPHPHPH (Display control) LV2 INT 2 1 0 COMMAND6 1110SELMODDISMUT0RNRNRNSNSNSNSN (Synchronizing signal detection) 0 0 LIN 2 1 03210 COMMAND7 111100000CINCINVNPVSPMSKMSKEGL (Display control) SEL CTL SEL SEL ERS SEL COMMAND8 111100010LNALNALNALNALPALPALPA (Display control) 3210210 COMMAND9 111100100LNBLNBLNBLNBLPBLPBLPB (Display control) 3210210 COMMAND10 111100110LNCLNCLNCLNCLPCLPCLPC (Display control) 3210210 COMMAND11 1111010000VSPVSPLNCMODLNBMOD (Display control) DCK SLC SEL 3 SEL 2 COMMAND12 111101010VINVINSELHLFSELSELCTL (Display control) NP 2 22 TON 2 1 3 COMMAND13 111101100CPACPA0VPMVPMVPMVPM (VPS/PDC control) 10 3210 COMMAND14 111101110VMWVMWHBSHBSBMSEMSDCE (VPS/PDC control) SE2 SEL 2 1 COMMAND15 1111100000ECVECVECVECVECVECV (VPS/PDC control) 15 14 13 12 11 5 COMMAND16 111110010ECPECPECPECPECPECPECP (VPS/PDC control) 19 18 17 16 15 14 13 COMMAND17 1111101000ECPECPECPECPECPECP (VPS/PDC control) 25 24 23 22 21 20
Once written, a first byte command identification code is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74798/M locks into the display character data write mode, and another first byte cannot be written. When the CS pin is set high, the LC74798/M is set to the COMMAND0 (display memory write address setup mode) state.
COMMAND0 (Display memory write address setup command)
COMMAND1 (Display character data write setup command)
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LC74798, 74798M
• First byte
DA
Register
Contents
Notes
0 to 7 State Function
7— 1 6— 0 5— 0 4— 0
3V3
0 1
2V2
0 1
1V1
0 1
0V0
0 1
Command 0 identification code. Sets the display memory write address.
Display memory line address (0 to B hexadecimal)
• Second byte
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
DA
Register
Contents
Notes
0 to 7 State Function
7 0 Second byte identification bit 6— 0 5— 0
4H4
0 1
3H3
0 1
2H2
0 1
1H1
0 1
0H0
0 1
Display memory column address (0 to 17 hexadecimal)
• First byte
DA
Register
Contents
Notes
0 to 7 State Function
7— 1 6— 0 5— 0 4— 1 3— 0 2— 0 1— 0 0— 0
Command 1 identification code. Sets up display character data write mode.
When this command is input, the LC74798/M locks in the display character data write mode until the CS pin goes high
No. 5833-10/32
LC74798, 74798M
• Second byte
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
DA
Register
Contents
Notes
0 to 7 State Function
7at
0 Character attribute off 1 Character attribute on
6c6
0 1
5c5
0 1
4c4
0 1
3c3
0 1
2c2
0 1
1c1
0 1
0c0
0 1
Character code (00 to 7F hexadecimal)
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
COMMAND2 (Vertical display start position and vertical character size setup command)
• First byte
DA
Register
Contents
Notes
0 to 7 State Function
7— 1 6— 0 5— 1 4— 0
3 VS21
0 1
2 VS20
0 1
1 VS11
0 1
0 VS10
0 1
Command 2 identification code. Sets the vertical display start position and the vertical character size.
Second line vertical character size
First line vertical character size
• Second byte
DA
Register
Contents
Notes
0 to 7 State Function
7 0 Second byte identification bit
6FS
0 Crystal oscillator frequency: 2fsc 1 Crystal oscillator frequency: 4fsc
5
VP5 0
(MSB) 1
4 VP4
0 1
3 VP3
0 1
2 VP2
0 1
1 VP1
0 1
0
VP0 0
(LSB) 1
The vertical display start position is set by the 6 bits VP0 to VP5. The weight of bit 1 is 2H.
If VS is the vertical display start position then:
5
VS = H ×(2 ∑ 2nVPn
)
n=0
H: the horizontal synchronization pulse period
Character
display area
01 0 1H/dot 2H/dot 1 3H/dot 1H/dot
VS21
VS20
01 0 1H/dot 2H/dot 1 3H/dot 1H/dot
VS11
VS10
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