SANYO LC74792JM, LC74792 Datasheet

Ordering number : EN*5965

40299RM (OT) No. 5965-1/25

Overview

The LC74792/JM is a CMOS IC that provides PDC, VPS, and UDT data acquisition functions. The LC74792/JM supports microprocessor control of its operating modes and microprocessor read out of data acquired in any of its operating modes.

Features

• VPS data acquisition (5 or 11 to 15 bytes) VPS: Video Program System

• PDC (8/30/2) data acquisition (13 to 25 bytes) PDC: Program Delivery Control

• UDT (8/30/1) data acquisition (13 to 25 bytes) UDT: Unified Date and Time

• Header (X/00) data acquisition (14 to 45 bytes)

• Status display (8/30/1, 8/30/2) data acquisition (26 to 45 bytes)

• Automatic VPS/PDC discrimination mode

• Built-in AFC and sync separator circuits

• Synchronization discrimination circuit

Package Dimensions

unit: mm

3067-DIP24S

unit: mm

3112-MFP24S

0.48

3.25

3.3

3.9max

0.51min

21.2

0.81 1.78

0.25

7.62

6.4

0.95

Preliminary

SANYO: DIP24S

[LC74792]

112

12.6

0.8

1.0

0.15

0.35

5.4

6.35

7.6

0.625

1.8max

1.5

0.1

SANYO: MFP24S

[LC74792JM]

LC74792, 74792JM

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

VPS / PDC Slicer IC

CMOS IC

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

Pin Assignment

No. 5965-2/25

LC74792, 74792JM

No. 5965-3/25

LC74792, 74792JM

Pin Functions

Pin No. Pin Function Description

1 V

1 Ground Digital system ground

2 Xtal

Crystal oscillator connections

Connections for the crystal element and capacitors that form the crystal oscillator. Also

3 Xtal

OUT

used for external clock input (fsc, 2fsc, or 4fsc).

4 CTRL1 Crystal element switching

Switches between external clock input mode and crystal oscillator mode. Set this pin low

for crystal oscillator, and high for external clock input. 5 CS Enable input pin Enable input pin (hysteresis input) 6 SIO Data input/output pin Data input/output pin (hysteresis input)

7 SCLK Clock input pin Clock input pin (hysteresis input)

External synchronizing signal presence/absence discrimination status output. 8 SYNC

JDG

External synchronizing signal A high level is output when synchronizing signals are present. discrimination output This pin outputs the crystal oscillator clock when the RST pin is low.

(This reset state output can be disabled with command input.) 9 Hout Horizontal synchronizing signal output Horizontal synchronizing signal output

10 VSS2 Ground Ground. (VCO circuit ground) 11 CP

OUT

Charge pump output Charge pump output. Connect a low-pass filter to this pin.

12 VCO

Oscillator control voltage input VCO oscillation control voltage input 13 VCOR Oscillator range adjustment VCO oscillation range adjustment resistor connection 14 DAV Data acquisition output Outputs a low level when PDC/VPS data has been discriminated 15 V

2 Power supply (+5 V) Power supply (+5 V) (VCO system power supply)

16 SYN

Sync separator circuit input Internal sync separator circuit video signal input 17 SEPC Slice level output Slice level verification 18 SEP

OUT

Composite synchronizing signal output Internal sync separator circuit composite synchronizing signal output

Inputs the vertical synchronizing signal by integrating the SEP

OUT

pin output signal.

19 SEP

Vertical synchronizing signal input Applications must connect the SEP

OUT

pin to this pin through an integration circuit. If

unused, connect this pin to VDD1. (This pin is enabled when CTRL2 is high.) Vertical synchronizing signal output

20 Vout Vertical synchronizing signal output This pin outputs the VCO clock when the RST pin is low.

(This reset state output can be disabled with command input.) Controls whether or not the VSYNC vertical synchronizing signal is input to the SEP

21 CTRL2 SEPINinput control

input. When low: The VSYNC signal is not input. (The internal vertical separation circuit is used.) When high: The VSYNC signal is input.

22 CDLR Clock phase adjustment Connection for the clock phase adjustment resistor 23 RST Reset input

System reset input. A pull-up resistor is built in. (This input has hysteresis characteristics.)

24 V

1 Power supply (+5 V) Power supply. (+5 V: digital system power supply)

No. 5965-4/25

LC74792, 74792JM

Parameter Symbol Conditions Ratings Unit

Supply voltage V

max VDD1 and VDD2 VSS– 0.3 to VSS+ 7.0 V

Input voltage V

All input pins VSS– 0.3 to VDD1 + 0.3 V

Output voltage V

OUT

SIO, SYNCJDG, SEPOUT, DAV, HOUT, and VOUT VSS– 0.3 to VDD1 + 0.3 V Allowable power dissipation Pd max Ta = 25°C 350 mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –40 to +125 °C

Specifications

Absolute Maximum Ratings

Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage V

1 VDD1 and VDD2 4.5 5.0 5.5 V

1 CS, SIO and SCLK 0.8 VDD1 5.5 V

High-level input voltage V

2 RST 0.8 VDD1 VDD1 + 0.3 V

3 CTRL1 and CTRL2 0.7 VDD1 VDD1 + 0.3 V

Low-level input voltage

1 RST, CS, SIO and SCLK VSS– 0.3 0.2 VDD1 V

2 CTRL1 and CTRL2 VSS– 0.3 0.3 VDD1 V

Pull-up resistance R

RST 25 50 90 kΩ

Composite video signal input voltage

VIN1 SYN

VDD1 = 5 V 1.5 2.0 2.5 Vp-p

Input voltage V

Xtal

(in external clock input mode)

1 = 5 V 0.10 5.0 Vp-p

fin = fsc, 2fsc, or 4fsc

OSC

1 The XtalINand Xtal

OUT

oscillator pins (4fsc: PAL) 17.734 MHz

Oscillator frequency F

OSC

2 The XtalINand Xtal

OUT

oscillator pins (2fsc: PAL) 8.867 MHz

OSC

3 The XtalINand Xtal

OUT

oscillator pins (fsc: PAL) 4.433 MHz

Recommended Operating Conditions

Note that adequate measure must be taken to prevent noise from entering the XtalINpin when it is used in clock input mode.

No. 5965-5/25

LC74792, 74792JM

Parameter Symbol Applicable pins Conditions

Ratings

Unit

min typ max

Output off leakage current Ileak2 DAV and SIO 1 µA High-level output voltage VOH1

SEPOUT, CPOUT, SYNCJDG, V

1 = 4.5 V,

3.5 V

HOUT, and VOUT I

= –1.0 mA

SEPOUT, CPOUT, SYNCJDG, V

1 = 4.5 V

1.0 V

Low-level output voltage

DAV, HOUT, and VOUT I

= 1.0 mA

2 SIO

1 = 5.0 V

0.4 V

= 3.0 mA

RST, SIO, SCLK, CTRL1, CTRL2,

= VDD1 1 µA

Input current

VCOIN

SIO, SCLK, CTRL1, CTRL2,

= VSS1 –1 µA

VCOIN

With all outputs open

Operating current drain I

1 VDD1 and VDD2 and a 17.734 MHz 40 mA

crystal

Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified.

Parameter Symbol Conditions

Ratings

Unit

min typ max

Minimum input pulse width

tw (sclk) SCLK 200 ns

tw (cs) CS pin (while CS = "H") 1 µs

Data setup time

tsu (cs) CS 200 ns

tsu (sin) SIN 200 ns

Data setup time

th (cs) CS 2 µs th (sin) SIN 200 ns

1-word write time

tword 8-bit data write time 4.2 µs

twt RAM data write time 1 µs

Timing Characteristics

[Write] (Refer to Figure 1) at Ta = –30 to +70°C, VDD1 = 5±0.5 V

Parameter Symbol Conditions

Ratings

Unit

min typ max

CKCY

SCLK 2 µs

Minimum input pulse width t

CKL

SCLK 1 µs

CKH

SCLK 1 µs

Data setup time t

ICK

SCLK 10 µs

Output delay time t

CKO

SIO 0.5 µs

[Read] (Refer to Figure 2) (in case of N-ch open-drain type) at Ta = –30 to +70°C, VDD1 = 5±0.5 V

Note: In case of CMOS output type, depends on OSD timing.

No. 5965-6/25

LC74792, 74792JM

Figure 1 Serial Data Input Timing

(Test load)

Figure 2 Serial Data Input Timing (in case of N-ch open-drain type)

System Block Diagram

No. 5965-7/25

LC74792, 74792JM

Sync separator and data

separator circuit

Synchronization

recognition circuit

Vertical

separator

circuit

Timing generator

AFC circuit (VCO)

Data acquisition circuit

Data latch

circuit

Interface

Control Commands

The control commands have an 8-bit serial input format. Commands consist of a command identification code in the first byte and data in the following bytes. Command 00: Data read mode set command Command 0: Clock control command Command 1: VPS/PDC control command 1 Command 2: VPS/PDC control command 2 Command 3: Synchronizing signal detection command 1 Command 4: Synchronizing signal detection command 2 Command 5: Output control command 1 Command 6: Output control command 2 Command 7: VPS/PDC control command 3 Command 8: VPS/PDC control command 4 Command 9: VPS/PDC control command 5 Command 10: VPS/PDC control command 6

Once written, the first byte command identification code is retained until the next first byte is written. Data is written in second byte only continuous mode. (Automatic increment) If COMMAND00 read mode is written, the read mode becomes fixed. The read mode is cancelled with CS "H".

No. 5965-8/25

LC74792, 74792JM

Display Control Commands: 3-wire type

First byte Second byte

Command Command ID code Data Data

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

COMMAND00 read mode 1 0 0 0 0 0 0 0 Data read COMMAND0 (Clock control) 1 1 1 1 0 0 0 0 0 FS FS2 FS3 O TST O SYS

MOD RST

COMMAND1 (VPS/PDC control 1) 1 1 1 1 0 0 0 1 0 CPA CPA CPA VPM VPM VPM VPM

2 1 0 3 2 1 0

COMMAND2 (VPS/PDC control 2) 1 1 1 1 0 0 1 0 0 VMW VMW HBS HBS BMS EMS DCE

SE2 SEL 2 1

COMMAND3

(Synchronizing signal detection 1)

1 1 1 1 0 0 1 1 0 RN RN RN SN SN SN SN

2 1 0 3 2 1 0

COMMAND4

(Synchronizing signal detection 2)

1 1 1 1 0 1 0 0 0 0 RNE SJN SJN SJN SJC SJC

0 3 2 1 1 0

COMMAND5 (Output control 1) 1 1 1 1 0 1 0 1 0 SP0 SP0 SP0 SJ0 SJ0 VNP VSP

2 1 0 1 0 SEL SEL

COMMAND6 (Output control 2) 1 1 1 1 0 1 1 0 0 0 NP1 NP0 VI0 HI0 V0T H0T

SET SET KST KST

COMMAND7 (VPS/PDC control 3) 1 1 1 1 0 1 1 1 0 0 ECV ECV ECV ECV ECV ECV

15 14 13 12 11 5

COMMAND8 (VPS/PDC control 4) 1 1 1 1 1 0 0 0 0 ECP ECP ECP ECP ECP ECP ECP

19 18 17 16 15 14 13

COMMAND9 (VPS/PDC control 5) 1 1 1 1 1 0 0 1 0 0 ECP ECP ECP ECP ECP ECP

25 24 23 22 21 20

COMMAND10 (VPS/PDC control 6) 1 1 1 1 1 0 1 0 0 HXA LKA MSK KMW SLH SLH SLH

LL2 SLC H1 3 2 1

+ 17 hidden pages