SANYO LC321664AT-80, LC321664AM-80, LC321664AJ-80 Datasheet

Ordering number : EN4795C

32896HA (OT)/O3194TH/81094TH (OT) No. 4795-1/30

Overview

The LC321664AJ, AM, AT is a CMOS dynamic RAM operating on a single 5 V power source and having a 65536-word × 16-bit configuration. Equipped with large capacity capabilities, high-speed transfer rates and low power dissipation, this series is suited for a wide variety of applications ranging from computer main memory and expansion memory to commercial equipment. Address input utilizes a multiplexed address bus which permits it to be enclosed in compact plastic packages of SOJ 40-pin, SOP 40-pin and TSOP 44-pin. Refresh rates are within 4 ms with 256 row address (A0 to A7) selection and support RAS-only refresh, CAS-before-RAS refresh and hidden refresh settings. There are functions such as page mode, read-modifywrite, and byte-write.

Features

• 65536-word × 16-bit configuration

• Single 5 V ±10% power supply

• All input and output (I/O) TTL compatible

• Supports fast page mode, read-modify-write, and bytewrite.

• Supports output caching control using early write and Output Enable (OE) control.

• 4 ms refresh using 256 refresh cycles

• Supports RAS-only refresh, CAS-before-RAS refresh and hidden refresh.

• Packages SOJ 40-pin (400 mil) plastic package: LC321664AJ SOP 40-pin (525 mil) plastic package: LC321664AM TSOP 44-pin (400 mil) plastic package: LC321664AT

• RAS access time/column address access time/CAS access time/ cycle time/power dissipation

Package Dimensions

unit: mm

3200-SOJ40

unit : mm

3195-SOP40

SANYO:SOJ40

[LC321664AJ]

SANYO:SOP40

[LC321664AM]

LC321664AJ, AM, AT-80

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN

1 MEG (65536 words × 16 bits) DRAM

Fast Page Mode, Byte Write

CMOS LSI

Parameter LC321664AJ, AM, AT-80 RAS access time 80 ns Column address access time 45 ns CAS access time 30 ns Cycle time 135 ns

Power dissipation

During operation 633 mW

(max.)

During standby 5.5 mW (CMOS level)/11 mW (TTL level)

LC321664AJ, AM, AT-80

No. 4795-2/30

Package Dimensions

unit : mm

Pin Assignments

3207-TSOP44

[LC321664AT]

SANYO:TSOP44 (TYPE-II)

LC321664AJ, AM, AT-80

No. 4795-3/30

Block Diagram

Specifications

Absolute Maximum Ratings

Parameter Symbol Ratings Unit Note

Maximum supply voltage V

max –1.0 to +7.0 V 1

Input voltage V

–1.0 to +7.0 V 1

Output voltage V

OUT

–1.0 to +7.0 V 1

Allowable power dissipation

LC321664AJ, AM

Pd max

800

mW 1

LC321664AT

700

Output short-circuit current I

OUT

50 mA 1 Operating temperature range Topr 0 to +70 °C 1 Storage temperature range Tstg –55 to +150 °C 1

Note: 1) Stresses greater than the above listed maximum values may result in damage to the device.

DC Recommended Operating Ranges at Ta = 0 to +70°C

Parameter Symbol min typ max Unit Note

Power supply voltage V

4.5 5.0 5.5 V 2

Input high level voltage V

2.4 6.5 V 2

Input low level voltage (A0 to A7,

–1.0* +0.8 V 2

RAS, CAS, UW, LW, OE) Input low level voltage

–0.5* +0.8 V 2

(I/O1 to I/O16)

Note: 2) All voltages are referenced to V

A bypass capacitor of about 0.1 µF should be connected between V

and VSSof the device.

* –2.0 V when pulse width is less than 20 ns

LC321664AJ, AM, AT-80

No. 4795-4/30

DC Electrical Characteristics at Ta = 0 to + 70°C, VCC= 5 V ± 10%

Parameter Symbol Conditions min max Unit Note

Operating current

CC1

RAS, CAS, address cycling:

115 mA

3, 4,

(Average current during operation) t

= tRCmin 5

Standby current I

CC2

RAS = CAS = V

2 mA

RAS-only refresh current I

CC3

RAS cycling, CAS = VIH:

115 mA 3, 5

= tRCmin

Fast page mode current I

CC4

RAS = VIL, CAS address cycling:

70 mA

3, 4,

= tPCmin 5

Standby current I

CC5

RAS = CAS = VCC–0.2V 1 mA

CAS-before-RAS refresh current I

CC6

RAS, CAS cycling:

115 mA 3

= tRCmin

Input leakage current I

0V ≤ V

≤ 6.5V, pins other than

–10 +10 µA

measuring pin = 0V

Output leakage current I

OUT

disable,

–10 +10 µA

≤ V

OUT

≤ 5.5V

Output high level voltage V

OUT

= –2.5mA 2.4 V

Output low level voltage V

OUT

= 2.1mA 0.4 V

Note: 3) All current values are measured at minimum cycle rate. Since current flows immoderately, if cycle time is

longer than shown here value becomes smaller.

Note: 4) I

CC1

and I

CC4

are dependent on output loads. Maximum values for I

CC1

and I

CC4

represent values with output

open.

Note: 5) One address change can be performed while RAS = V

IL(ICC1

and I

CC3

One address change can be performed during one t

cycle (I

CC4

LC321664AJ, AM, AT-80

No. 4795-5/30

AC Electrical Characteristics at Ta = 0 to +70°C, VCC= 5 V ± 10% (Note 6, 7, 8)

Parameter Symbol min max Unit Note

Random read or

135 ns

write cycle time Read-write/read-modify-write

RWC

180 ns

cycle time Fast page mode cycle time t

55 ns

Fast page mode Read-write/read-modify-

PRWC

100 ns

write cycle time RAS access time

RAC

80 ns

9, 14

CAS access time t

CAC

30 ns 9, 14

Column address access time t

45 ns 9, 15

CAS precharge access time t

CPA

50 ns 9

Output low-impedance

CLZ

0 ns 9

time from CAS low Output buffer turn-off delay time

OFF

0 20 ns 10

Rise or fall time t

3 50 ns

RAS precharge time t

45 ns

RAS pulse width t

RAS

80 10000 ns

RAS pulse width for

RASP

80 100000 ns

fast page mode only RAS hold time t

RSH

30 ns

CAS hold time t

CSH

80 ns

CAS pulse width t

CAS

30 10000 ns

RAS to CAS delay time t

RCD

25 50 ns 14

RAS to column address delay time

RAD

17 35 ns 15

CAS to RAS precharge time t

CRP

10 ns

CAS precharge time t

10 ns

Row address setup time t

ASR

0 ns

Row address hold time t

RAH

12 ns

Column address setup time t

ASC

0 ns

Column address hold time t

CAH

20 ns

Column address hold time

60 ns

referenced to RAS Column address to RAS lead time

RAL

45 ns

Read command setup time t

RCS

0 ns

Read command hold time

RCH

0 ns 11

referenced to CAS Read command hold time

RRH

0 ns 11

referenced to RAS Write command hold time t

WCH

15 ns

Write command hold time

WCR

60 ns

referenced to RAS Write command pulse width t

15 ns

Continued on next page.

LC321664AJ, AM, AT-80

No. 4795-6/30

Continued from preceding page.

Parameter Symbol min max Unit Note

Write command to RAS lead time

RWL

20 ns

Write command to CAS lead time

CWL

20 ns

Data input setup time t

0 ns 12

Data input hold time t

20 ns 12

Data input hold time

DHR

60 ns

referenced to RAS Refresh period t

REF

4 ms

Write command setup time t

WCS

0 ns 13

CAS to UW, LW delay time t

CWD

50 ns 13

RAS to UW, LW delay time t

RWD

100 ns 13

Column address to UW, LW

AWD

65 ns 13

delay time

CAS precharge to UW, LW

delay

CPWD

70 ns 13

time (fast page mode cycle only)

CAS setup time for

CSR

10 ns

CAS-before-RAS refresh CAS hold time for

CHR

15 ns

CAS-before-RAS refresh RAS precharge time to

RPC

10 ns

CAS active time CAS precharge time for

CPT

40 ns

CAS-before-RAS counter test RAS hold time referenced to OE

ROH

15 ns

OE access time t

OEA

25 ns 9

OE delay time t

OED

15 ns

OE to output buffer turn-off

OEZ

0 15 ns 10

delay time OE command hold time t

OEH

20 ns

Data input to CAS delay time t

DZC

0 ns 16

Data input to OE delay time t

DZO

0 ns 16

Masked write setup time t

MCS

0 ns

Masked write hold time

MRH

0 ns

referenced to RAS Masked write hold time

MCH

0 ns

referenced to CAS

Input/Output Capacitance at Ta = 25°C, f = 1 MHz, VCC= 5 V ± 10%

Parameter Symbol min max Unit

Input capacitance

7 pF

to A7, RAS, CAS, UW, LW, OE)

I/O capacitance (I/O

to I/O16) C

I/O

7 pF

LC321664AJ, AM, AT-80

No. 4795-7/30

Notes: 6) After the power is turned on, 200 µs are required after the arrival of VCCstabilized current before

memory is initialized and begins operation. In addition, before memory operation initializes, approximately 8 cycles worth of RAS dummy cycles are required. When the on-chip refresh counter is applied, approximately 8-cycles worth of CAS-before-RAS dummy cycles are required instead of the RAS dummy cycles.

7) Measured at tT= 5 ns.

8) When measuring input signal timing, VIH(min) and VIL(max) are used for reference points. In addition, rise and fall time are defined between VIHand VIL.

9) Measured using an equivalent of 50 pF and one standard TTL load.

10) t

OFF

(max) and t

OEZ

(max) are defined as the time until output voltage can no longer be measured when

output switches to a high impedance condition.

11) Operation is guaranteed if either t

RRH

or t

RCH

are satisfied.

12) These parameters are measured from the falling edge of CAS for an early-write cycle, and from the falling edge of UW and LW for a read-write/read-modify-write cycle.

13) t

WCS

, t

CWD

, t

RWD

, t

AWD

and t

CPWD

are not restrictive operating parameters for memory in that they

specify the operating mode. If t

WCS

≥ t

WCS

(min), the cycle switches to an early-write cycle and output

pins switch to high impedance throughout the cycle. If t

CWD

≥ t

CWD

(min), t

RWD

≥ t

RWD

(min), t

AWD

≥

AWD

(min) and t

CPWD

≥ t

CPWD

(min), the cycle switches to a read-write/read-modify-write cycle and data outputs equal information in the selected cells. If neither of the above conditions are satisfied, output pins are in an undefined state.

14) t

RCD

(max) does not indicate a restrictive operating parameter but instead represents the point at which

the access time t

RAC

(max) is guaranteed. If t

RCD

≥ t

RCD

(max), access time is determined according to

CAC

15) t

RAD

(max) does not indicate a restrictive operating parameter but instead represents the point at which

the access time t

RAC

(max) is guaranteed. If t

RAD

≥ t

RAD

(max), access time is determined according to

tAA.

16) Operation is guaranteed if either t

DZC

or t

DZO

are satisfied.

LC321664AJ, AM, AT-80

No. 4795-8/30

Timing Chart

Read Cycle

LC321664AJ, AM, AT-80

No. 4795-9/30

Early Write Cycle

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