Samsung SF 4700 Circuit Description

Samsung Electronics

5-1

5. List Abbreviations

Acrynym Definition

MFP MULTI FUNCTION Peripheral
I/F INTERFACE
UART Universal Asynchronous Receiver/Transmitter
ECP Extended Capabilities Port
CR CARRIAGE RETURN
LF LINE FEED
SCANIP SCAN IMAGE PROCESSOR
CIS CONTACT IMAGE SENSOR
A/D ANALOG TO DIGITAL
D/A DIGIT ALTO ANALOG
LIU Line Interface Unit
TIT Transformer Input from Transformer
ROT Receive Output Transformer
LI Line Input

Samsung Electronics

6-1

6. Circuit

6-1 SF-4750C Main PBA

6-1-1 Summary

The main circuit that consists of CPU, MFP
controller (built-in 32bit RISC processor core:
ARM7TDMI) including various I/O device
drivers, system memory, scanner,printer,

motor driver, PC I/F, and FAX transceiver controls
the whole system. The entire structure of the main
circuit is as follows:

Fig.6-1-1. Entire Structure of Main Circuit for Each Key Signal

OPE-TXD

MA0~MA14

/WE

/OE
MD0~MD7

TMIA1

TMIA0
TMIB0

TMIB1

OK2PRINT
/P_EXIT
/RING_DET

/HOOK_OFF

CIS_CLK
CIS_SH

/SPK_CTL

PREHEAT

_M

PREHEAT

_C

CIS-SIG

VREFADC
VREFDAC

VOL0
VOL1
VOL2

CML_ON

/DRAM_EN

ICML1

GLED
RLED
BLED

OPE-RXD

MCLK(38MHz)
/POR

/ROMCS

/RD, /WR

D0~D15

D0~D15

D0~D7

A0~A17

A0~A9

A0~A4

/MODEM-RST

/USB-RST

/USB-CS

/USB-XDDCK

/USB-XDREQ

/USB-INT

/MCS

/MIRQ

/RD, /WR

/RASO

/WR

/UCAS,

/LCAS

/F-POR

MORK(38MHz)

/XDACK
/XDREQ

/IP-CS

/RD, /WR

D0~D15

A0~A5

/TX-INT

LFPHA

MFP

CONTROLLER

(KS32C6400)

LFPHB

LFIA0
LFIA1
LFIB0
LFIB1

DIR

PWM

CHX
CHY

/HEAD-EN

/HGA1~/HGA13

HOE1~HOE16

/FAULT-TEST

BIASOFF

/RST-OUT

/RST-OUT

FLASH

MEMORY

(4M bit)

DRAM

(16M bit)

MODEM

SCAN

IMAGE

PROCESSOR

LF MOTOR

DRIVER

SRAM

CIS

CR MOTOR

DRIVER

CR

EN CORDER

PRINT HEAD

DRIVER &

PRINT

CONTROL/

CIRCUIT

OPE

TX MOTOR

DRIVER

/OPE-RST

C_HEAD DATA

Backup

Power

USB

Controller

VBUS
USBDP
USBDM

PULLUP

VB

48MHz CLK

Samsung Electronics

6-2

6-1-2 MFP Controller (KS32C6400 : U26

MFP Controller consists of CPU(ARM7TDMI RISC
processor), 4K-byte cache, data and address buses,
serial communication part with OPE(OPERATION
PANEL) print head controller, USB interface, external
DMA part to receive data from external color image
processor (SCANIP), LF/CR motor diver
controller and I/O controller.

6-1-2-1. SYSTEM CLOCK

The internal clock frequency is 38MHz. 38MHz
system clock (MCLK) supplied from the outside is
used without being divided inside.

6-1-2-2. DATA& ADDRESS BUS CONTROL

• /RD & /WR
/RD & /WR signals are synchronized with
MCLK(38MHz) and become LOW ACTIVE.
These signals are strobe signals used to read and
write data when each CHIP SELECT is connected

with /RD and /WR pin of RAM, ROM, USB,
MODEM and the outside devices and becomes
active.

• CHIP SELECT (/IP_CS, /ROMCS, /USB_CS,
/MCS)

- /IP-CS : SCANIP(U29) CHIP SELECT (LOW

ACTIVE)

- /ROMCS : ROM/FLASH MEMORY(U31) CHIP

SELECT (LOW ACTIVE)

- /USB_CS : USB (U43) CHIP SELECT (LOW

ACTIVE)

- /MCS : MODEM(U37) CHIP SELECT (LOW

ACTIVE)
When each CHIP SELECT is low, data can be read or
written.

• D0 - D15

- 16bit data bus

• A0 - A17

- ADDRESS BUS (A18 - A21 are reserved.)

Circuit

Samsung Electronics

6-3

6-1-2-3. OPE Serial Communication Part

UART (Universal Asynchronous
Receiver/Transmitter) at KS32C6400 enables the main
and OPE to transmit serial

data. The block diagram of UART is as follows: (Fig.6­1-2) KS32C6400 has 2 UART channels. The baud rate
is 9600bps.

Circuit

TxD

TxD

RxD

IRS

RE

IR Tx

Encoder

IR Rx

Decoder

0

0

1

1

RxD

UART

Block

Fig.6-1-2. UART BLOCK DIAGRAM

TXD :

START D0 D1 D2 D3 D4 D5 D6 D7 STOP

RXD :

START D0 D1 D2 D3 D4 D5 D6 D7 STOP

Fig.6-1-3 UART DATA FORMAT

Samsung Electronics

6-4

6-1-2-4. EXTERNAL DMA BLOCK

It brings data from external devices (SCANIP:U29 ,
USB:U43) using DMA channel 0,1. DMA REQUEST
sent from an external device to KS32C6400 activates
DMAACKNOWLEDGE signal and drives DMA
channel 0 to produce CHIP SELECT and READ
STROBE (/RD) at the external

device and bring data from it. It generates address of
destination memory, CHIP SELECT and WRITE
STROBE (/WR) in order to move this data into
destination memory, and then stores the data.

Circuit

MCLK

/XDREQ

/XDACK

D[15:0]

/RD

/WR

Fig.6-1-4 EXTERNAL DMA TIMING DIAGRAM

Samsung Electronics

6-5

6-1-2-5. DRAM CONTROLLER

As KS32C6400 has DRAM controller in it, DRAM can
be connected with external memory.
The control mode of DRAM controller enabling
EARLY WRITE, NORMAL READ, PAGE MODE, and
BYTE/HALF WORD ACCESS supports EDO DRAM
as well as normal DRAM. DRAM READ/WRITE sig­nals are /RD and /WR signals used to control system

buses. It supports CAS BEFORE RAS for DRAM
REFRESH and self-refresh mode for DRAM backup.
Connected with common /LCAS, /UCAS and RAS
[1:0], it consists of 2 banks. Though each may be con­nected with up to 1M - 4M halfword, two (2) of 512
Kbytes are
connected for this product.

Circuit

Samsung Electronics

6-6

6-1-2-6. INKJET HEAD CONTROLLER

This part produces major control signals used to drive
INKJET head. It consists of signals to drive head noz­zles, /HGA[13:1], HOE[16:1], /FAULT-TEST, /HEAD­EN, and BIASOFF, and consists of signals to check the
status of the head, HEAD-DATA.

It has double height print head, system 208 nozzles
for mono and 192 nozzles for color, and uses
/HGA[13:1], HOE[16:1] signals and /HEAD-EN to
drive these nozzles. Fig.5-1-8 is timing diagram of
each signal.

/HGA

Signal

HOE

Signal

Fire Enable Timer

Pre-Heat Pulse Width

Front End Delay Back End DelayPr-Heat Delay Width

Fire Pulse Width

t

p (PD)

Fig.6-1-5 Timing Diagram to Drive Head

Circuit

Samsung Electronics

6-7

Circuit

The above control signals are sent to head driver and
the head driver converts these signals to the level
(+11.75V) to drive head nozzles.

6-1-2-7. PRINTER MOTOR CONTROLLER (CRPHA,

CRPHB, CRIA0, 1, CRIB0, 1, LFPHA, LFPHB,
LFIA0, 1, LFIB0, 1)

MFP Controller (KS32C6400:U26) supports both DC
motor and stepper motor. It controls CR (Carriage
Return) motor used to print documents and LF (Line
Feed) motor used to feed and eject paper.
CR motor controller can support 75, 150, 200, 300,
600, or 1200dpi according to resolution, while LF

motor controller supports uni-polar and bi-polar
according to the kind of motors. Though full step, half
step and software control are possible for both, CR
motor is controlled DC control block and LF motor is
controlled half step and quarter step here.

/HEAD-EN

/HGA1
/HGA2

/HGA3
/HGA4

/HGA5
/HGA6

/HGA7
/HGA8
/HGA9

/HGA10
/HGA11

/HGA12
/HGA13

(Tp)

HOE1-

HOE16

Fig.6-1-6. Timing Diagram for Each Nozzle

Samsung Electronics

6-8

6-1-2-8. I/O PORT FOR KS32C6400

PIN NAME

PIN NO

I/O PORT NAME

DESCRIPTION FOR STATE

GOP0/TXD1
GOP1/TXD2
GOP2/nEDACK
GOP3/TONE
GOP4/nRST0
GOP5/nIOWR1
GOP6/nIOWR2
GOP7/nIORD1
GOP8/DRV–SDO
GOP9/CLKOUT
GOP10/FIRE­PULSE
GOP1 1/nHSC
GOP12/nEDACK
2
GOP13/nECS3
GIP0/nRXD1
GIP1/nRXD2
GIP2/nEINT1
GIP3/nEINT2
GIP4/nEDREQ
GIP5/UCLK
GIP6/nEWT3
GIOP0/TCK
GIOP1/TMS
GIOP2/TDI
GIOP3/nTRST
GIOP4/TDO
GIOP5
GIOP6
GIOP7/nWAIT

121
123
138
148
149
133
154
155
152
151
150
153
128

42
122
124
135
136
137
127

41
126
125
120
116
115
103

38

31
145
146

DP

OPE_TXD

/XDACK

KEYCLICK

WATCHDOG

/FAULT_TEST

/OPE_RST

BIASOFF

/RST_OUT

CLK_OUT

TONE_CTL
/C_HEAD_EN
/USB_XDACK

RESERVED
RESERVED

OPE_RXD

/MIRQ

TX_INT

/XDREQ

/USB_XDREQ

/USB_INT

TCK
TMS

TDI

/TRST

TDO

/MODEM_RST

RECALL

/M_HEAD_EN

/USB_RST

RX_CTL

DIAL PULSE ON

DIAL PULSE OFF:IDLE STAT

SERIAL DATA FROM KS32C6400 TO OPE MICOM

–

DMAACKNOWLEDGE TO SCAN IP

KEYCLICK TONE

WATCHDOG RESET OFF WATCHDOG RESET

– TEST PRINT HEAD FAULT

OPE RESET OFF OPE RESET

PRINT HEAD BIAS OFF PRINT HEAD BIAS ON

RESET OFF RESET ON

OUTPUT WITH 38.00053MHz

LINE MONITORING KEYCLICK

DISABLE COLOR PRINT HEAD ENABLE COLOR PRINT HEAD

IDLE

DMAACKNOWLEDGE TO USB IC
NC NC
NC NC

SERIAL DATA FROM OPE MICOM TO KS32C6400

MODEM INTERRUPT INACTIVE MODEM INTERRUPT ACTIVE

IDLE TX MOTOR INTERUPT
IDLE

DMA REQUEST FROM SCAN IP

IDLE DMAREQUEST FROM USB IC

IDLE INTERUPT SIGNAL FROM USB IC
RESERVED TEST PIN for ICE(JTAG)
RESERVED TEST PIN for ICE(JTAG)
RESERVED TEST PIN for ICE(JTAG)
RESERVED TEST PIN for ICE(JTAG)
RESERVED TEST PIN for ICE(JTAG)

RESET OFF RESET ON
RECALL ON RECALL OFF:IDLE STATE

DISABLE MONO PRINT HEAD ENABLE MONO PRINT HEAD

RESET OFF:IDLE STATE RESET ON

RX LINE TX LINE OR REMOTE

O
O
O
O
O
O
O
O
O
O
O
O
O
O

I
I
I
I
I
I
I
I
I
I

I
O
O
O
O
O
O

H L

Circuit

Samsung Electronics

6-9

Circuit

6-1-2-9. RESET CIRCUIT

As for this product, there are 2 power resets of prima­ry reset(/F-POR) and secondary reset(/POR) and also
reset by watchdog timer (/RSTO). Primary reset is
used to initialize flash memory when the system is
turned on, while secondary reset is used to initialize
the whole system by initializing MFP controller
(KS32C6400) after primary

reset. Primary reset makes flash memory wait in
READ mode to fetch program
codes, and secondary reset makes the main
controller (KS32C6400) wake up and initialize
external peripherals to operate the system.
Fig.5-1-10 is Power Reset Timing Diagram.

• POWER MONITOR (U220: XC61FN4512)
If +5V supplied to XC61FN4512 is so unstable as to
reach +4.65V - +4.35V (typically 4.5V), it will
recognize it as power failure. Then XC61FN4512
output terminal becomes low (0V) and the voltage is
impressed to flash memory and KS32C6400, run­ning RESET (LOW ACTIVE). Flash memory and

KS32C6400 are reset first. Thereafter modem,USB,
print control parts and SCANIP(Color Image
Processor) linked to /RSTOUT terminal of
KS32C6400 are reset as well. XC61FN4512 output
terminal of open drain structure is pulled up 1MΩ
and put out.

supply

Voltage

/F-POR

/POR

PnRST

Internal Reset

256 MCLK

Reset filter

65 MCLK

ROM Access

(internal)

Reset

Fig.6-1-7 POWER RESET TIMING DIAGRAM