Samsung SF 330/09 Schematic

Repair Manual

1. Block Diagram

2. Connection Diagram

3. Circuit Description

4. Schematic Diagrams

SAMSUNG FACSIMILE

SF-330/331P/335T

C•O•N•T•E•N•T•S

- This Service Manual is a property of Sam sung Electronics Co.,Lt d.
Any unautho rized use of Ma nual can be punis hed under app licable

International and/or dome stic law. -

Samsung Electronics Digital Printing
CS Group

Copyright (c) 2002. 07

This manual is made and

described centering around

circuit diagram

and circuit description needed

in the repair center

in the form of appendix.

1

1-1

Samsung Electronics

BLOCK DIAGRAM

Repair Manual

1. Block diagram

2Pin

5pin

4pin

7pin

7pin

5pin

SCAN MOTOR

(STEP)

5pin

2pin

CR

MOTOR

(DC)

LF

MOTOR

(STEP)

60 pin

30Pin

2pin

SS

MOTOR

(STEP)

CIS (200dpi)

LCD (16*1)

MICOM

DDET DSCA N

SMPS

(+24V,-5V)

SIXSHOOT

OR

DI SCRETE

TRANS

600:600

RELAY

CHORUS2

(Including IP)

MODEM

FM214 : SF-330/331P
FM214-VS : SF-335T

(14.4k)

FLASH

MEMOR Y

(8Mbit)

ERTE

SDRAM

16Mbit : SF-330/331P
64Mbit : SF-335T

QUARTER-

HO RSE

(C

DC-DC CONVERT

R/LF/SS

MOTOR DRV.)

Scec on

SPEECH

MAIN

OPE

LIU

SPEAKER

Encorder

Sensor

CR

HOOK S/W

(Ph oto

(SF-330/331P ONLY)˚

Interr upt or )

EXT LINE

TEL LINE

HANDSET

AFE

Mic

(SF-335T ONLY)

USB

SF-331P ONLY

SCAN

MOTOR DRV.

TRANS

600:600

MAIN P CB : 2 75 x 67 .5 m m

OPE PCB: 247 x 95.5mm

LIU PCB: 100 x 98.5mm

STUBBY

INK

INK-M40
INK-C

(SF-331P ONLY)

40

(3Pin Connector)

(8Pin Connector)

(6Pin Connector)

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2

2-1

Samsung Electronics

CONNECTION DIAGRAM

Repair Manual

2. Connection Diagram

R37

R11

C1 COU

R13

R9

R39

R14

R40

ID2

R38

R48

R12

CIS

(200 DPI)

23456781

2341

A

B

C

D

E

ED DATE 01 2002.07.12

SIGN

D

W

G

E
N
G

C
H
K

A
P
P

REF NO SEC

1/1

RHINE(SF-330/331P/335T)

CONNECTION DIAGRAM

F

E

A

B

C

D

S
a

m
s

u

n
g

E
l

e

c

t

r

o
n

i

c

s
C

o
L

t

d

A
l

l
R

i

g

h

t

s
r

e

s

e

r

v

e

d

¡£¡¢

¡£

TX MOTOR

1

PICK_UP
SENSOR

CR

8

ENCODER

SENSOR

CN
2

MAIN

USB

11

1
2
3
4
5

1
2
3
4
5
6

LF MOTOR

LF _A
LF_nA
LF_nB

LF _B

1
2
3
4
5

1
2
3
4
5

+19.2V

CR MOTOR

6

CR_MOT_P

CR_MOT_M

1
2

1
2
3

SS MOTOR

SMPS

3

1
2
3
4

-5V

DGND

+24V

1
2
3
4

1
2
3
4
5

SS_A
+19.2V
SS_nA
SS_nB

SS_B

1
2
3
4
5

R1
R7
R3
R5

R15
R21
R17
R19
R23
R25
R27

R31

R33
R29

R35
R41
R43
R45
R47

TSR1

+19.2V (R49)

C3 COL
C4 CEL

ID1 (R50)

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

9

LIU

HANDSET

1
2
3
4

1
2
3
4

MIC­RCV2

RCV1
MIC+

M
J

3

1
0

1

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

CIS_SI

DGND

OPE_R XD

nOPE_RST

+24V

OPE_TXD

+5V

nHOOK_DET1

CIS_LED

CIS_CLK

+5V

nDP

MJ1 MJ2

OPE

LCD

(16X1)

1
2
3
4
5
6
7
8

9
10
11
12
13
14

1

1
2
3
4
5
6
7
8

9
10
11
12
13
14

DGND

+5V

VD

LCD_RW
LCD_CS

D0
D1

D2
D3
D4
D5
D6
D7

LCD_RS

D_DET

D_SCAN

OPE_TXD

nOPE_RST

OPE_RXD

+5V

1
2
3
4
5
6
7

3

2

DGND

1
2
3
4
5
6
7

AGND

MIC_IN

1
2
3
4
5

6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

HS_VOL_CTL

AGC

HS_TX_CTL

AGND

MODEM_RX

AGND

MODEM _TX

DGND

-5V

MIC_IN

CIS_SIG

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

R46
R44
R42
R36

R32
R30
R34
R28
R26
R24
R20

R16

R18
R22

R6
R4
R8
R2

R10

C2 CE U

DGND
CH_X

+5V

CH_Y

1

2

3

4

5

6

7

8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CIS_SIG

DGND

+5V

CIS_SI

CIS_CLK
CIS_LED

+24V(VLED)

1
2
3
4
5
6
7
8

3

1
2
3
4
5
6
7

VBUS

USB_DM

USB_DP

DGND

1
2
3
4

TX_A
nTX_A
nTX_B

TX_B

+24V

N.C

N.C

5

DGND

nCML2

HS_RX_CTL

nCML1

+3.3V

REMOTE

nRING_DET

nHOOK_DET2

1
2

MIC_SIG

AGND

2

Only SF-335T

N.C

HOOK

DET

SPEAKER

1
2

1
2

SPK_ O UT

DGND

7

TEL LINE EXT LINE

FPC PIN NAME

SS SWITCH

1
3
2

1
2

nSS_SW

DGND

4

N.C

(42)(44)(4 6)(T2) (C4)(C3) ( T1)(45)(4 3)(41)

(40)(38)(3 6) (50)(49) (3 5)(37)(39)

(30)(32)(3 4) (I D2)(ID1 ) (33)(3 1)(29)

(28)(26)(2 4) (48)(47) (2 3)(25)(27)

(18)(20)(2 2) (21)(19)(1 7)

(16)(14)(1 2) (11)(13)(1 5)

(4)(6) (5)(3)

(2)(8) (7)(1)

(C2)(10) (9)(C1)

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

CN

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3

CIRCUIT DESCRIPTION

3.1 Main B’D

3.1.1 GENERAL DESCRIPTION

Main circuit consists of mainly consists of CPU and the controller part with various types of built-in I/O device driver(built-in RISC
Processor Core : ARM7TDMI), system memory part, Image control part (CHORUS-2) controlling input of image received from
media and conversion. The following nomenclatures by section is the same as those listed in the circuit diagram.

3.1.2 MEMORY MAP

The entire Addressing area provided by MAIN CONTROLLER(S3C46Q0X) is 256MBytes from 0x00000000 to 0x10000000,
and the Max. Address Range for each External Chip Select is 32M Byte or Half word from 0x000000 to 0x01FFFFFF and
embodied with Big-Endian Bus interface. MEMORYarea is divided into EXTERNAL ROM and RAM areas(See (Figure 1)), and
the areas actually used are 2M/8M BYTES SDRAM and 1M BYTES ROM(FLASH MEMORY). In case of SDRAM0, it uses
0x0000000h ~ 0x01BFFFFFFh area.

3. Circuit Description

<Figure 1. S3C46Q0X MEMORY MAP>

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CIRCUIT DESCRIPTION

<1> General description

MAIN CONTROLLER(S3C46Q0X,U12) consists of this
system consists of CPU(ARM7TDMI RISC PROCES­SOR), 8K BYTES CACHE, DATA and ADDRESS BUS,
PLL deriding input frequency and CLOCK CONTROLpart,
SERIAL COMMUNICATION part supporting UART, PRINT
HEAD control part, PARALLEL PORT INTERFACE part,
USB INTERFACE part, Internal Image Processor Part,
External DMA part MEMORY and EXTERNAL BANK con­trol part, SYNCHRONOUS SERIAL INTERFACE control
part for interfacing Quarter_Horse, and TX Motor drive con­trol and general purpose I/O control parts.(See Figure 2 )

3.1.3.2 S3C46Q0X FUNCTION DESCRIPTION

<1> SYSTEM CLOCK

There are two ways of Clock input method. One is the
method to make Master Clock(MCLK) at the internal PLL
by connecting X-tal and Capacitor to the outside, and
another method is to use MCLK(When inputting 40MHz)
directly, which supplies maximum 40MHz Clock to the
EXTCLK terminal(PIN65). The range of frequency being
input in case of using X-tal is limited to 4MHz~10MHz.
For making the MCLK, the Clock is supplied to the
EXTCLK Terminal of the ASIC by sending output power
(32.256MHz) of the MODEM (FM214 or FM214-VS, U16)
XCLK via the RC Filter. The inner side of the ASIC takes
the Clock, and it goes to the MPLL circuit to create a basic
operating frequency (66MHz MCLK signal). Also the Clock
goes to the UPLL circuit to make the operating frequency
of the USB Controller (48MHz).

<2> DATA and ADDRESS BUS CONTROL

1. _RD & _WR

_RD & _WR SIGNAL are synchronized with the inside
MCLK(66MHZ) and becomes active to Low.

These signal are Strobe Signal used to Read or Write
data when each Chip Select becomes active connected
to SDRAM, ROM(Flash), _WR PIN, _RD of Modem.

2. CHIP SELECT
(_ROMCS, _IP_CS,_MED_CS,_SCS0,_SCS1)

• _ROMCS : FLASH MEMORY(U7) CHIPSELECT
(LOW ACTIVE)

• _MODEM_CS : MODEM(U16) CHIP SELECT

(LOW ACTIVE)

• _SCSO : SDRAM (BASIC 16MBIT(U9), TAD 64MBIT(U8),

CHIP SELECT (LOW ACTIVE)

In case each Chip Select is low, it may Read or Write data.

3. D0 ~ D15

• 16BIT DATA BUS

4. A0 ~ A24

• ADDRESS BUS (A23 ~ A24 RESERVED)

3.1.3.1 BLOCK DIAGRAM and MAIN CONTROLLER description

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CIRCUIT DESCRIPTION

<Figure 2. Main Part Interface Signals>

_SS_SW

CR
MOTOR

(U5)

(U4)

(U7)

(SF-330 : U9)
(SF-331P : U9)
(SF-335T : U8)

(0:15)

(0:15)

(0:11)SF-330 :

SF331P:
SF-335T :

(0:11)
(0:12)

TX_A

CIS_LED
CIS_CLK

CIS_CIG
CIS_SI

_RD

_WR

-MODEM_RST

-MODEM_MCS

-MODEM_MIRQ

OPE_TXD
OPE_RXD
OPE_RST

TX_nA
TX_B

TX_nB

(U2)

(U12)

(U16)

3.3V
(U10)

(SF-331P ONLY)

1.8V
(U13 )

-

_scs0

-

-

-

-

-

-

-

LF
MOTORSSMOTOR

TX
MOTOR

SIX
SHOOTER

CR_MOT_P

CR_MOT_M

SS A

SS nA

SS B

SS nB

LF_B

LF_nB

LF_A

LF_nA

MIC

(SF-335T ONLY)

To Analog Part

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CIRCUIT DESCRIPTION

<Figure 3. Flash Memory Read Timing>

<Figure 4. Flash Memory Write Timing>

EXTCLK

nGCSx

nGCSx

ADDR

tRWD

tRAD

Tacs

tRCD

nWE

DATA

nBEx

Tacc

Toch

Tcah

Tocs

tRCD

tRWD

tRDD

tRAD

tRDH

’1’

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EXTCLK

ADDR

nGCSx

nWE

nGCSx

nBEx

DATA

tRAD

tRCD

Tacs

tRWD

Tocs

tRWBED

Tcos

tRDD

Tacc

tRWD

Toch

tRWBED

Toch

tRAD

tRCD

Tcah

tRDD

CIRCUIT DESCRIPTION

<Figure 5. SDRAM Read Timing>

SCLK

SCKE

ADDR/BA

AP/A10

nGCSx

nSRAS

nSCAS

nBEx

nWE

DATA

’1’

tSAD

tSAD

tSCSD

tSRD

Trp Trcd

tSCD

tSBED

Tcl

tSWD

tSDS

tSDH

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CIRCUIT DESCRIPTION

<Figure 6. SDRAM Write Timing>

SCLK

’1’

SCKE

ADDR/BA

AP/A10

nGCSx

nSRAS

nSCAS

nBEx

nWE

DATA

tSAD

tSAD

tSCSD

tSRD

Trp

Trcd

tSWD

tSDD

tSDD

tSBED

tSCD

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CIRCUIT DESCRIPTION

<Figure 7. SDRAM Write Timing>

SCLK

SCKE

ADDR/BA

AP/A10

nGCSx

nSRAS

nSCAS

nBEx

nWE

DATA

tSAD

’1’

’1’

’HZ’

tSAD

tSCSD

tSRD tSRD

tSCD

tSWD

tSCSD

tSAD

Trp Trc

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CIRCUIT DESCRIPTION

<Figure 8. SDRAM auto Refresh Timing>

SCLK

SCKE

ADDR/BA

AP/A10

nGCSx

nSRAS

nSCAS

nBEx

nWE

DATA

tSAD

’1’

’1’

’HZ’

tSAD

tSCSD

tSRD tSRD

tSCD

tSWD

tSCSD

tSAD

Trp Trc

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CIRCUIT DESCRIPTION

<Figure 9. SDRAM Self Refresh Timing>

SCLK

SCKE

ADDR/BA

AP/A10

nGCSx

nSRAS

nSCAS

nBEx

nWE

DATA

’HZ’

tSWD

’HZ’

’1’

’1’

’1’

’1’

’1’

’1’

’1’

tCKED

tSAD

tSAD

tSCSD

tSRD tSRD

tSCD

tSCSD

tSAD

tCKED

Trc

Trp

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CIRCUIT DESCRIPTION

<3> EXTERNAL DMA part

This system does not use External DMA part.

<4> DRAM control part

Since S3C46Q0X has the DRAM CONTROLLER build-in,
it may be used by connecting DRAM with external memo­ry. The Control mode of DRAM CONTROLLER provided
by S3C46Q0X is available for EARLY WRITE, NORMAL
READ, P AGE MODE, and BYTE_HALF WORD ACCESS,
and is supported even by EDO DRAM,and SDRAM as well
as, Fast page DRAM. This system uses SDRAM, and the
signal used for READ_WRITE uses _RD,_WR signal used
for SYSTEM BUS CONTROL. It is supported with auto
REFRESH and also by the Self-refresh mode for DRAM
BACK UP. It consists of 2 Banks connected to common
_SCSO, _SCAS, _SRAS, _SCLK, _SCKE, _DQM[1:0],
each of them may use up to 2M ~ 32M HALF WORD.

In this system, Basic 2MB (T AD 8MB) is applied as system
memory. The area of DRAM is specified in the DRAM
MEMORY MAP of Fig. 1, while the related TIMING DIA­GRAM in Fig. 5, 6, 7, 8, 9.

<5> RTC (REAL TIME CLOCK) part

S3C46Q0X real time clock (RTC) operates by the super
capacitor although the system power turns off. In case of
the Basic, the backup is operated with the primary battery
(CR2032), and in case of the TAD, the backup is operated
with the secondary battery (Super-cap). The RTC has the
time data that is stored as the 8 bit BCD (binary coded dec­imal) format. The data include second, minute, hour, date,
day , month, and year. The RTC unit works with an external

32.768 kHz crystal and also can perform the alarm function
and round reset function.

<6> PARALLEL PORT INTERFACE division

This system does not use Parallel Port Interface Division.

<7> USB INTERFACE PART

1. USB function description

As the mode of implementing low cost express PC
Interface, USB was applied. At USB, PC plays the role of
route hub simultaneously by existing in the highest level as
the host. That is, the device supporting each USB is con­nected centering on PC.

The device is available for Interface for the maximum of

127. USB cable is composed of total of a set of twisted pair
and 2 power lines. The part for implementing USB function
is included in S3C46Q0X.

For Interface of USB, pull-up of 15KΩ is interfaced to the
data line of high level instruments, and, among data lines
of lower level instruments, pull-up resistance of 1.5KΩ is
interfaced to any one.

At this time, DP line is pulled up for Full Speed device, and,
for Low Speed device, DMline is pulled up. For upper level
instruments(Host, HUB) speed of device is classified inter­faced to low level by detecting any one among DP and DM.
If both lines are in the level of GND at the same time,
device is judged that low device is not interfaced. In the
transmission mode of USB, there are (1) Control transmis­sion, (2) Interrupt transmission, (3) Bulk transmission,
isochronous transmission. Control transmission is for Host
to find out configuration information from USB device. This
is conducted when device is interfaced. Interrupt transmis­sion is used when small quantity of data is sent periodical­ly. Interval value may be known from device in the case of
initial setting. Bulk transmission is valid in case of trying to
transmit data in large quantities or in case of transmitting
them accurately.

Isochronous transmission should be assured of bandwidth,
and is used when transmitting large quantities of informa­tion. Data in voice is used where delay is not allowed but
small error is allowed. At USB coding mode and bit supping
are being conducted. First, in case original data is 1, bit
shall not change, and only when original data is 001, it shall
be inverted. Only while data is 1, 1 and 0 shall be repeat­ed. Also, in case 1, original data, is continued in 6 bit, 0
shall be inserted, Also, in the 1st phase of packet, data in
the synchronized pattern shall be sent. About more
detailed information regarding USB,

see http//:www.usb.org.

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