Samsung SF150 Circuit Descriptions
SF150T 5-1
5. Circuit Description
5-1 General
The main circuit board controls the machine, and consists of Super Fax Chip (KS16118), External memory,
CODEC circuit with modem-TX and RX signal path and some parts of the Line Interface Unit, Digital TAD
circuit with DSP amd DRAM, witch controls the system.
5-2 System Control Section
This circuit consists of the EP-ROM and SRAM, external Real Time Clock crystal, RTC and memory back-up
circuitry, and the Super Fax Chip (KS16118).
The KS16118 Super Fax Chip is an integrated 9600 bps modem, image processor, 8-bit MPU, peripheral
controller, and analog front end circuit on a single-chip.
Peripheral functions inculde 2-channel SI0, 3-channel DMA, 6-bit Half flash A/D converter, scanner and
video processor units, TPH interface, CODEC unit, and tone generator.
Modem is a 9600 bps, half duplex monolithic device incorporating digital filters, a Samsung SSP1600 digital
signal processor and CPU-Interface logic.
Figure 5-1: KS16118 External Memory Map
1FFFH
0100H
00FFH
0000H
0000H
FFFFH
FF80H
FF7FH
FF00H
FEFFH
/DMS
(SRAM)
Peripheral
PCS0
DSP /CS
PCS1
Interrupt
Vectors
/PMS
(EP-ROM)
[ Program Memory ]
[ Data Memory ]
5-2-1 Memory Map
The external memory of the CPU is devided into, 1 byte(FF00H) DSP chip select, 32kbyte SRAM (0000H
through 7FFFH) and 128kbyte EP-ROM (0100H through 1FFFH).
Circuit Description
5-2 SF150T
Figure 5-2: XFC Hardware Interface Signals
5-2-2 lExternal Chip Control
KS16118 internal logic generates chip select signals for both memory chips and peripherals.
To support external access, from one to three wait cycles can be inserted under program control during
external access.
A chip select signal line goes active (low) whenever its corresponding device is accessed over the external
interface. The peripheral addresses are located in data memory space.
/DMS : SRAM chip select active (low)
/PMS : EP-ROM chip select active (low)
/PCSn : Peripheral chip select active (low)
D0 - D7 : 8 bit data bus
A0 - A15 : address bus
5-2-3 System Clock
The 12 MHz internal system clock frequency is generated by dividing the 24 MHz clock.
OPERATING
PANEL
PRINTER DATA
CONTROL AND
SENSORS
MOTOR
DRIVER
(MOTOR)
SCANNER
CONTROL
AND
PROCESSING
RTC
CRYSTAL
DATA
MEMORY
PROGRAM
MEMORY
GENERAL
PURPOSE I/ 0
OP00-OP06
LED_CTL
LCD_EN
OPI0-OPI3
STB 0-3
PDAT
PCLK
PLAT
THADI
SM0-SM3
MODE
SI
CLK1
Vin
+Vref
-Vref
XIN
XOUT
/DMS
/RD /WR
D0~D7
A0~A14
/RD
D0~D7
A0~A15
A16
/PMS
RESTOUT
/RESET
KS16118
Circuit Description
SF150T 5-3
Figure 5-4: Printer Timing
5-2-4 Real Time Clock (RTC)
This circuit receives clock pulses from an external
32.768 kHz crystal, which it divides into hours,
minutes, seconds, year, month, and day.
A battery maintains operation when power is off.
KS16118 can up-track 100 years, begining with
1992.
5-2-5 Print Control
The PCLK and PDATA signals synchronize serial
print data to the TPH.
PLAT latches TPH serial print data to the TPH
from a shift register through PDATA.
STB0 - STB3 enable TPH printing in four steps.
This system has a 10ms/line printing format and
sets STB High/Low enable status
according to the STBPOL signal.
PDATA
PCLK
PLAT
STB0
STB1
STB2
STBWID
[0:11]
STB0FF
[0:11]
STB3
Figure 5-6: THD Connection Circuit
GND5
THD1
+5V
R5
R4
Rth
(T)
TPH
Thermistor
5-2-6. A/D Converter (Scanner & TPH
Temperature)
Using a half-flash conversion technique, the 6-bit
A/D converter supports a 0.8µs peak conversion
time and dissipates only 7mA, maximum.
The half-flash unit uses 16 comparators, a most
significant 3-bit ADC, and a least significant 3-bit
ADC.
If the analog input voltage is greater than +Vref,
the A/D conversion result is 3FH.
If the analog input voltage is less than -Vref, the
A/D conversion result is 00H.
A/D conversion register, ADCON (19H), is used
to select an internal or external source for the A/D
converter, to enable or disable the converter, and
to select the operating mode (H: ADin 1 (Scanner),
L: ADin 0 (TPH)).
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