Samsung S6C0671 Datasheet
.
S6C0671
written permission of LCD Driver IC Team.
8 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
February. 2000.
Ver. 0.0
Prepared by: Myoung-Sik, Suh
mail to: mssuh@samsung.co.kr
S6C0671 8 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
S6C0671 Specification Revision History
Version Content Date
0.0 Original Feb.2000
0.1 Ac timging Mar. 2000
2
8 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER S6C0671
CONTENTS
INTRODUCTION.................................................................................................................................................4
FEATURES......................................................................................................................................................... 4
BLOCK DIAGRAM..............................................................................................................................................5
PIN ASSIGNMENTS............................................................................................................................................6
PIN DESCRIPTIONS...........................................................................................................................................7
OPERATION DESCRIPTION.............................................................................................................................. 8
DISPLAY DATA TRANSFER............................................................................................................................ 8
EXTENSION OF OUTPUT...............................................................................................................................8
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE.................................................8
RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE...............................................11
RECOMMENDED OPERATION CONDITIONS.................................................................................................25
DC CHARACTERISTICS................................................................................................................................... 26
AC CHARACTERISTICS ................................................................................................................................... 27
WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1) ............................................................................................28
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD ....................... 29
3
S6C0671 8 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
INTRODUCTION
The S6C0671 is a 384 channel output, TFT-LCD source driver for an 256 gray scale LCD panel. Data input is
based on digital input consisting of 8 bits by 6 dots, which can realize a full-color display of 16,700,000 color by
output of 256 values gamma-corrected.
This device has an internal D/A (Digital-to-Analog) converter for each output and 18 (9-by-2) reference voltages.
Because the output dynamic range is as large as 7.8 - 14.8 Vp-p, it is unnecessary to operate level inversion of
the LCD's common electrode. Besides, to be able to deal with dot-line inversion when mounted on a single-side,
output gray scale voltages with different polarity can be output to the odd number output pins and the even output
pins.
S6C0671 can be adopted to larger panel, and SHL (shift direction selection) pin makes the use of the LCD panel
connection conveniently. Maximum operation clock frequency is 65 MHz at 2.7 V logic operation and it can be
applied to the TFT-LCD panel of XGA/SXGA standard.
FEATURES
• TFT active matrix LCD source driver LSI
• 256G/S is possible through 18 (9 by 2) reference voltages and D/A converter
• Both dot inversion display and N-line inversion display are possible
• CMOS level input
• Compatible with gamma-correction
• Input data inversion function (DATPOL1,2)
• Logic supply voltage: 2.7 - 3.6 V
• LCD driver supply voltage: 8.0 - 15.0 V
• Output dynamic range: 7.8 - 14.8 Vp-p
• Maximum operating frequency: fMAX = 65 MHz (internal data transmission rate at 2.7 V operation)
• Output: 384 outputs
• TCP
4
8 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER S6C0671
Y001
BLOCK DIAGRAM
POL
VGMA1 -
VGMA18
CLK1
18
Y384
8 8 8 8 8 8
8 8 8 8 8 8
Y383
Y382
Output Buffer
D/A Converter
Data Latch
Y003
Y002
DATPOL1
DATPOL2
D00 - D07
D10 - D17
D20 - D27
D30 - D37
D40 - D47
D50 - D57
CLK2
Data Register
8
8
8
8
8
8
24
24
Data Control
64bit Shift Register
DIO2 DIO1
SHL
Figure 1. S6C0671 Block Diagram
5
S6C0671 8 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
PIN ASSIGNMENTS
DIO1
D00
D01
D02
D03
D04
Y001
Y002
Y003
Y004
Y381
Y382
Y383
Y384
(Top View)
S6C0671
D05
D06
D07
D10
D11
D12
D13
D14
D15
D16
D17
D20
D21
D22
D23
D24
D25
D26
D27
TEST
DATPOL1
DATPOL2
POL
CLK1
CLK2
VSS1
VGMA1
VGMA2
VGMA3
VGMA4
VGMA5
VGMA6
VGMA7
VGMA8
VGMA9
VSS2
VDD2
VGMA10
VGMA11
VGMA12
VGMA13
VGMA14
VGMA15
VGMA16
VGMA17
VGMA18
SHL
VDD1
D30
D31
D32
D33
D34
D35
D36
D37
D40
D41
D42
D43
D44
D45
D46
D47
D50
D51
D52
D53
D54
D55
D56
D57
DIO2
Figure 2. S6C0671 Pin Assignments
6
8 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER S6C0671
PIN DESCRIPTIONS
Symbol Pin Name Description
VDD1 Logic power supply 2.7 - 3.6 V
VDD2 Driver power supply 8.0 - 15.0 V
VSS1 Logic ground Ground (0 V)
VSS2 Driver ground Ground (0 V)
Y1 – Y384 Driver outputs The D/A converted 256 gray-scale analog voltage is output.
D0<0:7>
- D5<0:7>
SHL
DIO1 Start pulse input/output
DIO2 Start pulse input/output
DATPOL1
DATPOL2
POL Polarity input
CLK2
CLK1 Latch input
VGMA1
–
VGMA18
TEST Test input
Display data input
Shift direction control
input
Data inversion input
Shift clock input
Gamma corrected power
supplies
The display data is input with a width of 48 bits,
gray-scale data (8 bits) by 6 dots (R,G,B) DX0: LSB, DX7: MSB
This pin controls the direction of shift register in cascade connection.
The shift direction of the shift registers is as follows.
SHL = H: DIO1 input, Y1 → Y384, DIO2 output
SHL = L: DIO2 input, Y384 → Y1, DIO1 output
SHL = H: Used as the start pulse input pin.
SHL = L: Used as the start pulse output pin.
SHL = H: Used as the start pulse output pin.
SHL = L: Used as the start pulse input pin.
DATPOL1,2 = L: Display data is not inverted
DATPOL1 = H: Display data of D0<0:7> - D2<0:7> is inverted
DATPOL2 = H: Display data of D3<0:7> - D5<0:7> is inverted
POL = H: The reference voltage for odd number outputs are VGMA10 –
VGMA18 and those for even number outputs are VGMA1 – VGMA9.
POL = L: The reference voltage for odd number outputs are VGMA1 –
VGMA9 and those for even number outputs are VGMA10 – VGMA18.
Refer to the shift register's shift clock input. the display data is loaded to
the data register at the rising edge of CLK2.
Latches the contents of the data register at rising edge and transfers
them to the D/A converter. Also, after CLK1 input, clears the internal
shift register contents. After 1 pulse input on start, operates normally.
CLK1 input timing refers to the "Relationships between CLK1 start pulse
(DIO1, DIO2) and blanking period" of the switching characteristic
waveform. Outputs the G/S data at falling edge.
Input the gamma corrected power supplies from external source.
VDD2 > VGMA1 > VGMA2 > …… > VGMA17 > VGMA18 > VSS2
Keep gray-scale power supply unchanged during the gray-scale
voltage output.
TEST = L: Normal operation mode
TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 10kΩ)
7
S6C0671 8 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
OPERATION DESCRIPTION
DISPLAY DATA TRANSFER
When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse
enables the operation of data transfer, so display data is valid on the next rising edge of CLK2. Once all the
data of 384 channels are loaded into internal latch, it goes into stand-by state automatically, and any new data
is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is
provided, new display data is valid on the 2nd rising edge of CLK2 after the rising edge of DIO1 (or DIO2).
EXTENSION OF OUTPUT
Output pin can be adjusted to an extended screen by cascade connection.
(1) SHL = "L"
Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins
except DIO1 and DIO2 are connected together in each device.
(2) SHL = "H"
Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins
except DIO2 and DIO1 are connected together in each device.
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE
The LCD drive output voltages are determined by the input data and 18 (9 by 2) gamma corrected power supplies
(VGMA1 - VGMA18). Besides, to be able to deal with dot line inversion when mounted on a single-side, gradation
voltages with different polarity can be output to the odd number output pins and the even number output pins.
Among 9-by-2 gamma corrected voltages, input gray-scale voltages of the same polarity with respect to the
common voltage, for the respective 9 gamma corrected voltages of VGMA1 – VGMA9 and VGMA10 - VGMA18.
SHL = H
OUTPUT
-
DATA
SHL = L
OUTPUT
-
DATA
Y1 - Y6 ...... Y379 - Y384
First Last
D00 - D07 - D50 - D57 ...... D00 - D07 - D50 - D57
Y1 - Y6 ...... Y379 - Y384
Last First
D00 - D07 - D50 - D57 ...... D00 - D07 - D50 - D57
Figure 3. Relationship between Shift Direction and Output Data
8
8 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER S6C0671
VDD2
VGMA1
VGMA2
VGMA3
VGMA4
VGMA5
VGMA6
VGMA7
VGMA8
VGMA9
1
30
32
64
64
32
31
1
VCOM
VGMA10
VGMA11
VGMA12
1
31
32
VGMA13
VGMA14
VGMA15
VGMA16
VGMA17
VGMA18
VSS2
00H 20H 40H 60H 80H A0H C0H E0H FFH
64
64
32
30
1
Figure 4. Gamma Correction Curve
9
Loading...