Samsung S6C0670 Datasheet
.
S6C0670
written permission of LCD Driver IC Team.
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
March. 2000.
Ver. 1.0
Prepared by: Myoung-Sik, Suh
mail to: mssuh@samsung.co.kr
S6C0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
S6C0670 Specification Revision History
Version Content Date
0.0 Original Aug.1999
1.0 “Resistor strings” , “CLK1 pulse high period” Mar.2000
2
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER S6C0670
CONTENTS
INTRODUCTION.................................................................................................................................................4
FEATURES......................................................................................................................................................... 4
BLOCK DIAGRAM..............................................................................................................................................5
PIN ASSIGNMENTS............................................................................................................................................6
PIN DESCRIPTIONS...........................................................................................................................................7
OPERATION DESCRIPTION.............................................................................................................................. 8
DISPLAY DATA TRANSFER............................................................................................................................ 8
EXTENSION OF OUTPUT...............................................................................................................................8
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE.................................................8
RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE...............................................12
ABSOLUTE MAXIMUM RATINGS....................................................................................................................26
RECOMMENDED OPERATION CONDITIONS.................................................................................................26
DC CHARACTERISTICS................................................................................................................................... 27
SINGLE EDGE AC CHARACTERISTICS .......................................................................................................... 28
DOUBLE EDGE AC CHARACTERISTICS........................................................................................................ 29
SINGLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1) ...................................................................30
DOUBLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1).................................................................. 31
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD ....................... 32
3
S6C0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
INTRODUCTION
The S6C0670 is a 384 / 402 channel output, TFT-LCD source driver for an 256 gray scale LCD panel. Data input
is based on digital input consisting of 8 bits by 6 dots, which can realize a full-color display of 16,700,000 color by
output of 256 values gamma-corrected.
This device has an internal D/A (Digital-to-Analog) converter for each output and 16 (8-by-2) reference voltages.
Because the output dynamic range is as large as 7.8 - 14.8 Vp-p, it is unnecessary to operate level inversion of
the LCD's common electrode. Besides, to be able to deal with dot-line inversion when mounted on a single-side,
output gray scale voltages with different polarity can be output to the odd number output pins
and the even output pins.
S6C0670 can be adopted to larger panel, and SHL (shift direction selection) pin makes the use of the LCD panel
connection conveniently. Maximum operation clock frequency is 75 MHz at 3.0 V logic operation, single edge
and it can be applied to the TFT-LCD panel of UXGA standard.
FEATURES
• TFT active matrix LCD source driver LSI
• 256 G/S is possible through 16 (8 by 2) reference voltages and D/A converter
• Both dot inversion display and N-line inversion display are possible
• CMOS level input
• Compatible with gamma-correction
• Input data inversion function (DATPOL1,2)
• Single edge, Double edge compatible (DEC)
• Logic supply voltage: 2.5 - 3.6 V
• LCD driver supply voltage: 8.0 - 15.0 V
• Output dynamic range: 7.8 - 14.8 Vp-p
• Maximum operating frequency: fMAX = 75 MHz
(internal data transmission rate at 3.0 V operation, single edge)
• Output: 384 / 402 outputs
• TCP available
4
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER S6C0670
Y001
BLOCK DIAGRAM
POL
VGMA1 -
VGMA16
CLK1
16
Y402
8 8 8 8 8 8
8 8 8 8 8 8
Y401
Y400
Output Buffer
D/A Converter
Data Latch
Y003
Y002
DATPOL1
DATPOL2
D00 - D07
D10 - D17
D20 - D27
D30 - D37
D40 - D47
D50 - D57
CLK2
Data Register
8
8
8
8
8
8
24
24
Data Control
67bit Shift Register
SHL
SELTDIO2 DEC DIO1
Figure 1. S6C0670 Block Diagram
5
S6C0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
PIN ASSIGNMENTS
DIO1
D00
D01
D02
D03
D04
Y001
Y002
Y003
Y004
Y399
Y400
Y401
Y402
(Top View)
S6C0670
D05
D06
D07
D10
D11
D12
D13
D14
D15
D16
D17
D20
D21
D22
D23
D24
D25
D26
D27
TEST
DATPOL1
DATPOL2
POL
CLK1
CLK2
DEC
VSS1
VGMA1
VGMA2
VGMA3
VGMA4
VGMA5
VGMA6
VGMA7
VGMA8
VSS2
VDD2
VGMA9
VGMA10
VGMA11
VGMA12
VGMA13
VGMA14
VGMA15
VGMA16
SELT
SHL
VDD1
D30
D31
D32
D33
D34
D35
D36
D37
D40
D41
D42
D43
D44
D45
D46
D47
D50
D51
D52
D53
D54
D55
D56
D57
DIO2
Figure 2. S6C0670 Pin Assignments
6
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER S6C0670
PIN DESCRIPTIONS
Symbol Pin Name Description
VDD1 Logic power supply 2.5 - 3.6 V
VDD2 Driver power supply 8.0 - 15.0 V
VSS1 Logic ground Ground (0 V)
VSS2 Driver ground Ground (0 V)
Y1 - Y402 Driver outputs The D/A converted 256 gray-scale analog voltage is output.
D0<0:7>
- D5<0:7>
SHL
DIO1 Start pulse input/output
DIO2 Start pulse input/output
DATPOL1
DATPOL2
POL Polarity input
CLK2 Shift clock input
CLK1 Latch input
VGMA1
–
VGMA16
SELT Output selection input
DEC
TEST Test input
Display data input
Shift direction control
input
Data inversion input
Gamma corrected power
supplies
Double edge selection
input
The display data is input with a width of 48 bits,
gray-scale data (8 bits) by 6 dots (R,G,B) DX0: LSB, DX7: MSB
This pin controls the direction of shift register in cascade connection.
The shift direction of the shift registers is as follows.
SHL = H: DIO1 input, Y1 → Y402, DIO2 output
SHL = L: DIO2 input, Y402 → Y1, DIO1 output
SHL = H: Used as the start pulse input pin.
SHL = L: Used as the start pulse output pin.
SHL = H: Used as the start pulse output pin.
SHL = L: Used as the start pulse input pin.
DATPOL1,2 = L: Display data is not inverted
DATPOL1 = H: Display data of D0<0:7> - D2<0:7> is inverted
DATPOL2 = H: Display data of D3<0:7> - D5<0:7> is inverted
POL = H: The reference voltage for odd number outputs are VGMA9 –
VGMA16 and those for even number outputs are VGMA1 – VGMA8.
POL = L: The reference voltage for odd number outputs are VGMA1 –
VGMA8 and those for even number outputs are VGMA9 – VGMA16.
Refer to the shift register's shift clock input. When DEC is Low, the
display data is loaded to the data register at the rising edge of
CLK2.When DEC is High, the display data is loaded to the data register
at the rising and falling edge of CLK2.
Latches the contents of the data register at rising edge and transfers
them to the D/A converter. Also, after CLK1 input, clears the internal
shift register contents. After 1 pulse input on start, operates normally.
CLK1 input timing refers to the "Relationships between CLK1 start pulse
(DIO1, DIO2) and blanking period" of the switching characteristic
waveform. Outputs the G/S data at falling edge.
Input the gamma corrected power supplies from external source.
VDD2 > VGMA1 > VGMA2 > …… > VGMA15 > VGMA16 > VSS2
Keep gray-scale power supply unchanged during the gray-scale
voltage output.
SELT = L: 384 Output (Y193 - Y210 are disabled), SELT = H: 402
Output
DEC = L: Single Edge, the display data is loaded to the data register at
the rising edge of CLK2. DEC = H: Double Edge, the display data is
loaded to the data register at the rising and falling edge of CLK2.
TEST = L: Normal operation mode
TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 10kΩ)
7
S6C0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
OPERATION DESCRIPTION
DISPLAY DATA TRANSFER
(1) DEC = ”L”
When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse
enables the operation of data transfer, so display data is valid on the next rising edge of CLK2. Once all the
data of 402 (or 384) channels is loaded into internal latch, it goes into stand-by state automatically, and any
new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or
DIO2) is provided, new display data is valid on the 2nd rising edge of CLK2 after the rising edge of DIO1 (or
DIO2).
(2) DEC = ”H”
When DIO1 (or DIO2) pulse is loaded into internal latch on the rising (or falling) edge of CLK2, DIO1 (or DIO2)
pulse enables the operation of data transfer. display data is valid on the next falling (or rising) edge of CLK2.
Once all the data of 402 (or 384) channels is loaded into internal latch, it goes into stand-by state
automatically, and any new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2)
input. When next DIO1 (or DIO2) is provided, new display data is valid on the 2nd edge of CLK2 after the
rising edge of DIO1 (or DIO2).
EXTENSION OF OUTPUT
Output pin can be adjusted to an extended screen by cascade connection.
(1) SHL = "L"
Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins
except DIO1 and DIO2 are connected together in each device.
(2) SHL = "H"
Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins
except DIO2 and DIO1 are connected together in each device.
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE
The LCD drive output voltages are determined by the input data and 16 (8 by 2) gamma corrected power supplies
(VGMA1 - VGMA16). Besides, to be able to deal with dot line inversion when mounted on a single-side, gradation
voltages with different polarity can be output to the odd number output pins and the even number output pins.
Among 8-by-2 gamma corrected voltages, input gray-scale voltages of the same polarity with respect to the
common voltage, for the respective 8 gamma corrected voltages of VGMA1 - VGMA8 and VGMA9 - VGMA16.
8
8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER S6C0670
SHL = H
OUTPUT
DATA
SHL = L
OUTPUT
DATA
VDD2
VGMA1
VGMA2
VGMA3
VGMA4
VGMA5
VGMA6
Y1 Y2
D00 - D07 D10 - D17
Y1 Y2 Y3 ...... Y400 Y401 Y402
-
D00 - D07 D10 - D17 D20 - D27 ...... D30 - D37 D40 - D47 D50 - D57
First Last
Last First
Y3 ......
D20 - D27 ......
Y400 Y401 Y402
D30 - D37 D40 - D47 D50 - D57
Figure 3. Relationship between Shift Direction and Output Data
32
32
64
64
48
14
VGMA7,8
VGMA9,10
VGMA11
VGMA12
VGMA13
VGMA14
VGMA15
VGMA16
VSS2
VCOM
14
48
64
64
32
32
00H 20H 40H 60H 80H A0H C0H E0H FFH
Figure 4. Gamma Correction Curve
9
S6C0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER
Table 1. Resistor Strings (R0 - R254, unit: Ω)
Name Value Name Value Name Value Name Value
R0 404 R32 74 R64 50 R96 36
R1 320 R33 73 R65 49 R97 36
R2 263 R34 72 R66 48 R98 36
R3 224 R35 72 R67 47 R99 36
R4 196 R36 71 R68 46 R100 36
R5 177 R37 71 R69 45 R101 36
R6 163 R38 71 R70 44 R102 36
R7 153 R39 70 R71 43 R103 36
R8 144 R40 70 R72 42 R104 36
R9 138 R41 69 R73 41 R105 36
R10 132 R42 69 R74 40 R106 35
R11 127 R43 69 R75 40 R107 35
R12 122 R44 68 R76 39 R108 35
R13 118 R45 68 R77 38 R109 35
R14 113 R46 67 R78 38 R110 35
R15 109 R47 67 R79 37 R111 35
R16 106 R48 66 R80 37 R112 35
R17 102 R49 65 R81 37 R113 35
R18 99 R50 65 R82 36 R114 35
R19 96 R15 64 R83 36 R115 34
R20 93 R52 63 R84 36 R116 34
R21 90 R53 62 R85 36 R117 34
R22 88 R54 61 R86 36 R118 34
R23 86 R55 60 R87 36 R119 34
R24 84 R56 59 R88 36 R120 34
R25 82 R57 58 R89 36 R121 34
R26 80 R58 57 R90 36 R122 34
R27 79 R59 56 R91 36 R123 34
R28 77 R60 55 R92 36 R124 34
R29 76 R61 53 R93 36 R125 33
R30 75 R62 52 R94 36 R126 33
R31 74 R63 51 R95 36 R127 33
10
Loading...