Samsung S6B0796 Datasheet
S6B0796
written permission of LCD Driver IC Team.
240 SEG / COM DRIVER FOR STN LCD
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
January, 2000
Ver. 1.0
Prepared by: Gyeong-Nam, Kim
kgn@samsung.co.kr
240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796
S6B0796 Specification Revision History
Version Content Date
0.0 l Original June.1999
0.1 l p6, p16 revision August.1999
1.0 l p4 Introduction revision. January. 2000
2
S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD
CONTENTS
INTRODUCTION ..................................................................................................................................................4
FEATURES..........................................................................................................................................................4
BLOCK DIAGRAM...............................................................................................................................................5
PAD CONFIGURATION (TBD).............................................................................................................................6
PAD CENTER COORDINATES ............................................................................................................................7
PIN DESCRIPTION ..............................................................................................................................................9
FUNCTIONAL DESCRIPTION............................................................................................................................ 10
BLOCK FUNCTION.....................................................................................................................................10
PIN FUNCTION...........................................................................................................................................11
FUNCTIONAL OPERATIONS......................................................................................................................15
SPECIFICATIONS..............................................................................................................................................18
ABSOLUTE MAXIMUM RATINGS...............................................................................................................18
RECOMMENDED OPERATING CONDITIONS ...........................................................................................18
DC CHARACTERISTICS.............................................................................................................................19
AC CHARACTERISTICS.............................................................................................................................21
PRECAUTION....................................................................................................................................................28
CONNECTION EXAMPLES OF PLURAL SEGMENT DRIVERS........................................................................29
TIMING CHART OF 4-DEVICE CASECADE CONNECTION OF SEGMENT DRIVERS......................................30
CONNECTION EXAMPLES OF PLURAL COMMON DRIVERS.........................................................................31
3
240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796
INTRODUCTION
The S6B0796 is a 240-outputs segment/common driver LSI for graphic dot-matrix liquid
crystal display systems. It is fabricated by low power CMOS high voltage process technology.
This device consists of 240-bits bi-directional shift register, 240-bits data latch and 240-bits
driver. In case of segment mode, the data input is selected 4bit parallel input mode and 8bit
parallel input mode by a mode (MD) pin. In case of common mode, data input/output pins are
bi-directional, four data shift directions are pin-selectable.
FEATURES
Both Segment Mode and Common Mode
- Supply voltage for LC driver: +15.0 to +32.0V
- Number of LC driver outputs: 240
- Low output impedance
- Low power consumption
- Supply voltage for the logic system: +2.4V to +5.5V
- CMOS silicon gate process (P-type Silicon Substrate)
- Package: 268-pin TCP (Tape Carrier Package) or Gold bumped chip
Segment Mode
- Shift clock frequency: 20MHz (Max) (Vdd=+5V±10%)
12MHz (Max) (Vdd=+2.4V to +4.5V)
- Adopts a data bus system
- 4- / 8-bit parallel input modes are selectable with a mode (MD) pin
- Automatic transfer function of an enable signal
- Automatic counting function which, in the chip select, causes the internal clock to be stopped
by automatically counting 240 of input data
- Line latch circuit reset function when DISPOFFB active
Common Mode
- Shift clock frequency: 4.0MHz (Max) (vdd=+2.4V to +5.5V)
- Built-in 240-bits bi-directional shift register (divisible into 120-bits ×2)
- Available in a single mode (240-bits shift register)
or in a dual mode (120-bits shift register ×2)
- Shift register circuit reset function when DISPOFFB active
4
S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD
BLOCK DIAGRAM
FR
260
DISPOFFB
EIO1
EIO2
LP
XCK
257
259
247
258
256
VORV
12R
V43R V5L
268 267 266 265
LEVEL
SHIFTER
ACTIVE
CONTROL
CONTROL
LOGIC
Y240Y239Y1 Y2
1 2 240239
240 BITS 4-LEVEL DRIVER
240
240 BITS LEVEL SHIFTER
240
240 BITS LINE LATCH/SHIFTER
REGISTER
16 16
8BITS*2
DATA
LATCH
16
16 16
16
16
16
244
243
242
241
V5L
V43L
V12L
VOL
L/R
MD
S/C
261
262
246
DATA LATCH CONTROL
8
SP CONVERSION & DATA CONTROL
(4 to 8 or 8to 8)
248 249 250 251 252 253 254 255 264245
D I0D I1D
D I3DI4DI5DI6DI
I
2
Figure 1. Block Diagram
7
V
DD
VSS
5
240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796
1
240
ð
ð
ð
ð
ð
ð
ð
ð
PAD CONFIGURATION
ррррррррррррррррррррр
241
S6B0796
(TOP VIEW, Pads Up)
- - - - - - - - - -
Y
(0,0)
рррррррррррррррррррр
X
ð ð ð ð ð ð ð ð ð ð ð ð ð ð - - - - - - - - - - ð ð ð ð ð ð ð ð ð ð ð ð
Figure 2. S6B0796 Chip Configuration
Table 1. S6B0796 Pad Dimensions
Item Pad NO.
Chip size - 16200 1100
Pad pitch
1 to 240
241 to 292
Size
X Y
65 (Min.)
260 (Min.)
288 245
ð
Unit
292
289244
1 to 240
Bumped pad size
Bumped pad height 1 to 292 14 (Typ.)
6
241 to 244
289 to 292
245 to 288 58 76
43 108
µm
76 73
S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates
[Unit: µm]
NO NAME X Y NO NAME X Y NO NAME X Y
1 Y1 7767.5 395 51 Y51 4517.5 395 101 Y101 1267.5 395
2 Y2 7702.5 395 52 Y52 4452.5 395 102 Y102 1202.5 395
3 Y3 7637.5 395 53 Y53 4387.5 395 103 Y103 1137.5 395
4 Y4 7572.5 395 54 Y54 4322.5 395 104 Y104 1072.5 395
5 Y5 7507.5 395 55 Y55 4257.5 395 105 Y105 1007.5 395
6 Y6 7442.5 395 56 Y56 4192.5 395 106 Y106 942.5 395
7 Y7 7377.5 395 57 Y57 4127.5 395 107 Y107 877.5 395
8 Y8 7312.5 395 58 Y58 4062.5 395 108 Y108 812.5 395
9 Y9 7247.5 395 59 Y59 3997.5 395 109 Y109 747.5 395
10 Y10 7182.5 395 60 Y60 3932.5 395 110 Y110 682.5 395
11 Y11 7117.5 395 61 Y61 3867.5 395 111 Y111 617.5 395
12 Y12 7052.5 395 62 Y62 3802.5 395 112 Y112 552.5 395
13 Y13 6987.5 395 63 Y63 3737.5 395 113 Y113 487.5 395
14 Y14 6922.5 395 64 Y64 3672.5 395 114 Y114 422.5 395
15 Y15 6857.5 395 65 Y65 3607.5 395 115 Y115 357.5 395
16 Y16 6792.5 395 66 Y66 3542.5 395 116 Y116 292.5 395
17 Y17 6727.5 395 67 Y67 3477.5 395 117 Y117 227.5 395
18 Y18 6662.5 395 68 Y68 3412.5 395 118 Y118 162.5 395
19 Y19 6597.5 395 69 Y69 3347.5 395 119 Y119 97.5 395
20 Y20 6532.5 395 70 Y70 3282.5 395 120 Y120 32.5 395
21 Y21 6467.5 395 71 Y71 3217.5 395 121 Y121 -32.5 395
22 Y22 6402.5 395 72 Y72 3152.5 395 122 Y122 -97.5 395
23 Y23 6337.5 395 73 Y73 3087.5 395 123 Y123 -162.5 395
24 Y24 6272.5 395 74 Y74 3022.5 395 124 Y124 -227.5 395
25 Y25 6207.5 395 75 Y75 2957.5 395 125 Y125 -292.5 395
26 Y26 6142.5 395 76 Y76 2892.5 395 126 Y126 -357.5 395
27 Y27 6077.5 395 77 Y77 2827.5 395 127 Y127 -422.5 395
28 Y28 6012.5 395 78 Y78 2762.5 395 128 Y128 -487.5 395
29 Y29 5947.5 395 79 Y79 2697.5 395 129 Y129 -552.5 395
30 Y30 5882.5 395 80 Y80 2632.5 395 130 Y130 -617.5 395
31 Y31 5817.5 395 81 Y81 2567.5 395 131 Y131 -682.5 395
32 Y32 5752.5 395 82 Y82 2502.5 395 132 Y132 -747.5 395
33 Y33 5687.5 395 83 Y83 2437.5 395 133 Y133 -812.5 395
34 Y34 5622.5 395 84 Y84 2372.5 395 134 Y134 -877.5 395
35 Y35 5557.5 395 85 Y85 2307.5 395 135 Y135 -942.5 395
36 Y36 5492.5 395 86 Y86 2242.5 395 136 Y136 -1007.5 395
37 Y37 5427.5 395 87 Y87 2177.5 395 137 Y137 -1072.5 395
38 Y38 5362.5 395 88 Y88 2112.5 395 138 Y138 -1137.5 395
39 Y39 5297.5 395 89 Y89 2047.5 395 139 Y139 -1202.5 395
40 Y40 5232.5 395 90 Y90 1982.5 395 140 Y140 -1267.5 395
41 Y41 5167.5 395 91 Y91 1917.5 395 141 Y141 -1332.5 395
42 Y42 5102.5 395 92 Y92 1852.5 395 142 Y142 -1397.5 395
43 Y43 5037.5 395 93 Y93 1787.5 395 143 Y143 -1462.5 395
44 Y44 4972.5 395 94 Y94 1722.5 395 144 Y144 -1527.5 395
45 Y45 4907.5 395 95 Y95 1657.5 395 145 Y145 -1592.5 395
46 Y46 4842.5 395 96 Y96 1592.5 395 146 Y146 -1657.5 395
47 Y47 4777.5 395 97 Y97 1527.5 395 147 Y147 -1722.5 395
48 Y48 4712.5 395 98 Y98 1462.5 395 148 Y148 -1787.5 395
49 Y49 4647.5 395 99 Y99 1397.5 395 149 Y149 -1852.5 395
50 Y50 4582.5 395 100 Y100 1332.5 395 150 Y150 -1917.5 395
7
240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796
Table 2. Pad Center Coordinates (Continued)
[Unit: µm]
NO NAME X Y NO NAME X Y NO NAME X Y
151 Y151 -1982.5 395 201 Y201 -5232.5 395 251 DUMMY -5900 -419
152 Y152 -2047.5 395 202 Y202 -5297.5 395 252 VDD -5640 -419
153 Y153 -2112.5 395 203 Y203 -5362.5 395 253 VDD -5380 -419
154 Y154 -2177.5 395 204 Y204 -5427.5 395 254 VDD -5120 -419
155 Y155 -2242.5 395 205 Y205 -5492.5 395 255 VDD -4860 -419
156 Y156 -2307.5 395 206 Y206 -5557.5 395 256 VDD -4600 -419
157 Y157 -2372.5 395 207 Y207 -5622.5 395 257 SC -4340 -419
158 Y158 -2437.5 395 208 Y208 -5687.5 395 258 EIO2 -4080 -419
159 Y159 -2502.5 395 209 Y209 -5752.5 395 259 DI0 -3820 -419
160 Y160 -2567.5 395 210 Y210 -5817.5 395 260 DI1 -3560 -419
161 Y161 -2632.5 395 211 Y211 -5882.5 395 261 DI2 -3300 -419
162 Y162 -2697.5 395 212 Y212 -5947.5 395 262 DI3 -3040 -419
163 Y163 -2762.5 395 213 Y213 -6012.5 395 263 DI4 -2780 -419
164 Y164 -2827.5 395 214 Y214 -6077.5 395 264 DI5 -2520 -419
165 Y165 -2892.5 395 215 Y215 -6142.5 395 265 DI6 -2260 -419
166 Y166 -2957.5 395 216 Y216 -6207.5 395 266 DI7 -2000 -419
167 Y167 -3022.5 395 217 Y217 -6272.5 395 267 XCK 1770 -419
168 Y168 -3087.5 395 218 Y218 -6337.5 395 268 DISPOFFB 2030 -419
169 Y169 -3152.5 395 219 Y219 -6402.5 395 269 LP 2290 -419
170 Y170 -3217.5 395 220 Y220 -6467.5 395 270 EIO1 2550 -419
171 Y171 -3282.5 395 221 Y221 -6532.5 395 271 FR 2810 -419
172 Y172 -3347.5 395 222 Y222 -6597.5 395 272 LR 3070 -419
173 Y173 -3412.5 395 223 Y223 -6662.5 395 273 MD 3330 -419
174 Y174 -3477.5 395 224 Y224 -6727.5 395 274 NC 3590 -419
175 Y175 -3542.5 395 225 Y225 -6792.5 395 275 VSS 3850 -419
176 Y176 -3607.5 395 226 Y226 -6857.5 395 276 VSS 4110 -419
177 Y177 -3672.5 395 227 Y227 -6922.5 395 277 VSS 4370 -419
178 Y178 -3737.5 395 228 Y228 -6987.5 395 278 VSS 4630 -419
179 Y179 -3802.5 395 229 Y229 -7052.5 395 279 VSS 4890 -419
180 Y180 -3867.5 395 230 Y230 -7117.5 395 280 VSS 5150 -419
181 Y181 -3932.5 395 231 Y231 -7182.5 395 281 DUMMY 5410 -419
182 Y182 -3997.5 395 232 Y232 -7247.5 395 282 DUMMY 5670 -419
183 Y183 -4062.5 395 233 Y233 -7312.5 395 283 DUMMY 5930 -419
184 Y184 -4127.5 395 234 Y234 -7377.5 395 284 DUMMY 6190 -419
185 Y185 -4192.5 395 235 Y235 -7442.5 395 285 DUMMY 6450 -419
186 Y186 -4257.5 395 236 Y236 -7507.5 395 286 DUMMY 6710 -419
187 Y187 -4322.5 395 237 Y237 -7572.5 395 287 DUMMY 6970 -419
188 Y188 -4387.5 395 238 Y238 -7637.5 395 288 DUMMY 7230 -419
189 Y189 -4452.5 395 239 Y239 -7702.5 395 289 V5R 7969 -348.5
190 Y190 -4517.5 395 240 Y240 -7767.5 395 290 V43R 7969 -127.5
191 Y191 -4582.5 395 241 V0L -7969 344.5 291 V12R 7969 93.5
192 Y192 -4647.5 395 242 V12L -7969 93.5 292 V0R 7969 344.5
193 Y193 -4712.5 395 243 V43L -7969 -127.5
194 Y194 -4777.5 395 244 V5L -7969 -348.5
195 Y195 -4842.5 395 245 DUMMY -7460 -419
196 Y196 -4907.5 395 246 DUMMY -7200 -419
197 Y197 -4972.5 395 247 DUMMY -6940 -419
198 Y198 -5037.5 395 248 DUMMY -6680 -419
199 Y199 -5102.5 395 249 DUMMY -6420 -419
200 Y200 -5167.5 395 250 DUMMY -6160 -419
8
S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD
PIN DESCRIPTION
Pin No. Symbol I/O Description
1 to 240
241, 292
242, 291
243, 290
244, 289
272
252 to
256
257
258
259 to
265
266
267
268
269
270
271
Y1 – Y240 O LC driver output
V0L, V0R - Power supply for LC driver
V12L, V12R - Power supply for LC driver
V43L, V43R - Power supply for LC driver
V5L, V5R - Power supply for LC driver
L/R I Display data shift direction selection
VDD - Power supply for logic system(+2.4 to +5.5V)
S/C I Segment mode/common mode selection
EIO2 I/O Input/output for chip select or data of shift register
DI0 – DI6 I Display data input for segment mode
DI7 I Display data input for segment mode/Dual mode data input
XCK I Display data shift clock input for segment mode
DISPOFFB I Control input for deselect output level
LP I Latch pulse input/shift clock input for shift register
EIO1 I/O Input/output for chip select or data of shift register
FR I AC-converting signal input for LC driver waveform
273
275 to
280
MD I Mode selection input
VSS - Ground(0V)
Table 3 Pin Description
9
240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796
FUNCTIONAL DESCRIPTION
BLOCK FUNCTION
. Active Control
In case of segment mode, controls the selection or deselection of the chip. Following a LP
signal, and after the chip select signal is input, a select signal is generated internally until 240
bits of data have been read in. Once data input has been completed, a select signal for
cascade connection is output, and the chip is deselected. In case of common mode, controls
the input/output data of bidirectional pins.
. SP Conversion & Data Control
In case of segment mode, keep input data which are 2 clocks of XCK at 4-bit parallel mode
into latch circuit, or keep input data which are 1 clock of XCK at 8-bits parallel mode into latch
circuit, after that they are put on the internal data bus 8 bits at a time.
. Data Latch Control
In case of segment mode, selects the state of the data latch which reads in the data bus
signals. The shift direction is controlled by the control logic, for every 16 bits of data read in, the
selection signal shifts one bit based on the state of the control circuit.
. Data Latch
In case of segment mode, latches the data on the data bus. The latched state of each LC
driver output pin is controlled by the control logic and the data latch control, 240 bits of data are
read in 30 sets of 8 bits.
. Line Latch / Shift Register
In case of segment mode, all 240 bits which have been read into the data latch are
simultaneously latched on the falling edge of the LP signal, and output to the level shifter block.
In case of common mode, shifts data from the data input pin on the falling edge of the LP
signal.
. Level Shifter
The logic voltage signal is level-shifted to the LC driver voltage level, and output to the driver
block.
. 4-level Driver
Driver the LC driver output pins from the line latch/shift register data, selecting one of 4 levels
(V0, V12, V43, V5) based on the S/C, FR and DISPOFFB signals.
. Control logic
Controls the operation of each block. In case of segment mode, when a LP signal has been
input, all blocks are reset and the control logic waits for the selection signal output from the
active control block. Once the selection signal has been output, operation of the data latch and
data transmission are controlled, 240 bits of data are read in, and the chip is deselected. In
case of common mode, controls the direction of data shift.
10
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