Samsung S6B0755 Datasheet

S6B0755

written permission of LCD Driver IC Team.

128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express

JUNE. 2000.

Ver. 1.0

Prepared by Hyoung_Seok ,Lee

mailto:[e-mail]

128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0755

S6B0755 Specification Revision History

Version Content Date

0.0 Original Dec.1999
Append PAD configuration

0.1

Append COG/ILB align key coordinates and TOM coordinate

Jan.2000

Append PAD center coordinates to table 1, 2
Added 6800-mode interface description for data latch with (page 12)

C2 CAP value : 0.1 to 0.47uF → 0.47 to 2.0uF (page 30)

0.2

Added description of the column address operation. (page 35)

Jan.2000

Added that Display On/Off command has priority over Entire Display
On/Off and Reverse Display On/Off. (page 39)

Added N-line inversion command description (page 43)

0.3

1.0

Modify 6800 parallel interface timing Feb.2000
Fix the TBD Value of DC Characteristics.

Modify dynamic current consumption value(Idd2.Idds1)

Jun.2000

2

S6B0755 PRELIMINARY SPEC. VER. 1.0 128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

CO

NTENTS

INTRODUCTION ..................................................................................................................................................1

BLOCK DIAGRAM...............................................................................................................................................2

PAD CONFIGURATION .......................................................................................................................................3

PIN DESCRIPTION ..............................................................................................................................................7

POWER SUPPLY ..........................................................................................................................................7

LCD DRIVER SUPPLY..................................................................................................................................7

SYSTEM CONTROL .....................................................................................................................................8

MICROPROCESSOR INTERFACE...............................................................................................................9

LCD DRIVER OUTPUTS.............................................................................................................................11

FUNCTIONAL DESCRIPTION............................................................................................................................ 12

MICROPROCESSOR INTERFACE.............................................................................................................12

DISPLAY DATA RAM (DDRAM)..................................................................................................................16

LCD DISPLAY CIRCUITS............................................................................................................................20

LCD DRIVER CIRCUIT ...............................................................................................................................22

POWER SUPPLY CIRCUITS ......................................................................................................................25

REFERECE CIRCUIT EXAMPLES..............................................................................................................30

RESET CIRCUIT.........................................................................................................................................32

INSTRUCTION DESCRIPTION...........................................................................................................................33

SPECIFICATIONS..............................................................................................................................................55

ABSOLUTE MAXIMUM RATINGS...............................................................................................................55

DC CHARACTERISTICS .............................................................................................................................56

AC CHARACTERISTICS.............................................................................................................................59

REFERENCE APPLICATIONS........................................................................................................................... 63

MICROPROCESSOR INTERFACE.............................................................................................................63

CONNECTIONS BETWEEN S6B0755 AND LCD PANEL............................................................................65

3

S6B0755 PRELIMINARY SPEC. VER. 1.0 128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

INTRODUCTION

The S6B0755 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 65
common and 128 segment driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8­bit parallel display data and stores in an on-chip display data RAM of 65 x 128 bits. It provides a highly flexible
display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it
performs display data RAM read/write operation with no externally operating clock to minimize power
consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible
to make a display system with the fewest components.

FEATURES

Driver Output Circuits

− 65 common outputs / 128 segment outputs

Applicable Duty Ratios

Programmable duty ratio Applicable LCD bias Maximum display area

1/17 to 1/65 1/4 to 1/9

− Various partial display

− Partial window moving & data scrolling

On-chip Display Data RAM

65 × 128

− Capacity: 65 x 128 = 8,320 bits

− Bit data "1": a dot of display is illuminated.

− Bit data "0": a dot of display is not illuminated.

Microprocessor Interface

− 8-bit parallel bi-directional interface with 6800-series or 8080-series.

− SPI (Serial Peripheral Interface) available. (only write operation)

On-chip Low Power Analog Circuit

− On-chip oscillator circuit

− Voltage converter (x3, x4 or x5)

− Voltage regulator (temperature coefficient: -0.05%/°C or external input)

− On-chip electronic contrast control function (64 steps)

− Voltage follower (LCD bias: 1/4 to 1/9)

Operating Voltage Range

− Supply voltage (VDD): 1.8 to 3.3 V

− LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V

Low power Consumption

− 120 µΑ Typ. (Internal power supply on and display OFF)

Package Type

− Gold bumped chip or TCP

1

128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0755

BLOCK DIAGRAM

SEG127

SEG126

VDD

V0
V1
V2
V3
V4

VSS2

:

SEG125

:

SEG2

SEG1

SEG0

128 SEGMENT

DRIVER CIRCUITS

COMS

COM0

:

:

66 COMMON

DRIVER CIRCUITS

COMS1

COM63

:

V0

VR

INTRS

VEXT

REF

VOUT

C1-

C1+

C2­C2+
C3+
C4+

VCI

V / F

CIRCUIT

V / R

CIRCUIT

V / C

CIRCUIT

INTERNAL

POWER
SUPPLY

PAGE

ADDRESS

CIRCUIT

SEGMENT CONTROLLER

DISPLAY DATA RAM

65 X 128 = 8,320Bits

COLUMN ADDRESS

CIRCUIT

INSTRUCTION DECODER & REGISTER

MPU INTERFACE (PARALLEL & SERIAL)

COMMON CONTROLLER

DISPLAY

LINE

ADDRESS

CIRCUIT

STATUS REGISTERBUS HOLDER

TIMING

GENERATOR

CIRCUIT/

OSCILLATOR

VSS1

VSS2

Test3

Test4

Test1

Test2

RESETB

DB0

DB1

DB2

DB3

DB4

DB5

DB6(SCLK)

DB7(SID)

RW_WR

E_RD

RS

CS1B

PS0

PS1

Figure 1. Block Diagram

2

S6B0755 PRELIMINARY SPEC. VER. 1.0 128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

PAD CONFIGURATION

Normal Dummy

290 145

291

317

S6B0755

(TOP VIEW)

1

Figure 2. S6B0755 Chip Configuration

Table 1. S6B0755 Pad Dimension

Item Pad No.

Chip size

Input 1 to 117 70

Pad pitch

Output

NC* 1,117,118,144,145,290,291,317 80

2 to 116 50 100

119 to 143 110 40

Y

(0,0)

- 9530 2080

119 to 143
146 to 289
292 to 316

1 60 110

117 60 110
118 110 60

X

117

Size

X Y

60

144

118

Unit

um

Bumped pad size (Max.)

Bumped pad height

* Dummy to Dummy pad pitch is 80 um . Dummy to normal pad pitch is 80 um.

144 110 60
145 60 110

146 to 289 40 110

290 60 110
291 110 60

292 to 316 110 40

317 110 60

All pad 14 (Typ.)

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128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0755

COG Align Key Coordinate ILB Align Key Coordinate

30µm 30µm 30µm

(+4503,+893

30

µ

m 30

µ

m 30

µ

m

30µm 30µm 30µm

(-3965,-485)

60
m 30

m

42µm 108µm

(-4668, +943)

µ

µ

42

µ

m 108

µ

m

42µm108µm

(+4121, +394)

42

µ

m 108

µ

m

TOM(TEG On Main chip) Coordinate

The TOM has test items for process evaluation. There are many bumped PADs in this area as
like main chip. So when designing COG pattern, ITO pattern must be prohibited on this area
(TOM). If ITO pattern is used for routing over this area, it can be happened pattern-short
through bumped PAD on TOM.

220um

(4153.0, 200.0)

(3933.0, -400.0)

4

600um

S6B0755 PRELIMINARY SPEC. VER. 1.0 128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

PAD CENTER COORDINATES

Table 2. Pad Center Coordinates

[Unit: µm]

NO. Name X Y NO. Name X Y NO. Name X Y NO. Name X Y

1 DUMMY -4070 -925 51 VSS2 -560 -925 101 V2 2940 -925 151 COM1 3990 893
2 TEST1 -3990 -925 52 VSS2 -490 -925 102 V2 3010 -925 152 COM0 3930 893
3 TEST2 -3920 -925 53 VSS2 -420 -925 103 V2 3080 -925 153 COMS 3870 893
4 TEST3 -3850 -925 54 VSS2 -350 -925 104 V2 3150 -925 154 SEG0 3810 893
5 TEST4 -3780 -925 55 VOUT -280 -925 105 V1 3220 -925 155 SEG1 3750 893
6 VSS -3710 -925 56 VOUT -210 -925 106 V1 3290 -925 156 SEG2 3690 893
7 VDD -3640 -925 57 VOUT -140 -925 107 V1 3360 -925 157 SEG3 3630 893
8 VDD -3570 -925 58 VOUT -70 -925 108 V1 3430 -925 158 SEG4 3570 893

9 PS0 -3500 -925 59 VOUT 0 -925 109 V0 3500 -925 159 SEG5 3510 893
10 VSS -3430 -925 60 VOUT 70 -925 110 V0 3570 -925 160 SEG6 3450 893
11 VDD -3360 -925 61 VOUT 140 -925 111 V0 3640 -925 161 SEG7 3390 893
12 PS1 -3290 -925 62 VOUT 210 -925 112 V0 3710 -925 162 SEG8 3330 893
13 VSS -3220 -925 63 C3+ 280 -925 113 VR 3780 -925 163 SEG9 3270 893
14 CS1B -3150 -925 64 C3+ 350 -925 114 VR 3850 -925 164 SEG10 3210 893
15 VDD -3080 -925 65 C3+ 420 -925 115 VSS 3920 -925 165 SEG11 3150 893
16 VDD -3010 -925 66 C3+ 490 -925 116 VSS 3990 -925 166 SEG12 3090 893
17 RESETB -2940 -925 67 C1- 560 -925 117 DUMMY 4070 -925 167 SEG13 3030 893
18 RS -2870 -925 68 C1- 630 -925 118 DUMMY 4618 -881 168 SEG14 2970 893
19 VSS -2800 -925 69 C1- 700 -925 119 COM31 4618 -801 169 SEG15 2910 893
20 RW_WR -2730 -925 70 C1- 770 -925 120 COM30 4618 -741 170 SEG16 2850 893
21 E_RD -2660 -925 71 C1+ 840 -925 121 COM29 4618 -681 171 SEG17 2790 893
22 VDD -2590 -925 72 C1+ 910 -925 122 COM28 4618 -621 172 SEG18 2730 893
23 DB0 -2520 -925 73 C1+ 980 -925 123 COM27 4618 -561 173 SEG19 2670 893
24 DB1 -2450 -925 74 C1+ 1050 -925 124 COM26 4618 -501 174 SEG20 2610 893
25 DB2 -2380 -925 75 C2+ 1120 -925 125 COM25 4618 -441 175 SEG21 2550 893
26 DB3 -2310 -925 76 C2+ 1190 -925 126 COM24 4618 -381 176 SEG22 2490 893
27 DB4 -2240 -925 77 C2+ 1260 -925 127 COM23 4618 -321 177 SEG23 2430 893
28 DB5 -2170 -925 78 C2+ 1330 -925 128 COM22 4618 -261 178 SEG24 2370 893
29 DB6 -2100 -925 79 C2- 1400 -925 129 COM21 4618 -201 179 SEG25 2310 893
30 DB7 -2030 -925 80 C2- 1470 -925 130 COM20 4618 -141 180 SEG26 2250 893
31 VDD -1960 -925 81 C2- 1540 -925 131 COM19 4618 -81 181 SEG27 2190 893
32 VDD -1890 -925 82 C2- 1610 -925 132 COM18 4618 -21 182 SEG28 2130 893
33 VDD -1820 -925 83 C4+ 1680 -925 133 COM17 4618 39 183 SEG29 2070 893
34 VDD -1750 -925 84 C4+ 1750 -925 134 COM16 4618 99 184 SEG30 2010 893
35 VDD -1680 -925 85 C4+ 1820 -925 135 COM15 4618 159 185 SEG31 1950 893
36 VDD -1610 -925 86 C4+ 1890 -925 136 COM14 4618 219 186 SEG32 1890 893
37 VDD -1540 -925 87 VSS 1960 -925 137 COM13 4618 279 187 SEG33 1830 893
38 VCI -1470 -925 88 REF 2030 -925 138 COM12 4618 339 188 SEG34 1770 893
39 VCI -1400 -925 89 VEXT 2100 -925 139 COM11 4618 399 189 SEG35 1710 893
40 VCI -1330 -925 90 VDD 2170 -925 140 COM10 4618 459 190 SEG36 1650 893
41 VCI -1260 -925 91 INTRS 2240 -925 141 COM9 4618 519 191 SEG37 1590 893
42 VCI -1190 -925 92 VSS 2310 -925 142 COM8 4618 579 192 SEG38 1530 893
43 VCI -1120 -925 93 V4 2380 -925 143 COM7 4618 639 193 SEG39 1470 893
44 VCI -1050 -925 94 V4 2450 -925 144 DUMMY 4618 719 194 SEG40 1410 893
45 VCI -980 -925 95 V4 2520 -925 145 DUMMY 4370 893 195 SEG41 1350 893
46 VSS1 -910 -925 96 V4 2590 -925 146 COM6 4290 893 196 SEG42 1290 893
47 VSS1 -840 -925 97 V3 2660 -925 147 COM5 4230 893 197 SEG43 1230 893
48 VSS1 -770 -925 98 V3 2730 -925 148 COM4 4170 893 198 SEG44 1170 893
49 VSS1 -700 -925 99 V3 2800 -925 149 COM3 4110 893 199 SEG45 1110 893
50 VSS2 -630 -925 100 V3 2870 -925 150 COM2 4050 893 200 SEG46 1050 893

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128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0755

Table 2. Pad Center Coordinates (Continued)

[Unit: µm]

NO. Name X Y NO. Name X Y NO. Name X Y

201 SEG47 990 893 251 SEG97 -2010 893 301 COM49 -4618 99
202 SEG48 930 893 252 SEG98 -2070 893 302 COM50 -4618 39
203 SEG49 870 893 253 SEG99 -2130 893 303 COM51 -4618 -21
204 SEG50 810 893 254 SEG100 -2190 893 304 COM52 -4618 -81
205 SEG51 750 893 255 SEG101 -2250 893 305 COM53 -4618 -141
206 SEG52 690 893 256 SEG102 -2310 893 306 COM54 -4618 -201
207 SEG53 630 893 257 SEG103 -2370 893 307 COM55 -4618 -261
208 SEG54 570 893 258 SEG104 -2430 893 308 COM56 -4618 -321
209 SEG55 510 893 259 SEG105 -2490 893 309 COM57 -4618 -381
210 SEG56 450 893 260 SEG106 -2550 893 310 COM58 -4618 -441
211 SEG57 390 893 261 SEG107 -2610 893 311 COM59 -4618 -501
212 SEG58 330 893 262 SEG108 -2670 893 312 COM60 -4618 -561
213 SEG59 270 893 263 SEG109 -2730 893 313 COM61 -4618 -621
214 SEG60 210 893 264 SEG110 -2790 893 314 COM62 -4618 -681
215 SEG61 150 893 265 SEG111 -2850 893 315 COM63 -4618 -741
216 SEG62 90 893 266 SEG112 -2910 893 316 COMS1 -4618 -801
217 SEG63 30 893 267 SEG113 -2970 893 317 DUMMY -4618 -881
218 SEG64 -30 893 268 SEG114 -3030 893
219 SEG65 -90 893 269 SEG115 -3090 893
220 SEG66 -150 893 270 SEG116 -3150 893
221 SEG67 -210 893 271 SEG117 -3210 893
222 SEG68 -270 893 272 SEG118 -3270 893
223 SEG69 -330 893 273 SEG119 -3330 893
224 SEG70 -390 893 274 SEG120 -3390 893
225 SEG71 -450 893 275 SEG121 -3450 893
226 SEG72 -510 893 276 SEG122 -3510 893
227 SEG73 -570 893 277 SEG123 -3570 893
228 SEG74 -630 893 278 SEG124 -3630 893
229 SEG75 -690 893 279 SEG125 -3690 893
230 SEG76 -750 893 280 SEG126 -3750 893
231 SEG77 -810 893 281 SEG127 -3810 893
232 SEG78 -870 893 282 COM32 -3870 893
233 SEG79 -930 893 283 COM33 -3930 893
234 SEG80 -990 893 284 COM34 -3990 893
235 SEG81 -1050 893 285 COM35 -4050 893
236 SEG82 -1110 893 286 COM36 -4110 893
237 SEG83 -1170 893 287 COM37 -4170 893
238 SEG84 -1230 893 288 COM38 -4230 893
239 SEG85 -1290 893 289 COM39 -4290 893
240 SEG86 -1350 893 290 DUMMY -4370 893
241 SEG87 -1410 893 291 DUMMY -4618 719
242 SEG88 -1470 893 292 COM40 -4618 639
243 SEG89 -1530 893 293 COM41 -4618 579
244 SEG90 -1590 893 294 COM42 -4618 519
245 SEG91 -1650 893 295 COM43 -4618 459
246 SEG92 -1710 893 296 COM44 -4618 399
247 SEG93 -1770 893 297 COM45 -4618 339
248 SEG94 -1830 893 298 COM46 -4618 279
249 SEG95 -1890 893 299 COM47 -4618 219
250 SEG96 -1950 893 300 COM48 -4618 159

6

S6B0755 PRELIMINARY SPEC. VER. 1.0 128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

PIN DESCRIPTION

POWER SUPPLY

Table 1. Power Supply Pins

Name I/O Description

VDD Supply Power supply

VSS1

VSS2

V0
V1
V2
V3
V4

Supply

I/O

Ground
NOTE: VSS1 and VSS2 must be shorted to external wire.

LCD driver supplies voltages
The voltage determined by LCD pixel is impedance converted by an operational amplifier
for application.
Voltages should have the following relationship;
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
When the internal power circuit is active, these voltages are generated as following table
according to the state of LCD bias.

LCD bias

1/N bias

NOTE: N = 4 to 9

V1

(N-1) / N x V0

V2 V3 V4

(N-2) / N x V0 (2/N) x V0 (1/N) x V0

LCD DRIVER SUPPLY

Table 2. LCD Driver Supply Pins

Name I/O Description

C1- O Capacitor 1 negative connection pin for voltage converter

C1+ O Capacitor 1 positive connection pin for voltage converter

C2- O Capacitor 2 negative connection pin for voltage converter
C2+ O Capacitor 2 positive connection pin for voltage converter
C3+ O Capacitor 3 positive connection pin for voltage converter
C4+ O Capacitor 4 positive connection pin for voltage converter

VOUT I/O Voltage converter input / output pin

VCI I

VR I

Voltage converter input voltage pin
Voltages should have the following relationship: VDD ≤ VCI ≤ V0

V0 voltage adjustment pin
It is valid only when on-chip resistors are not used (INTRS = "L")

REF I

VEXT I

Selects the external VREF voltage via VEXT pin

− REF = "L": using the external VREF

− REF = "H": using the internal VREF

Externally input reference voltage (VREF) for the internal voltage regulator
It is valid only when REF is "L".

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128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0755

SYSTEM CONTROL

Table 3. System Control Pins

Name I/O Description

Internal resistors select pin
This pin selects the resistors for adjusting V0 voltage level.

INTRS I

TEST1

to

TEST4

− INTRS = "H": use the internal resistors

− INTRS = "L": use the external resistors

VR pin and external resistive divider control V0 voltage.
Test pins

I

Don’t use these pins.

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S6B0755 PRELIMINARY SPEC. VER. 1.0 128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

MICROPROCESSOR INTERFACE

Table 4. Microprocessor Interface Pins

Name I/O Description

RESETB I

PS0 I

PS1 I

CS1B

RS I

RW_WR I

Reset the input pin
When RESETB is "L", initialization is executed.
Parallel/Serial data input select input

PS0

H Parallel RS DB0 to DB7

L Serial RS or None SID(DB7) Write only SCLK(DB6)

*NOTE: When PS is "L", DB0 to DB5 are high impedance and E_RD and RW_WR
must be fixed to either "H" or "L".

Microprocessor interface select input pin

− PS0 = “H” , PS1 = "H": 6800-series parallel MPU interface

− PS0 = “H” , PS1 = "L": 8080-series parallel MPU interface

− PS0 = “L” , PS1 = "H": 4 Pin-SPI serial MPU interface

− PS0 = “L” , PS1 = "L": 3 Pin-SPI serial MPU interface

Chip select input pins

I

Data/instruction I/O is enabled only when CS1B is "L" . When chip select is non-active,
DB0 to DB7 may be high impedance.

Register select input pin

− RS = "H": DB0 to DB7 are display data

− RS = "L": DB0 to DB7 are control data

Read / Write execution control pin

PS1 MPU Type RW_WR Description

H 6800-series RW

L 8080-series /WR

Interface

Mode

Data/

Instruction

Data Read / Write Serial Clock

E_RD

RW_WR

Read/Write control input pin

− RW = "H": read

− RW = "L": write

Write enable clock input pin
The data on DB0 to DB7 are latched at the rising
edge of the /WR signal.

-

9

128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0755

Table 6 (Continued)

Name I/O Description

Read / Write execution control pin

PS1 MPU Type E_RD Description

Read/Write control input pin

− RW = "H": When E is "H", DB0 to DB7 are in an

E_RD I

H 6800-series E

output status.

− RW = "L": The data on DB0 to DB7 are latched at
the falling edge of the E signal.

Read enable clock input pin

L 8080-series /RD

When /RD is "L", DB0 to DB7 are in an output
status.

8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data

DB0

to

DB7

I/O

bus. When the serial interface selected (PS0 = "L");

− DB0 to DB5: high impedance

− DB6: serial input clock (SCLK)

− DB7: serial input data (SID)

When chip select is not active, DB0 to DB7 may be high impedance.

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S6B0755 PRELIMINARY SPEC. VER. 1.0 128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

LCD DRIVER OUTPUTS

Table 5. LCD Driver Outputs Pins

Name I/O Description

LCD segment driver outputs
The display data and the M signal control the output voltage of segment driver.

SEG0

to

SEG127

COM0

to

COM63

COMS

(COMS1)

Display data M (Internal)

H H V0 V2

O

LCD common driver outputs
The internal scanning data and M signal control the output voltage of common driver.

O

O

Common output for the icons
The output signals of two pins are same. When not used, these pins should be left open.

H L VSS V3

L H V2 V0
L L V3 VSS

Power save mode VSS VSS

Scan data M (Internal) Common driver output voltage

H H VSS
H L V0

L H V1
L L V4

Power save mode VSS

Segment driver output voltage

Normal display Reverse display

NOTE: DUMMY – These pins should be opened (floated).

11

128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0755

FUNCTIONAL DESCRIPTION

MICROPROCESSOR INTERFACE

Chip Select Input

There are CS1B for chip selection. The S6B0755 can interface with an MPU only when CS1B is "L" . When these
pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be
high impedance. And, in case of serial interface, the internal shift register and the counter are reset.

Parallel / Serial Interface

S6B0755 has four types of interface with an MPU, which are two serial and two parallel interface. This parallel or
serial interface is determined by PS 0pin as shown in Table 6.

Table 6. Parallel / Serial Interface Mode

PS0 Type CS1B PS1 Interface mode

H Parallel CS1B

L Serial CS1B

Parallel Interface (PS0 = "H")

The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS1 as shown in
Table 7. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in Table 8.

Table 7. Microprocessor Selection for Parallel Interface

PS1 CS1B RS E_RD RW_WR DB0 to DB7 MPU bus

H CS1B RS E RW DB0 to DB7 6800-series

L CS1B RS /RD /WR DB0 to DB7 8080-series

Table 8. Parallel Data Transfer

Common 6800-series 8080-series Description

RS

H H H L H Display data read out
H H L H L Display data write

L H H L H Register status read
L H L H L Writes to internal register (instruction)

E_RD

(E)

RW_WR

(RW)

E_RD

(/RD)

H 6800-series MPU mode

L 8080-series MPU mode

H 4 Pin-SPI MPU mode

L 3 Pin-SPI MPU mode

RW_WR

(/WR)

NOTE: When E_RD pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In
this case, interface data is latched at the rising edge of CSB and the type of data transfer is determined by
signals at RS, RW_WR as in case of 6800-series mode.

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S6B0755 PRELIMINARY SPEC. VER. 1.0 128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

Serial Interface (PS0 = "L")

When the S6B0755 is active(CS1B=”L”), serial data (DB7) and serial clock (DB6) inputs are enabled. And not
active, the internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication may be
controlled either via software or the Register Select(RS) Pin, based on the setting of PS1. When the RS pin is
used (PS1 = “H”), data is display data when RS is high, and command data when RS is low. When RS is not used
(PS1 = “L”), the LCD Driver will receive command from MPU by default. If messages on the data pin are data
rather than command, MPU should send Data Direction command(11101000) to control the data direction and
then one more command to define the number of data bytes will be write. After these two continuous commands
are send, the following messages will be data rather than command. Serial data can be read on the rising edge of
serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. And the DDRAM
column address pointer will be increased by one automatically. The next bytes after the display data string is
handled as command data.

Serial Mode PS0

PS1 CS1B RS

Serial-mode with RS pin L H CS1B Used

Serial-mode with software

command

L L CS1B Not used

4 Pin-SPI Interface (PS0 = "L" , PS1 = "H")

CS1B

SID

SCLK

RS

DB6DB7DB0DB1DB2DB3DB4DB5DB6DB7

Figure 3. 4 Pin SPI Timing (RS is used)

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128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0755

3 Pin-SPI Interface (PS0 = "L" , PS1 = "L")

To write data to the DDRAM, send Data Direction Command in 3-Pin SPI mode. Data is latched at the rising edge
of SCLK. And the DDRAM column address pointer will be increased by one automatically.

CS1B

829 830 831

SCLK

SID

0 0 1 7 8

~

~

3 Byte (1) 2 Byte (2) 128 Byte

Page

MSB

23

LSB DDC

~

~

15

~

~

No. of

DATA

0

~

~

Data In

(1) Set Page and Column Address.

Set Page Address : 1 0 1 1 P3 P2 P1 P0
Set Column Address MSB : 0 0 0 1 0 Y6 Y5 Y4
Set Column Address LSB : 0 0 0 0 Y3 Y2 Y1 Y0

(2) Set DDC(Data Direction Command) and No. of Data Bytes.

Set Data Direction Command( For SPI mode Only):

1 1 1 0 1 0 0 0

Set No. of Data Bytes(DDL)

: D7 D6 D5 D4 D3D2D1D0

Figure 4. 3 Pin SPI Timing (RS is not used)

This command is used in 3-Pin SPI mode only. It will be two continuous commands, the first byte controls the data
direction and informs the LCD driver the second byte will be number of data bytes will be write. After these two
commands sending out, the following messages will be data. If data is stopped in transmitting, it is not valid data.
New data will be transferred serially with most significant bit first.

Notes:

l In spite of transmission of data, if CS1B will be disable, state terminates abnormally. Next state is

initialized.

l DDL Register value “0” à “1” , “127” à “128”. (decimal value)

Busy Flag

The Busy Flag indicates whether the S6B0755 is operating or not. When DB7 is "H" in read status operation, this
device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor
needs not to check this flag before each instruction, which improves the MPU performance.

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S6B0755 PRELIMINARY SPEC. VER. 1.0 128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

D(N)

D(N+1)

D(N+2)

N

N+1

N+2

N+3

Data Transfer

The S6B0755 uses bus holder and internal data bus for Data Transfer with the MPU. When writing data from the
MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Figure 5. And
when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder
(dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in Figure

6. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of
address sets is executed. Therefore, the data of the specified address cannot be output with the read display data
instruction right after the address sets, but can be output at the second read of data.

MPU signals

RS

/WR

DB0 to DB7

Internal signals

/WR

BUS HOLDER

COLUMN ADDRESS

MPU signals

RS

/WR

/RD

DB0 to DB7

Internal signals

/WR

N D(N) D(N+1) D(N+2) D(N+3)

N D(N) D(N+1) D(N+2) D(N+3)

N N+1 N+2 N+3

Figure 5. Write Timing

N

Dummy D(N) D(N+1)

/RD

BUS HOLDER

COLUMN ADDRESS

N

Figure 6. Read Timing

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128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0755

- -

- -

- -

- -

001

- -

0

011

- -

0

101

- -

0

000

- -

1

DISPLAY DATA RAM (DDRAM)

The Display Data RAM stores pixel data for the LCD. It is 65-row by 128-column addressable array. Each pixel
can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8
lines and the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page
directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD
common lines as shown in Figure 7. The microprocessor can read from and write to RAM through the I/O buffer.
Since the LCD controller operates independently, data can be written into RAM at the same time as data is being
displayed without causing the LCD flicker.

DB0
DB1
DB2
DB3
DB4

1 0 0 - - 1

COM0

COM1
COM2
COM3
COM4

- -

Display Data RAM LCD Display

Figure 7. RAM-to-LCD Data Transfer

Page Address Circuit

This circuit is for providing a Page Address to Display Data RAM shown in Figure 9. It incorporates 4-bit Page
Address register changed by only the "Set Page" instruction. Page Address 8 (DB3 is "H", DB2, DB1 and DB0 is
"L") is a special RAM area for the icons and display data DB0 is only valid.

Line Address Circuit

This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by
setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing
the contents of on-chip RAM as shown in Figure 9 & Figure 10. It incorporates 7-bit Line Address register
changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame,
the contents of register are copied to the line counter which is increased by CL signal and generates the Line
Address for transferring the 128-bit RAM data to the display data latch circuit. However, display data of icons are
not scrolled because the MPU can not access Line Address of icons.

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S6B0755 PRELIMINARY SPEC. VER. 1.0 128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

Column Address Circuit

Column address circuit has a 7-bit preset counter that provides column address to the Display Data RAM as
shown in Figure 9. When set Column Address MSB / LSB instruction is issued, 7-bit [Y6:Y0] is updated. And,
since this address is increased by 1 each a read or write data instruction, microprocessor can access the display
data continuously. And the Column Address counter is independent of page address register.

ADC Select instruction makes it possible to invert the relationship between the column address and the segment
outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC Select instruction. Refer to
the following Figure 8.

SEG output

SEG

0

SEG

1

SEG

2

SEG

3

... ...

SEG

124

SEG

125

SEG

126

SEG

127

Column address [Y6:Y0] 00H 01H 02H 03H ... ... 7CH 7DH 7EH 7FH

Display data 1 0 1 0 1 1 0 0

LCD panel display

... ...

( ADC = 0 )

LCD panel display

( ADC = 1 )

... ...

Figure 8. The Relationship between the Column Address and the Segment Outputs

Segment Control Circuit

This circuit controls the display data by the Display ON / OFF, reverse display ON / OFF and entire display ON /
OFF instructions without changing the data in the display data RAM.

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128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0755

Page Address

DB3 DB0DB1DB2

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

Data

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

Page 0

Page 1

Page 2

Page 3

Line

Address

00H
01H
02H
03H
04H
05H
06H
07H
08H

09H
0AH
0BH
0CH
0DH
0EH

0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH

initial line

register = 00H

1/65

Duty

1/57

Duty

COM

Output

COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8

COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19

COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

Column

Address

LCD Output

ADC=0
ADC=1

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0

Page 5

Page9

Page 6

Page 7

Page 8

00

01 02 03 04 05 7A 7B 7C 7D 7E 7F

SEG1

SEG0

SEG2

SEG3

SEG4

SEG5

- - - - -

- - - - -

SEG123

SEG122

SEG124

01020304057A7B7C7D7E7F

SEG126

SEG125

00

SEG127

28H
29H
2AH
2BH
2CH
2DH
2EH

2FH

30H
31H
32H
33H

34H
35H
36H
37H
38H

39H
3AH
3BH
3CH
3DH
3EH

3FH

- - - - -

Figure 9. Display Data RAM Map (Initial Line Address = 00H)

Initial start line address = 00H

COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59

COM60
COM61
COM62
COM63

COMS

18